Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0264—Arrangements for coupling to transmission lines
  • H04L25/028—Arrangements specific to the transmitter end
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0008—Arrangements for reducing power consumption
  • H03K19/0019—Arrangements for reducing power consumption by energy recovery or adiabatic operation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0264—Arrangements for coupling to transmission lines
  • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission

Definitions

• This invention relates to electronic circuits.
• this invention relates to improving the performance of a type of electronic driver circuit the operation of which is intended to reduce power consumption.
• This invention relates to achieving low power consumption in such driver circuits, whilst at the same time producing desirable signal characteristics.
• Fig. la shows a conventional CMOS inverting driver 10 formed as part of an IC.
• Output driver 10 generates an inverted driver output voltage VDO in response to a driver input voltage signal VI.
• Driver 10 is connected through electrical conductor 12 printed wiring board (PWB) to load circuitry 14.
• PWB printed wiring board
• electrical conductor 12 converts driver output voltage VDO into conductor output voltage VBO that drives a group of one or more digital ICs 16 in load 14.
• Driver 10 is formed with N-channel insulated gate field effect transistor ('FET') QA and P-channel insulated gate FET QB whose gate electrodes receive driver input voltage VI.
• the sources of FET QA and QB respectively are connected to a source of low supply voltage VSS, typically ground reference (0 volts) and a source high supply voltage VDD.
• the QA and QB drains are connected together to provide driver output voltage VDO.
• N-channel FET QA is turned on by raising input voltage VI to suitably high level.
• FET QB is turned on by reducing input voltage VI to a suitably low level. Accordingly, only one of FETs QA and QB is conductive during steady state operation.
• output voltage VDO is at a high value close to VDD when input voltage VI is low and causes FET QB to be turned on.
• the "on" resistance of each of FET QA and QB is normally quite low. Consequently output signal VDO makes a rapid transition from VSS to VDD in response to a rapid transition of input signal VI from high to low. Likewise output signal VDO makes a rapid transition from VDD to VSS in response to a rapid transition of input signal VI from low to high. During a transition there is a typically a brief period when both FETs QA and QB are conductive.
• PWB electrical conductor 12 commonly referred to as an interconnect, consists of copper track and a ground plane at the VSS potential.
• the steps shown in the line passing through conductor 12 in Fig. la qualitatively represent the changes in direction that conductor 12 makes on the PWB.
• the ground plane is represented by the block slanted shading.
• Fig. lb is a simplified electrical model, it does not show the parasitic lead inductances which typically exist when driver 10 is formed as part of an integrated circuit which is contained within an in integrated circuit package which is in turn mounted on a PWB. These parasitic inductances must be accounted for in the design of driver 10 if an undesirable effect known as ground/power bounce is to be avoided.
• Interconnect 12 in Fig. la or lb having distributed inductance and capacitance is alternatively known as a transmission line having characteristic impedance Z0.
• RON in Fig. lb is ideally chosen to match Z0 so that a half amplitude outward bound wave is launched initially which doubles its amplitude on reaching load 14 and reflects back towards driver 10 as a full amplitude wave. In the absence of RON or if RON is too small, the reflected wave is of an amplitude exceeding the level of VDD and causing signal integrity problems.
• Figs. 2a and 2b show how the resonant line driver can equivalently replace conventional line driver of Figs la and lb.
• Fig. 2b for example shows a CMOS implementation of a resonant line driver.
• Ql and Q3 can connect the driver output VDO to low and high voltage sources VSS and VDD respectively as in a conventional driver.
• Q2 can connect driver output VDO also to an intermediate voltage source VHH during transitions.
• Gate electrodes (and therefore switching of Ql, Q2 & Q3) are controlled by control circuit 20 via signals VCl, VC2 & VC3 respectively.
• Ql and Q3 are N channel MOSFET (NMOS) transistors, they provide a conductive path when VCl and VC3 respective are at a high voltage level.
• Q2 is a P channel MOSFETs (PMOS) transistor it provides a conductive path when VC2 respective is at a low voltage level.
• Fig. 3 shows that intermediate voltage supply VHH can be supplied by a reservoir capacitor CR.
• Fig. 4 shows waveforms representative of the operation of the circuit shown in Fig. 2b when CL is much larger than CB and CL and LB act more like a sinusoidally LC resonant system than a transmission line. Initially only Ql is “ON” and VDO is at a low level. Then in response to a change of level of the input signal VI at time tl Ql is switched “OFF” while Q2 is switched “ON” driving VDO near to the level of VHH. Current builds sinusoidally to a maximum and then falls back to zero whilst at the same time the voltage seen at the load VBO swings sinusoidally to the level of VDD at which point control circuit 20 switches Q2 "OFF” and switches Q3 "ON” to complete the transition. As shown in Fig. 4, the circuit operates in a similar manner to produce the opposite polarity transition
• Fig. 5 shows waveforms resulting from the equivalent sequence of events when CL is smaller than or of a similar value to CB, in which case the transmission line character of CB and LB is more clearly evident.
• Ql is switched "OFF” while Q2 is switched “ON” driving VDO near to. the level of VHH.
• An outward bound (or incident) wave of voltage amplitude equivalent to VHH travels along the transmission line. When it reaches the load, and since the load is reasonably small and cannot provide a significant path for the current in the incident wave, a reflected wave results tending to cancel the current of the incident wave.
• This reflected wave is also of amplitude equivalent to VHH but adds to the incident wave to give a voltage level at the load equal to VDD.
• the reflected wave travels back toward driver 18 until the whole length of the transmission line is at the level of VDD by time t2, being the time when the reflected wave actually reaches the driver 18, at which point control circuit 20 switches Q2 "OFF” and switches Q3 "ON” to complete the transition.
• Control circuit 20 can be designed in a variety of ways to control the timing of this to coincide with the return of the reflected wave.
• the timing for the current transition of VDO can be determined by observing and storing some characteristic of a previous transition to make adjustments to some circuit capable of storing and reproducing timed sequences, for example a digitally controlled delay line controlled by a digital counter.
• Resonant Line Drivers have the potential to both reduce power consumption and produce well conditioned signal without ringing and overshoot. Unfortunately though, when certain unavoidable characteristics of typical physical implementations are taken into account, whilst low power consumption can be achieved, signal conditioning may be poor.
• Fig. 6 shows the circuit of Fig. 3 but modified to make it more representative of a real physical implementation.
• driver 18 is formed on silicon chip which is in turn contained in a chip package in turn mounted onto PWB 12.
• reservoir capacitor CR may be contained within the chip or chip package.
• Fig. 3 shows driver 18, PWB 12 and load 14 all sharing a common voltage reference level VSS. In an actual physical implementation this is often not the case since as shown in Fig.
• driver 18 would normally be part of an IC not only driving output signals but also receiving input signals.
• the input signals have considerable capacitance coupling with VSSB and VDDB, their levels tend to be determined in reference to VSSB and VDDB so that for example an input signal which is nominally at a low level will present to its receiver on the aforementioned IC, a voltage spike very similar to that shown for VSSB in Fig. 7 at time tl . This causes the possibility of the input signal being temporarily interpreted as being at a high level.
• all the change in output current from driver 18 in Fig. 6 is supplied from VSSD either via reservoir capacitor CR & Q2 in Fig. 2b or through Ql in Fig.
• an electronic driver circuit for generating a circuit output signal providable to an electrical conductor that furnishes a conductor output signal providable to a load where the circuit and conductor output signals respectively making corresponding circuit and conductor output transitions approximately between a pair of output voltage levels between which there is an intermediate voltage level.
• Inductance and capacitance of the conductor and the load produce resonance that enables the conductor output signal to largely complete each conductor output transition while the circuit output signal is being held at approximately the intermediate voltage level for a non-zero intermediate-level holding period during the corresponding circuit output transition.
• the circuit includes at least a first capacitor element between the intermediate voltage level and each of the first and second voltage levels and at least a second capacitor element (preferably equal to the first capacitor element, e.g. a ) between the intermediate voltage level and the second voltage level.
• the first and second capacitor elements may form a split-reservoir capacitor.
• a package lead inductance may exist between the electrical conductor and a source of each of the pair of output voltage levels.
• the first and second capacitor elements are preferably such that a change in circuit output voltage causes return current flowing back into the driver to be split approximately equally between the package lead inductances.
• the first and second capacitor elements may provide decoupling capacitance between the output voltage levels.
• an electronic driver circuit for generating a circuit output signal providable to an electrical conductor that furnishes a conductor output signal providable to a load.
• the circuit and conductor output signals respectively make corresponding circuit and conductor output transitions approximately between a pair of output voltage levels between which there is an intermediate voltage level.
• Inductance and capacitance of the conductor and the load produce resonance that enables the conductor output signal to largely complete each conductor output transition while the circuit output signal is being held at approximately the intermediate voltage level for a non-zero intermediate-level holding period during the corresponding circuit output transition.
• the circuit comprising a ramp control circuit for controlling partial circuit output transitions between at least one of the pair of output voltage levels and the intermediate level to provide a substantially non-zero transition time for a partial circuit output transition.
• the partial circuit output transition is preferably controlled to be slow relative to other switching events in the circuit.
• a pull-up transistor and a pull-down transistor may be provided for pulling the circuit output up to a first of the two output voltage levels and down to a second of the two output voltage levels, in which case the partial circuit output transition is controlled to be slower than the switching of the pull-up and pull-down transistors.
• An intermediate level driving transistor can be provided, which, in switching- on drives the circuit output up to the intermediate voltage level and in switching-off permits the circuit output to be driven up to a first of the two output voltage levels. In this case the partial circuit output transition is controlled to be slower than the switching-off of the intermediate level driving transistor.
• the partial circuit output transition time is preferably adjustable, for example it is controllable as a function of the time taken for the conductor output signal to largely complete a conductor output transition.
• the control circuitry may comprise time-comparison circuitry for comparing the circuit output signal and the second control signal to determine whether the circuit output signal completes a circuit output transition before the second control signal completes the corresponding control transition and adjustment circuitry for adjusting the partial circuit transition time depending on the comparison.
• the comparator circuit preferably compares a level of the partial circuit output transition with a reference voltage that is approximately midway between the intermediate voltage level and an output voltage level to which the output is transitioning at a time approximately midway between a start of the partial circuit output transition and an expected completion of the partial circuit output transition.
• reference ramp circuitry may be provided for generating a reference ramp, together with comparator circuitry coupled to the reference ramp circuitry for comparing a partial circuit output transition with the reference ramp.
• the time taken for a partial circuit transition is preferably controlled as a function of characteristics (e.g. characteristics determined from relative timing of two signals) of at least one previous circuit output transition.
• the ramp control circuit controls a partial circuit output transition as a function of a current stored control value stored as a result of a previous partial circuit output transition.
• an electronic driver circuit for generating a circuit output signal providable to an electrical conductor that furnishes a conductor output signal providable to a load.
• the circuit and conductor output signals respectively make corresponding circuit and conductor output transitions approximately between a first voltage, a second voltage and an intermediate voltage between the first and second voltages.
• the circuit comprises: a first transistor having (a) a first flow electrode coupled to a source of the first voltage, (b) a second flow electrode coupled to an output node from which a circuit output signal is provided, and (c) a control electrode responsive to a first control signal for controlling current flow between the first transistor's flow electrodes; a second transistor having (a) a first flow electrode coupled to a source of the second voltage, (b) a second flow electrode coupled to the output node, and (c) a control electrode responsive to a second control signal for controlling current flow between the second transistor's flow electrodes; and a third transistor having (a) a first flow electrode coupled to a source of the intermediate voltage, (b) a second flow electrode coupled to the output node, and (c) a control electrode responsive to a third control signal for controlling current flow between the third transistor's flow electrodes.
• Fourth and fifth transistors are connected between the control electrode of the third transistor and the sources of the first and second voltage levels respectively.
• Control circuitry selectively discharges the control electrode of the third transistor to the first and second voltage levels respectively through the fourth and fifth transistors such that the control electrode makes partial transitions between the first and second voltage levels.
• the output signal makes rising and falling circuit output transitions approximately between the first and second voltages controlled by the first, second and third control signals, and the circuit output signal stays approximately at the intermediate voltage for a non-zero intermediate-level holding period during each circuit output transition.
• the split reservoir (or other) capacitor reduces ground and power reference differences (known as ground and power bounce) between a chip containing a resonant driver and the PWB on which it is mounted.
• the split reservoir capacitor also provides power and ground decoupling.
• the invention provides for a controlled slew rate ramp initiating an incident or outbound wave or turn-on and circuit methods for this.
• the invention provides for the time taken to complete the controlled slew rate ramp to be adjusted approximately proportionately in time with the intermediate voltage holding period of the resonant driver.
• a further aspect of the current invention lies in matching the "ON" resistance of the driver pull-up and pull-down transistors (for example Q3 and Ql in Fig. 2b) approximately to the characteristic impedance interconnect 12.
• a still further aspect of the invention relates to means for determining a feedback control signal to adjust the internal delay of a resonant line driver.
• Figs. 1 to 3 represent prior art resonant line driver circuits.
• Figs. 4 and 5 are timing diagrams illustrating the operation of the circuit of Fig. 2b for different values of CL.
• Fig. 6 represents a resonant line driver similar to that of Fig. 3 in a typical physical environment.
• Fig. 7 is a timing diagram for the circuit of Fig. 6.
• Fig. 8 represents a resonant line driver in accordance with a first embodiment of the invention.
• Figs. 9 to 11 are timing diagrams illustrating the operation of the circuit of Fig. 8.
• Fig. 12 represents a resonant line driver in accordance with a second embodiment of the invention.
• Fig. 13 is a timing diagram illustrating the operation of the circuit of Fig. 12.
• Fig. 14 represents a resonant line driver in accordance with a third embodiment of the invention.
• Figs. 15 and 16 are timing diagrams illustrating the operation of the circuit of Fig. 14.
• Fig. 17 is a diagram of a control circuit suitable for use in the circuit of Fig. 12 or Fig. 14 or other embodiments.
• Fig. 18 illustrates a prior art control circuit.
• Fig. 19 is a timing diagram for explanation of the operation of a resonant line driver in accordance with the second aspect of the invention.
• Fig. 20 illustrates a control circuit suitable for use in accordance with the second aspect of the invention.
• Fig. 21 expands upon Fig. 19.
• Fig. 22 illustrates a control circuit alternative to that of Fig. 20.
• Fig. 23 represents a resonant line driver in accordance with a further embodiment.
• Fig. 24 is a timing diagram for the circuit of Fig. 23.
• Fig. 25 illustrates in greater detail a comparator suitable for use in the circuit shown in Fig. 23.
• Fig. 8 it shows a circuit similar to that in Fig. 6 but instead of the reservoir capacitance being supplied entirely between the VSSD and VHHD circuit nodes, the reservoir capacitor is split into two capacitances CR1 and CR2.
• CR1 provides capacitance between NSSD and NHHD while CR2 provides capacitance between NDDD and VHHD. Since each of CR1 and CR2 provides reservoir capacitance in parallel, each of CR1 & CR2 can be made half the numerical size of CR in Fig. 6 to provide the same effective reservoir capacitance.
• a split reservoir capacitor driver 19 in Fig. 8 is made more symmetrical so when a change in voltage of driver output signal VDO causes current to flow into or out of interconnect 12, a return current flows back into driver 19 split equally between package lead inductances LPL1 & LPL2.
• Fig. 9 shows waveforms that occur in relation to the circuit of Fig 8. Comparing Fig. 7 with Fig. 9, whereas at time tl in Fig. 7 since in Fig. 6 all return current flows through LPL2 giving a large offset between VSSB and VSSD, at time tl in Fig. 9 both VSSB and VDDB are offset approximately equally from VSSD and VDDD respectively but by a smaller amount since in the circuit of Fig. 8 any return current is split equally between package lead inductances LPL1 an LPL2. As a further benefit, the series combination of LPL1 and LPL2 provides a very useful degree of decoupling capacitance between VSSD and VDDD. For example, at time t2 in Fig.
• a second element of the current invention provides for a controlled slew rate ramp when at time tl, driver output signal is driven from the level of VSSD to VHHD.
• the positive going ramp takes output signal VDO smoothly at a controlled rate from the level of VSSD at time tl nearly to the level of VHHD at time tla and a negative going ramp takes output signal VDO smoothly at a controlled rate from the level of VDDD at time t3 nearly to the level of VHHD at time t3a.
• the ramp is generated by a circuit of low output impedance so that the amplitude and duration of the ramp is largely unaffected by the degree of loading on output signal VDO.
• a controlled ramp considerably reduces the rate of change of current output from the driver and therefore the rate of change of return current through for example LPLl and LPL2 and results in considerable reduction of power and ground bounce, as shown in Fig. 10 and yet adds only a small delay to the overall transit of the signal from source to load.
• control circuit 20 disconnects output VDO from VHHD and connects it to VDDD via pull-up transistor for example Q3 in Fig. 2b. If Q3 is sized such that its "ON" resistance is matched to the characteristic impedance of the transmission line then the driver output voltage VDO smoothly approaches the level of VDDD without overshoot or undershoot to complete the transition.
• Q3 is sized such that its "ON" resistance is matched to the characteristic impedance of the transmission line then the driver output voltage VDO smoothly approaches the level of VDDD without overshoot or undershoot to complete the transition.
• a similar sequence commences at time t3 in the opposite polarity transition and likewise Ql in Fig.2b can be sized such that its "ON" resistance is matched to the characteristic impedance of the transmission line.
• a disadvantage of the controlled ramp method is that a reduced portion of total charge for the transition is supplied from the reservoir capacitor.
• the shade areas under the IHH and IDD curves show the relative proportions of charge deliver from the VHHD node (i.e. reservoir capacitor) and VDDD power supply node.
• VHHD node i.e. reservoir capacitor
• VDDD power supply node the remaining 25% coming from the VDDD power supply.
• Fig. 10 dotted lines
• the use of a controlled ramp leads to a slightly higher power consumption, though still much lower than a conventional driver but improves signal integrity and ground/power bounce.
• the ramp circuit is made controllable (i.e. capable of delivering ramp times of variable duration within a range, and if the ramp time is controlled by the same circuit control mechanism used in control circuit 20 to adjust the intermediate level holding period of the resonant line driver, then the driver can operate over a range of load conditions (i.e. can drive load with varying transmission line delay or LC resonant frequency) and still produce waveforms which represent close to an optimum chosen compromise between, on the one hand power consumption and speed and on the other hand signal integrity.
• load conditions i.e. can drive load with varying transmission line delay or LC resonant frequency
• Fig. 12 shows a resonant line driver 118 comprising a first embodiment of a ramp control circuit 118. Comparing it with the circuit in Fig. 2b, NMOS transistor Q2 has been replaced by a pair of transistors Q2N (an NMOS device) and Q2P (a PMOS device) with their respective channels connected in parallel. At the beginning of a transition of output signal VDO the gate of Q2N is charged (positively) by a flow of current from current mirror Q21/Q20 when Q22 switches “ON", and at the same Q24 is turned “OFF” whilst the gate of Q2P is charge (negatively) by a flow of current from current mirror Q31/Q30 when Q32 switches "ON” and at the same Q34 is turned “OFF”.
• PMOS transistor Q2P In a LOW to HIGH transition, for example that commencing at time tl in Fig. 13, PMOS transistor Q2P is initially not conducting even after its gate electrode begins to fall because its channel cannot switch "ON" until the gate electrode become more negative than VHH.
• NMOS device Q2N on the other hand becomes conductive as soon as its gate electrode becomes more positive than VDO by at least the threshold voltage of Q2N. It will be seen that Q2N is therefore initially in a source follower configuration. During the ramp time signal, VDO is pulled gradually higher by a very low impedance, since a source follower configuration gives a very low output resistance.
• Q2P does eventually switch "ON” after the ramp is substantially complete and helps to attain a low overall "ON" resistance for Q2N and Q2P in parallel combination.
• both Q2N and Q2P are rapidly switched “OFF", while pull-up transistor Q3 is switched “ON”.
• Q2P which switches "ON” first in source follower mode
• Q2N which switches "ON” later so that the same pattern of operation occurs as described in relation the LOW to HIGH transition.
• Varying the value of current reference IREF allows variable ramp rates to be generated.
• FIG. 12 shows a resonant line driver comprising an alternative ramp control circuit 119 using a single NMOS device Q2 in place of the parallel combination of Q2N and Q2P in Fig. 12.
• Q2 can again be driven in a source follower mode to generate a variable ramp.
• the gate of Q2 is again charged during LOW-HIGH ramp when Q22 switches “ON” current mirror Q21/Q20 and at the same Q24 is turned “OFF”.
• the reference current for mirror Q21/Q20 comes in turn from current mirror Q30/Q31, which is in turn controlled by current reference IREFOUT.
• Q2 cannot be used as a source follower but is effectively configured as a common source switch which would normally switch "ON" very abruptly when the gate became more positive than VHH by an amount equal to the threshold voltage of Q2.
• a feedback capacitor CFB is place between output signal VDO and the input to mirror Q41/Q40, then the ramp rate generates a rate dependent current feedback which subtracts from reference current IREFOUT.
• the circuit uses negative feedback to control the ramp rate to depend on the reference current input, since if the ramp is too slow the gate voltage will build at the input to mirror Q41/Q40 tending to correct the rate to that desired. In effect therefore the ramp again has a low output impedance.
• capacitor CFB can be described as checking the rate of rise of the current to the control electrode of transistor Q2 when the circuit output signal falls from VDD to VSS.
• a drawback with the circuit of Fig. 14 is that on HIGH-LOW transitions there is an appreciable delay from beginning to charge the gate of Q2 to the point where Q2 first becomes conductive until driver output NDO begins to move. As shown in Fig. 16. however, during the period when VDO is high, it is not necessary to discharge the gate of Q2 to the level of VSSD in order to switch Q2 "OFF". If the gate is discharged only to VHHD as shown in Fig. 16, Q2 will still be switched “OFF” but can be switched “ON” again much more quickly at the start of the next HIGH-LOW transition. This can be achieved by replacing Q24 in Fig.
• the gate of Q2 can be first discharged to VSSD and then pre- charged to the level of VHHD only before HIGH-LOW transitions.
• Fig. 17 shows a block diagram of a control circuit 120 in which the same current reference controls both the intermediate level holding period of a resonant line driver via controllable delay Dl and provides current IREFOUT to a ramp circuit (for example in driver 119 of Fig. 14) so that the ramp period tracks the intermediate level holding period for chosen optimum over a range of timing conditions.
• IREFOUT can be adjusted according to some characteristic of a previous transition as described in the prior art.
• Fig. 18 shows a control circuit described in US patent No. 6,201,420, in which the duration of the intermediate level holding period is set by the value of an up/down counter 32, in turn controlled by a comparator circuit 30 which compares the timing of circuit output signal VDO with control signal VC2 to produce feedback signal RP.
• 2 comparator 30 is designed to compare the relative timing of two fast transitioning signals and may be unreliable or inaccurate for use in a resonant line driver using a controlled ramp as described previously.
• a further aspect of the current invention therefore provides a means of adjusting the intermediate level holding for resonant line drivers using a controlled ramp.
• Fig. 19, for clarity, shows only the low-to-high transition of a resonant line driver using a controlled ramp.
• Time t3 is the time of the transitioning of control signals VC3 and VE2N as determined by the control circuitry.
• An element of the current invention is the positioning of an optimum timing for the transitioning of control signals VC3 and VE2N at t3 such that it coincides as nearly as possible with initial reflection.
• output signal VDO rises with approximately the same slope starting from time t3 as it does during the initial ramp starting at time tl. This optimum timing is depicted by voltage waveform VDOO in Fig. 19.
• signal VDO rises more quickly than the initial ramp beginning at time tl as indicated by waveform VDOE. Conversely, when initial reflection arrives late in relation to time t3, signal VDO rises with a slope similar to the initial ramp at time tl but commencing some time after time t3 as depicted by waveform VDOL.
• Control circuit 128 contains latching comparator circuit 132 which has level sensitive inputs receiving signals NDO and NREF and furnishes digital output signal U/D to an ⁇ -bit up/down counter 130 in response to clock signal input NIDD.
• Signal U/D is set to a logic "high” on the rising edge of NIDD if at that time signal NDO has a higher voltage than signal VREF or to a logic "low” on the rising edge of VIDD if at that time signal VDO has a lower voltage than signal VREF.
• Signal U/D controls the ⁇ -bit up/down counter 130 such that if signal U/D is at a logic “high” during the logic “high” to logic “low” transition of input signal VI then the counter value increments. Conversely if signal U/D is at a logic “low” during the logic “high” to logic “low” transition of input signal VI then the counter value decrements.
• Counter 130 in turns controls digitally controlled delay circuit 134 such that input signal VI is delayed in time by an amount dependent upon the current value stored by counter 130.
• Signal VID the delayed version of signal VI
• delay circuit 134 receives the transitioning of output signals VE2 ⁇ , VC3 and VCl at time t3 in Fig. 21.
• Current controlled delay circuit 136 further delays signal VID to produce signal VIDD which transitions at time t4 in Fig. 21.
• Signal VIDD in turn is the clocking signal for latching comparator 132.
• Delay circuit 136 is controlled by an output of current source 126 which supplies current IREF such that the greater the value of IREF the shorter the delay produced by delay circuit 136.
• Current source 126 furnishes a second equal or proportional current to output IREFOUT which in turn can control the rise time of the ramp beginning at time tl in Fig. 21.
• output signal VDO rises with approximately the same slope starting from time t3 as it does during the initial ramp starting at time tl, as depicted by waveform VDDO.
• Delay circuit 136 is arranged to produce a delay always equal to approximately one half of the duration of the ramp commencing at time tl in Fig. 21.
• Input signal VREF on the other hand has a potential approximately midway between the potential of VHHD and VDDD as shown in the figure.
• waveform VDOO results such that its potential approximately equals VREF at time t4 producing an indeterminate output U/D from latching comparator 132.
• latching comparator 132 will drive its output signal, U/D to a logic "high” or logic “low” respectively. Since signal U/D controls the timing of signal VID and hence the positions of time t3 in Fig. 21 via counter 130 and delay circuit 134 in Fig. 20, the overall operation of the circuit is such that output signals VE2N, VC3 and VCl are controlled to occur at or near an optimum time.
• latching comparator 132, up/down counter 130 and digitally controlled delay 134 together comprise elements of a control loop or more specifically a delay locked loop when used as the control circuit in a resonant line driver.
• Fig. 22 shows control circuit 138. which is similar to control circuit 128 in Fig. 20 but differs in that digitally controlled delay 134 in of control circuit 128 is replaced by current controlled delay 135 in control circuit 138. Furthermore delay 135 is controlled by a current supplied from digitally controlled current source 140 in place of fixed current source 126 in control circuit 128. Digitally controlled current source 140 supplies several equal or proportional output currents whose magnitudes are controlled as some function of the n-bit binary control input supplied by up/down counter 130 in control circuit 138, but typically the output currents of current source 140 are substantially proportional or inversely proportional to the binary value control input supplied by counter 130.
• control circuit 138 can supply additional control currents IREFOUT and IREFOUT 1 which are proportional to the control input current to current controlled delay 135.
• IREFOUT in Fig. 22 can be used to control the rise time of a ramp circuit allowing the ramp period to track the intermediate level holding period in a resonant line driver. The further usefulness of IREFOUT 1 is described later. As described in relation to control circuit 128 in Fig.
• control circuit 138 likewise contains current controlled delay 136, the purpose of which is to provide clock signal VIDD to latching comparator circuit 132 such that signal VDO is compared at time t3 to reference voltage VREF as shown in Fig. 21.
• Voltage VREF and time t3 typically have their intersection as shown in Fig. 21 coinciding with waveform VDOO so that waveform VDOE can be discriminated from waveform VDOL to produce loop feedback signal U/D.
• a particular difficulty when physically implementing control circuits 128 or 138 may be in designing latching comparator 132 to work at sufficiently high speed and providing it with reference and clocking inputs of sufficient precision.
• voltage levels VHHD and VDDD are shown as time invariant, in a physical implementation both VDDD and VHHD are subject to change, particularly the level of VHHD when it is supplied from a reservoir capacitor. Therefore the choice of appropriate level for VREF in relation to the current and immediately prior levels of VHHD and VDDD and circuitry required to furnish signal VREF may become quite complex issues.
• the timing of signal VIDD in control circuits 128 or 138 needs to be accurate and repeatable to a degree which may prove hard to achieve.
• latching comparator 132 in control circuits 128 or 138 notionally compares the voltage of signal VDO to the voltage of signal VREF at a single instant on the rising " edge of clocking signal VIDD.
• that comparator will tend to compare the values of inputs signal VDO and VREF averaged throughout the time duration of a sampling window, approximately (though not precisely) coinciding with the rising edge of clocking input signal VIDD.
• improved means are provided for furnishing loop feedback signal U/D in control circuit 128 and 138. This is achieved in part by redefining the inputs to latching comparator 132 to demand less precision and in part by providing an internal circuit for latching comparator 132 which is novel and particular to the application and further relaxes the timing accuracy demanded of clocking signal VIDD.
• Fig. 23 shows an alternative resonant line driver comprising a control circuit 138, a ramp circuit 119 similar to that shown in Fig. 14, output MOSFET's Ql, Q2 and Q3 and additional circuitry comprising N-channel MOSFET Q2R and capacitor CRAMP.
• Capacitor CRAMP furnishes a' signal VREFRAMP which functions as described below.
• the source and drain terminals of N-Channel MOSFET Q2R are connected to signals VHHD and VREFRAMP respectively.
• reference current output IRFEOUTl from control circuit 138 initially charges capacitor CRAMP high to the voltage level of VDD.
• N-Channel MOSFET Q2R turns "ON", discharging capacitor CRAMP and signal REFRAMP to the level of VHHD. Then at time immediately prior to time t3, signal VC2 falls.
• Waveform VREFRAMP has a slope between time t3 and t5 that is arranged to be substantially the same as waveform VDDO in Fig. 21.
• the slope of signal VREFRAMP between time t3 and t5 is proportional to the reference current IREFOUTl, which is in turn proportional to the reference current IREFOUT, which (through ramp circuit 119) substantially determines the slope of the VDO ramp beginning at time tl. Therefore the slope of signal VREFRAMP between times t3 and t5 can be arranged to be always substantially the same as the slope of the ramp of output signal VDO beginning at time tl, and when signals VDO and VREFRAMP are compared at any time between t3 and t5 by latching comparator 132 (Fig.
• a loop feedback signal U/D can be furnished, which very accurately discriminates waveform VDOE of output signal VDO from waveform VDOL of output signal VDO.
• up/down counter 130 and digitally controlled current source 140 allow current controlled delay 135 in control circuit 138 (all shown in Fig. 22) to be adjusted very close to an optimum value.
• this figure shows an integrating latching comparator 150 with comparator inputs VREFRAMP and VDO and furnishing comparator outputs Q and QN. Integrating latching comparator 150 also accepts a reference current IREF and latching control signals VE2N, EXTENT and EXTENT_NOT where suitable. Example timing of for these control signals is shown in the lower part of Fig. 24.
• the input stage of integrating latching comparator 150 comprises capacitors
• N-channel MOSFETs Q105 and Q106 act as source followers with bias current supplies by N- channel MOSFETs Q102 and Q103 and therefore capacitors CCOMPl and CCOMP2 track the voltage levels of input signals VREFRAMP and VDO shifted lower by the gate-source bias voltage of Q105 and Q106.
• signal EXTENT goes to a high level
• N-channel MOSFET Q104 is switched "ON" and shorts source terminals of N-channel MOSFETs Q105 and Q106 so that they now function as a differential pair with bias current again supplied by N-channel MOSFETs Q102 and Q103.
• the output current of the differential pair flows to output nodes Q and QN so that when, shortly before time t3 in Fig.
• VE2N goes to a high level and Q109, Ql 10 and Ql 11 are switched “OFF", this output current begins charging output nodes Q and QN and associated capacitance (provided mainly by the gate capacitance of P-channel MOSFETs Q107 and Q108 and N-channel MOSFETs Ql 12 and Ql 13).
• the current source formed by Q102 and Q103 is arranged to supply only a modest amount of current so that even if VE2N happens relatively far in advance of time t3, output nodes Q and QN remain quite near to the level of VDDD and thus the relative timing of VE2N is non-critical in relation to time t3 save that it should go to a low level in advance of time t3.
• the integrating latching comparator 150 has a positive input VDO which receives the partial output transition, and a negative input VREFRAMP which receives a signal corresponding to (i.e. representative of) a reference ramp.
• the integrating latching comparator accumulates charge on the comparator output nodes (Q and QN) only during a time when either of the two input signals is rising. It provides an average comparison over the whole ramping period, i.e. over the time of the partial output transition.
• a positive feedback regeneration circuit comprising the transistors Q 107 to Ql 14 receives charge at the comparator output nodes Q and QN via the differential input transistor pair.
• the regeneration circuit takes a small difference on nodes Q and QN, and, when EXTENTNOT causes Q 114 to conduct, it amplifies this small difference to a full rail voltage.
• Capacitors CCOMPl and CCOMP2 are sized such that charging them requires quite a large current in relation to the modest bias current supplied by Q 102 and Q103 so that the total bias current through the differential pair formed by Q 105 and Q106 becomes quite large, but only while input signals VDO and VREFRAMP continue to rise.
• the circuit therefore embodies an inherent feature which tends to integrate the difference voltage between inputs VREFRAMP and VDO only during their respective ramp period between time t3 and t5 in Fig. 24. This feature further relaxes the timing precision required of control input signals to integrating latching comparator 150. By time t5 in Fig.
• control signal EXTENTJMOT is non- critical in relation to time t5 in Fig. 24, save that it should occur after time t5.
• the final state of output signals Q & QN will be such that one is at the level of VDDD and the other at the level of VSSD depending on the time integrated difference voltage between input signals VREFRAMP and VDO between time t3 and t5 in Fig. 24.
• Integrating latching comparator 150 along with suitable circuitry to furnish control signals EXTENT and EXTENT_NOT could therefore replace latching comparator 132 in control circuit 138 of Fig. 23 with one of its output signal Q or QN chosen for appropriate logic polarity furnishing loop feedback signal U/D in Fig. 23.

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• 2003
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• 2004
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