WO2004097642A1 - Systeme de traitement numerique incorpore avec exploitation auto-configuree - Google Patents

Systeme de traitement numerique incorpore avec exploitation auto-configuree Download PDF

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Publication number
WO2004097642A1
WO2004097642A1 PCT/EP2003/050133 EP0350133W WO2004097642A1 WO 2004097642 A1 WO2004097642 A1 WO 2004097642A1 EP 0350133 W EP0350133 W EP 0350133W WO 2004097642 A1 WO2004097642 A1 WO 2004097642A1
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WO
WIPO (PCT)
Prior art keywords
processing device
counter
timer
configuration
operating unit
Prior art date
Application number
PCT/EP2003/050133
Other languages
English (en)
Inventor
Eberhard Amann
Andreas Arnez
Walter Pietschmann
Jürgen SAALMÜLLER
Original Assignee
International Business Machines Corporation
Ibm Deutschland Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation, Ibm Deutschland Gmbh filed Critical International Business Machines Corporation
Priority to AU2003233799A priority Critical patent/AU2003233799A1/en
Priority to PCT/EP2003/050133 priority patent/WO2004097642A1/fr
Priority to TW093109087A priority patent/TW200517860A/zh
Publication of WO2004097642A1 publication Critical patent/WO2004097642A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1417—Boot up procedures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4406—Loading of operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/142—Reconfiguring to eliminate the error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1438—Restarting or rejuvenating

Definitions

  • the present invention generally concerns digital processing devices and systems that have to be configured for operation and more particularly to an embedded digital processing device or system and an according method for self-configured operation.
  • Data processing devices like Application Specific ⁇ Integrated Circuits (ASICs) , field programmable Gate Arrays and embedded controllers are often used as data processing systems "embedded” in another device like a mobile phone or a washing machine have to be configured to solve certain tasks.
  • ASICs Application Specific ⁇ Integrated Circuits
  • field programmable Gate Arrays and embedded controllers are often used as data processing systems "embedded” in another device like a mobile phone or a washing machine have to be configured to solve certain tasks.
  • each configurable logic element in the array itself is capable of performing any one of a plurality of logic functions depending upon control information placed in the configurable logic element.
  • Each configurable logic element can have its function varied even after it is installed in a system, only by changing the control information placed in that element. In particular, it is provided access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system (environment) of which the array is a part.
  • the underlying concept of the invention there are provided at least two sets of configuration information stored in a configuration unit.
  • the underlying device or system finds autonomously one configuration set out of these multiple sets which allows the device or system to operate correctly together with an external environment.
  • the required properties of that environment are gathered by means of a sensing mechanism preferably implemented in an operating unit of the device or system or a corresponding sensor interface interoperating with the operating unit.
  • a set of configuration which fits with a given environment is selected by means of a mismatch mechanism, in particular a time-out mechanism, where the available configuration sets are loaded and checked for interoperability of the underlying device or system with the given environment and where a resulting mismatch and corresponding time-out for a particular configuration set does not reveal a system stop but moreover an automatic loading of another configuration set until an appropriate configuration of the device or system is achieved.
  • a mismatch mechanism in particular a time-out mechanism
  • the invention enables devices and systems herein addressed to self-configure during initial boot-up so that they can adapt to different hardware and/or software environments or interface applications.
  • a side effect of the present solution is that those devices or systems can even be made more reliable in their start-up and operational state.
  • the proposed mechanism of self-configuration eliminates the requirement of human interaction or interaction by an external device, as required in state of the art solutions and thus is much more flexible as the prior art solutions and suitable for autonomous applications.
  • Fig. 1 is a block diagram illustrating the basic features of a digital processing device according to the present invention
  • Fig. 2 is a block diagram illustrating an embedded controller device in accordance with the present invention
  • Fig. 3 is a schematic illustration of an initial boot operation in accordance with the present invention.
  • Fig. 4 is another block diagram illustrating a communication hub device as an exemplary ASIC having implemented a self-configuring mechanism and according hardware features in accordance with the present invention.
  • the basic principles of the present invention are illustrated in the block diagram of Fig. 1. Beneath the shown digital processing device 100 an external environment 105 is depicted by the dotted line 110.
  • the shown digital processing device 100 is an adaptive system in regard of its self-configuring ability. This self-configuring ability will be well-understood by the following functional description.
  • the device 100 particularly consists of an operating unit 115, a timer 120, a counter 125 and a configuration unit 130 which altogether interact with each other.
  • the operating unit 115 in the present embodiment, shares a set of actor interfaces 135 - 145 and sensor interfaces 150 - 160 with the external environment 105.
  • These interfaces 135 - 160 principally can be any type of communication interfaces to interact with the external environment 105, the present device 100 is part of.
  • the shown processing device 100 is only illustrative and thus can be any embedded controller, hardware-driven state-machine, field-programmable and configurable Gate Arrays or the like which require a shown configuration unit 130 that contains structured information (data) to set up the operating unit 115 at the initial start-up phase of the device to a defined state corresponding to the task the operating unit 115 has to fulfil.
  • the configuration unit 130 does provide not only one set of configuration information for the operating unit 115 but rather multiple of those sets. Those multiple configuration sets can consist of the same or variable content. More particularly, for the different application scenarios mentioned above, a preferred configuration set for an embedded controller is a boot image stored in a persistent memory device that will be executed after power-on or reset. For a hardware-driven state-machine, a preferred configuration set is a register set that influences the sequence such state-machine will execute in response to sensor signals it receives via the sensor interfaces 150 - 160, which sensors to value and what actors to activate via the actor interfaces 135 - 145 with what attributes (e.g. high, low level signal, pulse etc.) .
  • attributes e.g. high, low level signal, pulse etc.
  • a preferred configuration set describes in which way the functional elements in the Gate Array will interact with each other to obtain a higher level of operation or operation performance out of the Gate Array.
  • Those functional elements of the Gate Array can be a configurable microprocessor core, a communication adapter or the like.
  • the above device set-up allows for self-configuration of the shown hardware device in order to run applications with different requirements.
  • several sets of configurations are provided in the configuration unit 130 that are loaded one after the other and tested for matching criteria for successfully running the application.
  • a 'Configuration Start' signal transmitted via line 165 to the timer 120 triggers start of the timer 120 and thus of the following procedural steps.
  • the 'Configuration Start' signal is also transferred to an 'OR' gate 175 as a trigger signal to start the operating unit via line 190.
  • the output of the timer 120 is attached to the counter 125 and, in parallel, to the mentioned 'OR' gate 175 via line 180, as a second trigger signal.
  • the counter 125 gets incremented each time the timer 120 expires.
  • the operating unit 115 and configuration unit are only triggered via lines 190, 195 for the following operational steps if the timer 120 reaches its final value and restarts which means it stays 'active' .
  • This active state of the timer 120 can only be stopped by means of a 'Stop Timer' signal transferred via line 185 to the timer 120.
  • Via lines 200 - 215, the timer 120 and the counter 125 step through the set of configurations provided by the configuration unit 130. While the number of different configurations to address in the configuration unit 130 determines the number of lines 200 - 215, in the present case of e.g.
  • the counter 125 provides a 4 bit counter signal via the lines 200 - 215 to the configuration unit 130 wherein each set is addressed by the possible values of the counter signal.
  • the operating unit 115 gets loaded with a configuration set currently selected by means of the counter signal 200 - 215 via line 220. Having loaded that current configuration, the operating unit 115 tries to run the application based on such configuration within the external environment 105 in order to check if certain criteria are met to keep the actual configuration. If these criteria are met, the timer 120 gets stopped by means of the 'Stop Timer' signal delivered via line 185 and the processing device 100 stays in the current mode of operation selected.
  • the timer reaches its final value (exhausts) , wraps and restarts with an initial setting. At the same time it generates the trigger for the counter 125 to step the configuration set as well as by means of the 'OR' function 175 to restart the operating unit 115 and bringing the configuration unit 130 to an operational state if necessary.
  • FIG. 2 illustrates a more detailed embodiment of the present invention in an embedded controller 300 with an above described self-configuring functionality.
  • An embedded controller is based typically on a system on a chip device that includes a microprocessor core and several peripheral control elements for communication, sense and control like UART, I 2 C busses, digital I/O signals.
  • the embedded controller device may also include integrated memory in type of fast read/writeable memory (RAM) and persistent memory (ROM, Flash- ROM) . Both types of memory can typically also be attached external to those controller devices.
  • RAM fast read/writeable memory
  • ROM persistent memory
  • Flash- ROM Flash-ROM
  • bootstrap load from this persistent storage.
  • program for bootstrap contained in the persistent storage either initializes the system in a way that it can fetch a further control program via a communication path (e.g. Local Area Network) or loads a real time operating system (RTOS) or similar multitasking operating system (e.g. Linux) from further persistent storage and starts it up.
  • RTOS real time operating system
  • Linux multitasking operating system
  • the embedded controller should depending on the application boot different control programs / applications specific for an actual configuration. It is state of the art to have different configurable load images for such bootstrap by switching the memory range of the persistent storage to a different image either by a manually activated jumper or by use of an external controller put in charge by a human interface to emulate such jumper.
  • the mechanism and device described herein gives a solution for those scenarios where an embedded controller gets autonomous by an improved boot mechanism so it operates more reliable in high availability and stand alone applications as well as allows for adaptation of the bootstrap to different configurations. That mechanism allows for an automated switching between different boot images without any direct or indirect manual interaction.
  • the controller 300 depicted in Fig. 2 also includes a timer 305 and a counter 310 function that get attached to the embedded controller 300 either internally, as in the present embodiment, or externally.
  • the combination of the timer 305 and the counter 310 influences the boot behaviour of an operating unit 315 ("processor core" in the present embodiment) that is implemented in the embedded controller 300.
  • the timer 305 is attached to the counter 310 via signal line 320.
  • the counter 310 gets incremented each time the timer expires.
  • the output of the counter 310 is connected to a logic element 325, in the present embodiment a logical AND and/or OR and/or XOR function, via lines 330 - 345.
  • a logic element 325 in the present embodiment a logical AND and/or OR and/or XOR function
  • lines 330 - 345 define a counter signal of arbitrary bit width depending on the number of configuration sets that may be selected.
  • the processor core 315 is attached to a memory controller 350 via a system memory bus 355.
  • the memory controller 350 is attached to an, in the present embodiment externally arranged, storage device 360, e.g. a Flash ROM. It is emphasized that the storage device 360, in the present embodiment, serves as configuration unit including multiple configuration sets for the operation of the processor core 315.
  • the memory controller 350 is connected to the storage device 360 via two different buses: An address bus 365, 370, 375 interconnecting the memory controller 350 with the external storage device 360, a part of which via the mentioned logic element 325, and a data bus 380 that also serves for transfer of certain control signals as discussed hereinafter.
  • the amount or number of address lines 375 to be influenced by the counter 310 is determined by the size of memory that shall be moved to a different location in address range.
  • the timer 305 when expiring, causes a configurable reset to the processor core 315 and the embedded controller 300. If the timer 305 gets not stopped by execution of an underlying application by the processor core 315, it continues its operation thus generating multiple time-outs and counter increments .
  • the actual counter value acts on the selection of a configuration set in the storage device 360 by the logic element 325 which, in the present embodiment, is implemented as AND and/or OR and/or XOR function.
  • the logic element 325 operates as an address translation function between the addresses applied by the processor core 315 and the location selected in the storage device 360 under control of the counter 310.
  • the present timer 305 and the subsequent counter 310 are driving the sequence of the self-configuration.
  • the timer 305 preferably is implemented as count down timer that causes the counter 310 to change its state each time the timer 305 expires and reaches a value of zero.
  • the timer 305 may wrap each time it expires and restart with its initial value until a timer stop signal is generated by the processor core 315 and transmitted to the timer 305 by means of a timer control register 385 via transmission lines 390 and 395.
  • the counter 310 interacts with the storage device 360 in such a way that, depending on the actual value of the counter 310 and the respective address generated by the logic element 325, one specific set from n available sets is selected for configuring the processor core 315.
  • the self-configuration mechanism of the embedded controller 300 gets started by a trigger signal ('Configuration Start') that activates a first configuration sequence.
  • a trigger signal can be generated by applying power-on reset 400 to the embedded controller 300 or by some external event 405 or by some internal event 410 via an 'OR' gate 415.
  • the processor core 315 is triggered too via transmission line 420, 425 and another 'OR' gate 430.
  • the processor core 315 interacts with the external storage device 360 (configuration unit) to get a configuration set stored therein to be executed. Which set of the multiple sets stored in the storage device 360 gets applied is determined by the actual setting of the counter, as described beforehand. By the same trigger signal 400, 405 or 410 the timer 305 gets started from an initial value input via lines 435 to count down. If the processor core 315 accomplishes to reach a certain state interacting with the external environment 105 (shown in Fig. 1 and not depicted in Fig. 2) by the actor interface 135 - 145 and sensor interface 150 - 160, it generates the above mentioned 'Timer Stop' signal and stays in operation with this configuration set.
  • the processor core 315 does not reach this state of operation, e.g. due to a wrong configuration set for a task or failure of a selected configuration set or wrong settings for the actor/sensor interfaces etc. to set the 'Timer Stop' signal, the timer 305 will expire and generate a signal to move the counter 310 forward one step as well as restart the configuration sequence by passing a reset signal through the delay element 445 and the "OR" function 430 to the processor core 315. This process of stepping through different sets of configurations takes place until a configuration is executed successfully to generate the mentioned 'Timer Stop' signal.
  • the above described timer 305 required for getting the timeout signal to step through the different configuration sets may be implemented in hardware or software and may be controllable in software by the timer control register 385.
  • the initial value 435 of the timer 305 is either loaded by a hard-coded internal or external setting at power-on or by a register programmable value while other types of reset do not influence setting of the register carrying the timer setting.
  • the timer control register 385 is read/writeable by the processor core 315 to stop, restart the timer 305 as well as setting and changing a delay the timer 305 lasts. Furthermore the setting of the counter 310 which counts for the time-outs and which may have an initial value 440 of zero after power-on can get changed by the timer control register 385 too.
  • the timer control register 385 in addition, allows for reading back the actual state of the counter 310 to allow for the software to determine which configuration set is actually selected. But the timer control register 385 may not be affected by any type of reset except power-on reset.
  • the timer 305 gets activated. While the timer 305 is counting down, the processor core 315 will start with typical bootstrap-specific program execution from persistent storage. If bootstrap executes successfully so far there will be a point in program execution where the timer 305 gets stopped by setting the deactivation signal through the timer control register 385. While the timer 305 is deactivated, no further action takes place from the timer 305 and program execution continues with the configuration set currently selected. For cases where a special guard is required during program execution to prevent the processor core 315 from a fault condition, the timer 305 can also get reactivated by software.
  • the timer 305 expires after the above mentioned preset value.
  • the timer 305 generates a 'Time-Out' signal which, in turn, generates a certain type of reset which may be a system reset or only a partial reset to the processor core 315 to restart.
  • this type of initiated reset may be programmable by the timer control register 385 or any equivalent register.
  • this reset may be split into several reset signals with different timings 445 (Delay 1, 2) to allow for certain functions like Flash-ROM or network devices to recover from a non-accessable state (e.g. Flash-ROM in write state) before the processor starts to fetch first instructions from such a device.
  • the 'Time-Out' signal also applies to the counter 310 insofar as the counter 310 is incremented. Since the output of the counter 310 is logically interconnected with some addresses of the address bus 365/370, the actual setting of the counter 310 operates like an aforementioned address translation. So by leaving the reset state, the processor core 315, after each time-out, addresses a different address range in the same or a different persistent storage element attached to the address bus 365. Which addresses need to become influenced by the counter 310 through the logic element 325 is determined by the code size of the bootstrap loader and/or the size of the operating system to be loaded.
  • a boot image has an image size of close to but less than 1 MByte and should get a back-up or alternate image faded in with the same size
  • that address line needs to get toggled by the counter 310 in case the timer 305 expires which switches the address range on the 1 MByte boundary.
  • the logic element- 325 is realized as AND gate, OR gate or XOR gate depends on the type of relocation that should take place in respect to the start address the processor core 315 applies after 'Reset' .
  • Fig. 3 where four different configuration sets consisting of four different boot images 545, 550, 555 and 560 are depicted.
  • the four possible time-outs of the timer 305 are designated by reference numerals 520, 525, 530 and 535 wherein the last time-out - 1 (
  • condition 535 reveals the first boot image to be reloaded again.
  • the counter 310 also may wrap when the highest value is reached so that the sequence starts over and continues with the very first image to start with. By doing so the controller can get synchronized to external dependencies e.g. a network that is temporarily not or not yet available but come up at a later time.
  • the different boot images contained in one configuration set 545, 550, 555, 560 are addressed by using a schematically depicted "address range" 540.
  • the view of the storage layout by the processor core 315 influenced by the logic element 325 is shown in the layouts 500 - 515 where the toggling of the counter 310 'moves' each time a different boot image 545 - 560 to the start address of the processor.
  • Fig. 4 shows another embodiment of the present invention implemented in an Application Specific Integrated Circuit (ASIC) .
  • the shown ASIC in particular, is a communication Hub device 600 that, in the present embodiment, provides protocol conversion and interface distribution in a switch-like manner.
  • the Hub device 600 therefore includes a number of different input/output (I/O) links, in the present example two Peripheral Component Interconnection (PCI) -Express links 605, 610, two Universal Serial Bus (USB) links 615, 620 and two InfiniBand links 625, 630, the latter being a communication architecture and specification for data flow between processors and I/O devices with enhanced bandwidth an almost unlimited expandability which, in the next few years, is expected to gradually replace the existing PCI shared-bus approach used in most of today's personal computers and servers .
  • PCI Peripheral Component Interconnection
  • USB Universal Serial Bus
  • the present Hub device 600 is developed too for usage in various application environments 105. Therefore different settings for the I/O links 605 - 630 may be required by an internal register set 640 located in a switch matrix 635 to fit these requirements.
  • the Hub device may also execute protocol conversion between links of different type.
  • the shown I/O Hub device 600 is able to run as an autonomous unit without need for receiving control information and/or configuration settings from a supervisory control instance.
  • the self-configuring behaviour in the present embodiment, is applied to configure the Hub device 600 for the different pre-mentioned applications.
  • the Hub device 600 receives a set of configuration information from an externally arranged persistent storage 660 after power is applied to the Hub device 600 and an external or internal reset signal is executed via an 'OR' gate 655. If a first configuration set does not configure the Hub device 600 correctly for a certain application, as in the other two embodiments, a timer 645 and counter 650 apply for a next set of configuration information to be delivered from the persistent storage 660 to the Hub device 600 and so forth.
  • a protocol converter can be included in the switch matrix 635 which is capable to detect certain control information in the data stream transferred via an active communication link 605 - 630 and thereby can also generate an internal reset to the Hub device 600 for reconfiguration.
  • configuration sets may also comprise some level of redundancy in order to provide higher reliability of the entire configuration process .

Abstract

Cette invention se rapporte à un dispositif au système de traitement numérique incorporé, qui fournit plusieurs ensembles d'informations de configuration mémorisées dans une unité de configuration, ces ensembles de configuration étant vérifiés de façon autonome, pour permettre au système ou au dispositif de fonctionner correctement en association avec un environnement externe. Cette vérification est effectuée au moyen d'un mécanisme de détection. Notamment, un ensemble de configuration qui est adapté à un environnement donné est sélectionné au moyen d'un mécanisme de désadaptation et de temporisation, dans lequel les ensembles de configuration disponibles sont chargés et vérifiés du point de vue de l'interopérabilité du dispositif ou système sous-jacent avec l'environnement donné et dans lequel une désadaptation résultante et une temporisation correspondante pour un ensemble de configuration particulier ne révèlent pas un arrêt du système mais plutôt un chargement automatique d'un autre ensemble de configuration, jusqu'à ce que la configuration appropriée du dispositif ou du système soit obtenue.
PCT/EP2003/050133 2003-04-29 2003-04-29 Systeme de traitement numerique incorpore avec exploitation auto-configuree WO2004097642A1 (fr)

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Application Number Priority Date Filing Date Title
AU2003233799A AU2003233799A1 (en) 2003-04-29 2003-04-29 Embedded digital processing system with self-configured operation
PCT/EP2003/050133 WO2004097642A1 (fr) 2003-04-29 2003-04-29 Systeme de traitement numerique incorpore avec exploitation auto-configuree
TW093109087A TW200517860A (en) 2003-04-29 2004-04-01 Embedded digital processing system with self-configured operation

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Application Number Priority Date Filing Date Title
PCT/EP2003/050133 WO2004097642A1 (fr) 2003-04-29 2003-04-29 Systeme de traitement numerique incorpore avec exploitation auto-configuree

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EP1764687A1 (fr) * 2005-09-16 2007-03-21 Moxa Technologies Co., Ltd. Procédé pour restaurer des systèmes démarragés
EP2180403A1 (fr) * 2008-10-21 2010-04-28 Moxa Inc. Système de sauvegarde qui stocke le fichier de données de démarrage de système intégré dans plusieurs sections de stockage et procédé associé
WO2011149481A1 (fr) 2010-05-28 2011-12-01 Hewlett-Packard Development Company, L.P. Initialisation de sous-système de mémoire d'unité de commande de gestion

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JP4119945B2 (ja) * 2006-08-24 2008-07-16 ネットクリアスシステムズ株式会社 タスク処理装置
TWI705371B (zh) * 2016-04-12 2020-09-21 凱銳光電股份有限公司 運作於單一作業系統之多裝置系統

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Publication number Priority date Publication date Assignee Title
EP1764687A1 (fr) * 2005-09-16 2007-03-21 Moxa Technologies Co., Ltd. Procédé pour restaurer des systèmes démarragés
EP2180403A1 (fr) * 2008-10-21 2010-04-28 Moxa Inc. Système de sauvegarde qui stocke le fichier de données de démarrage de système intégré dans plusieurs sections de stockage et procédé associé
WO2011149481A1 (fr) 2010-05-28 2011-12-01 Hewlett-Packard Development Company, L.P. Initialisation de sous-système de mémoire d'unité de commande de gestion
CN102906717A (zh) * 2010-05-28 2013-01-30 惠普发展公司，有限责任合伙企业 对管理控制器的存储器子系统进行初始化
EP2577475A1 (fr) * 2010-05-28 2013-04-10 Hewlett-Packard Development Company, L.P. Initialisation de sous-système de mémoire d'unité de commande de gestion
EP2577475A4 (fr) * 2010-05-28 2014-04-09 Hewlett Packard Development Co Initialisation de sous-système de mémoire d'unité de commande de gestion
US9870233B2 (en) 2010-05-28 2018-01-16 Hewlett Packard Enterprise Development Lp Initializing a memory subsystem of a management controller

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