WO2004070834A1 - Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method - Google Patents

Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method Download PDF

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Publication number
WO2004070834A1
WO2004070834A1 PCT/IB2004/050030 IB2004050030W WO2004070834A1 WO 2004070834 A1 WO2004070834 A1 WO 2004070834A1 IB 2004050030 W IB2004050030 W IB 2004050030W WO 2004070834 A1 WO2004070834 A1 WO 2004070834A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductor
intermediate layer
chosen
channel region
Prior art date
Application number
PCT/IB2004/050030
Other languages
French (fr)
Inventor
Robert Lander
Dirk M. Knotter
Original Assignee
Koninklijke Philips Electronics N.V.
Interuniversitair Microelektronica Centrum Vzw
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Application filed by Koninklijke Philips Electronics N.V., Interuniversitair Microelektronica Centrum Vzw filed Critical Koninklijke Philips Electronics N.V.
Priority to US10/544,412 priority Critical patent/US7157337B2/en
Priority to EP04702771A priority patent/EP1593155A1/en
Priority to JP2006502525A priority patent/JP2006518547A/en
Publication of WO2004070834A1 publication Critical patent/WO2004070834A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/976—Temporary protective layer

Definitions

  • the invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body comprising a first field effect transistor with a first source, drain and channel region of a first conductivity type and a first gate electrode which includes a first conductor and which is separated from the channel region by a dielectric layer, and comprising a second field effect transistor with a second source, drain and channel region of a second conductivity type, opposite to the first conductivity type, and a second gate electrode which includes a second conductor that is different from the first conductor, and which is separated from the channel region by a dielectric layer, wherein to form the gate electrodes a first conductor layer is applied to the semiconductor body provided with the dielectric layer, which conductor layer is subsequently removed again outside the first channel region, after which a second conductor layer is applied to the semiconductor body, and wherein, before the first conductor layer is applied, an intermediate layer is provided on the dielectric layer.
  • C)MOSFET Complementary Metal Oxide Semiconductor Field Effect Transistor
  • N- MOS transistor n-type channel region
  • P-MOS transistor p-type channel region
  • an N-metal and a P-metal are to be taken to mean a metal or metallic material whose work function is close to the Fermi level of, respectively, N-type doped and P-type doped poly crystalline silicon, the Fermi levels in question being approximately 4.15 and 5.2 eV, respectively.
  • a semiconductor body wherein two transistors are formed in, respectively, an n-type region and a p-type region in a silicon semiconductor body, is provided with a dielectric layer on which two gate electrodes of a different metal are formed as follows: first, an intermediate layer of a material such as tantalum pentoxide, silicon nitride or aluminum oxide is provided. Next, at the location of the transistor to be formed first, a first conductor layer is provided and subsequently removed again outside the region of the first gate electrode. In this case, the intermediate layer serves as an etch-stop layer. Subsequently, a second conductor layer is deposited over the semiconductor body. By means of etching, said second conductor layer is removed again outside the first gate electrode already formed and outside the second gate electrode to be formed. In this case too, the intermediate layer serves as an etch-stop layer.
  • a drawback of the known method resides in that the transistors formed by means of said method have a relatively thick gate dielectric. After all, this is formed by two layers, i.e. the dielectric layer and the intermediate layer. Also the properties of such a gate dielectric composed of two different materials are less well defined.
  • a method of the type mentioned in the opening paragraph is characterized in accordance with the invention in that for the material of the intermediate layer use is made of a material that is selectively etchable with respect to the dielectric layer, and before the first conductor layer is provided, the intermediate layer is removed at the location of the first channel region, and after the first conductor layer has been provided and removed again outside the first channel region, and before the second conductor layer is provided, the intermediate layer is removed at the location of the second channel region.
  • the invention is based on the recognition that in this manner the number of process steps to which the dielectric layer is exposed is minimized by virtue of the presence of the intermediate layer.
  • the invention is further based on the recognition that a suitable choice of the material for the intermediate layer enables said layer to be selectively removed again, using comparatively mild etching techniques, at locations where it is not required. Said selective removal taking place, in particular, without removing also an undefined part of the dielectric layer, as occurs inevitably if a metallic conductor is provided on the dielectric layer and removed again by etching. This also depends on which metal is used.
  • the intermediate layer is removed at the location of the first gate electrode to be formed, and before providing the second conductor layer, the intermediate layer is removed at the location of the second gate electrode.
  • the intermediate layer can still serve as an etch-stop layer and protect the dielectric layer outside the first transistor.
  • the gate electrodes of both transistors are present already and protecting the dielectric layer is much less necessary because the parts of the dielectric layer forming the gate dielectric are and remain covered by, respectively, the first and the second conductor layer.
  • An important advantage of the method in accordance with the invention finally is that the intermediate layer no longer fonns part of the gate dielectrics of the finished transistors. As a result, said dielectrics may be very thin and composed of a single material.
  • the intermediate layer is locally removed by means of photolithography and etching. This method is comparatively simple and fits in well with the customary technology.
  • the intermediate layer is provided with a further intermediate layer the material of which is selectively etchable with respect to the material of the intermediate layer.
  • This further intermediate layer is patterned by means of photolithography and etching. When the intermediate layer is being etched, the patterned part of the further intermediate layer can then be used as a mask.
  • there is greater freedom as regards the choice of the etchants for the conductor layer because the intermediate layer is protected by the further intermediate layer instead of by a photoresist.
  • An additional advantage in this connection is that also during the necessary removal of the photoresist, the intermediate layer is protected against the agents necessary for this operation.
  • a suitable material for the further intermediate layer is, for example, a metal such as aluminum. This is selectively etchable with respect to many materials and, in addition, many materials can be selectively removed with respect to this metal.
  • aluminum is a material that is frequently used as a connection conductor in the semiconductor technology. Thus, if aluminum is used, the method in accordance with this modification shows excellent compatibility with the customary silicon technology.
  • the most suitable choice as regards the material for the intermediate layer depends on which material is chosen for the dielectric layer. If Si0 2 is chosen as the latter material, then an intermediate layer of Si is a very suitable choice. This material can be readily selectively removed with respect to Si0 2 and also effectively protects Si0 2 . This is partly due to the fact that the element Si is common to both.
  • the dielectric layer comprises Si0 2 formed by thermal oxidation
  • an intermediate layer of sputtered Si0 2 is an attractive variant.
  • This material can also be readily selectively removed (akkoord?) with respect to thermal Si0 2 (ratio of the etching rates in a hydrogen fluoride solution is approximately 20:1). As both materials comprise the same elements, the risk of contamination of the dielectric layer by the intermediate layer is minimal.
  • Si x O y N z is chosen as the material for the dielectric layer
  • the first conductivity type is chosen to be the n-conductivity type
  • a material is chosen from the group composed of tantalum, tungsten, titanium or a nitride of these materials
  • the second conductor preferably a metal suicide is chosen.
  • the redundant parts of the first conductor layer as well as the redundant parts of the second conductor layer are removed by means of etching.
  • a method in accordance with the invention enables the etching technique that is very customary in the field of silicon technology to be applied without inconvenience.
  • the invention finally also comprises a semiconductor device obtained by means of a method in accordance with the invention.
  • FIGS. 1 through 10 are diagrammatic, cross-sectional views at right angles to the thickness direction, of a semiconductor device in successive stages of the manufacture by means of a first embodiment of a method in accordance with the invention.
  • Figs. 11 through 19 are diagrammatic, cross-sectional views at right angles to the thickness direction, of a semiconductor device in successive stages of the manufacture by means of a second embodiment of a method in accordance with the invention.
  • Figs. 1 through 10 are diagrammatic, cross-sectional views at right angles to the thickness direction, of a semiconductor device in successive stages of the manufacture by means of an embodiment of a method in accordance with the invention.
  • a semiconductor body 2 with a substrate 1, here of silicon, in which a first MOSFET 3 will be formed at the location of an n- type semiconductor region 3 A provided in the, in this case, p-type substrate 1, which semiconductor region forms the channel region 3 A of the first transistor 3.
  • the adjacent part of the substrate 1 serves as a channel region 5 A of a second MOSFET 5 to be formed.
  • the channel regions 3, 5 are, in this case, electrically separated by means of insulating regions 11 of silicon dioxide, i.e. a so-termed trench insulation.
  • the surface of the semiconductor body 2 is covered with a 0.5 to 1.5 nm thick dielectric layer 4 which contains, in this case, silicon dioxide.
  • a photoresist 7A on the intermediate layer 6 is patterned.
  • Fig. 2 a photoresist 7A on the intermediate layer 6 is patterned.
  • the intermediate layer 6 is removed, at the location of the first transistor 3 to be formed, by means of etching using a silicon etch such as a mixture of hydrogen fluoride and nitric acid or a solution of potassium hydroxide.
  • a silicon etch such as a mixture of hydrogen fluoride and nitric acid or a solution of potassium hydroxide.
  • the photoresist 7A is removed by means of a so-termed photoresist stripper.
  • a plasma etching process for this purpose, use can be made of a plasma etching process.
  • CVD Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • titanium is chosen as the material for the first conductor layer 33, and the thickness is chosen to be preferably at least 5 nm, in this case 10 nm.
  • a photoresist layer 7B is patterned.
  • the redundant parts of the first conductor layer 33 are removed by means of etching using a buffered hydrogen peroxide solution or a mixture of hydrogen peroxide and ammonia.
  • the intermediate layer 6 serves as an etch- stop layer.
  • the remaining part of the first conductor layer 33 serves as a gate electrode 3B of the first transistor 3 to be formed.
  • a second conductor layer 55 in this case of molybdenum disilicide, is provided in a thickness of, preferably, at least 5 nm, here 10 nm.
  • a further conductor layer 56 preferably, like in this case, of polycrystalline silicon is subsequently provided in a thickness of 100 nm, which will serve as an etch mask for removing the redundant parts of the second conductor layer 55, and as an anti-reflection layer for photolithography and, of course, as a conductor.
  • the layer 56 is patterned as desired by means of photolithography and etching, in this case by means of plasma etching.
  • the second gate electrode 5B and, at the same time, a stack of a part of the layers 55, 56 situated above the first gate electrode 3B are formed.
  • the parts of the gate electrode 3B that are situated outside the stack are removed by means of etching.
  • the gate electrode 5B of the second transistor 5 may be protected by a layer 13 of silicon dioxide or silicon nitride.
  • the layer 56 of polycrystalline silicon may be advantageously provided with, for example, a 30 nm thick layer of Si x O y N z (not shown in the drawing).
  • CMOS complementary metal-oxide-semiconductor
  • the source and drain regions, not shown, of the two transistors 3, 5 are formed by means of suitable implantations.
  • the semiconductor body 2 is covered with further insulating layers and provided with connection regions and, if necessary, connection conductors.
  • Individual devices 10 are obtained by means of a separating technique such as sawing.
  • Figs. 11 through 19 are diagrammatic, cross-sectional views at right angles to the thickness direction, of a semiconductor device in successive stages of the manufacture by means of a second embodiment of a method in accordance with the invention.
  • the manufacture of this example corresponds substantially to that of the first example, and for the details reference is thus made to said part of the description.
  • a further intermediate layer 8 is provided, in this case an aluminum layer having a thickness of 100 nm.
  • the further intermediate layer 8 is patterned (see Fig. 13) and the mask thus formed (see Fig. 14) is used to remove the intermediate layer 6 at the location of the first transistor 3.
  • a photoresist 7B is provided and the parts of the layer 33 situated outside said photoresist are removed. After the photoresist 7B (see Fig.
  • the invention is not limited to the exemplary embodiment described herein, and within the scope of the invention many variations and modifications are possible to those skilled in the art.
  • devices having a different geometry and/or different dimensions may be manufactured.
  • a substrate of Si it is possible to alternatively use a substrate of glass, ceramic or a synthetic resin.
  • the dielectric layer does not necessarily have to be the same or of the same thickness for both transistors.
  • the device may comprise further active and passive semiconductor elements or electronic components, such as a larger number of diodes and/or transistors and resistors and/or capacitors, whether or not in the form of an integrated circuit.
  • the manufacture is of course effectively adapted thereto.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (1) and a semiconductor body (2) comprising a first (N-MOS)FET (3) with a first channel region (3A) and a first gate electrode (3B) which includes a first conductor and which is separated from the channel region by a dielectric layer (4), and comprising a second (P-MOS)FET (5) with a second channel region (5A) and a second gate electrode (5B) which includes a second conductor that is different from the first conductor and which is separated from the channel region (5A) by a dielectric layer (4), wherein to form the gate electrodes (3B, 5B) a first conductor layer (33) is deposited on the semiconductor body (2) provided with the dielectric layer (4), which layer (33) is subsequently removed outside the first channel region (3A) after which a second conductor layer (55) is deposited on the semiconductor body (2), and wherein before the first conductor layer (33) is deposited, an intermediate layer (6) is deposited on the dielectric layer (4). According to the invention, a material for the intermediate layer (6) is chosen which is selectively etchable with respect to the dielectric layer (4), and before the deposition of the first conductor layer (33) the intermediate layer (6) is removed at the location of the firs channel region (3A), and after the deposition of the first conductor layer (33) and the removal thereof outside the first channel region (3A) and before the deposition of the second conductor layer (55), the intermediate layer (6) is removed at the location of the second channel region (5A). Thus, FETs are obtained in a simple manner and without damage to their gate dielectric. Preferably, a further intermediate layer (8) is deposited on the intermediate layer (6) which is selectively etchable with respect thereto.

Description

Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method
The invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body comprising a first field effect transistor with a first source, drain and channel region of a first conductivity type and a first gate electrode which includes a first conductor and which is separated from the channel region by a dielectric layer, and comprising a second field effect transistor with a second source, drain and channel region of a second conductivity type, opposite to the first conductivity type, and a second gate electrode which includes a second conductor that is different from the first conductor, and which is separated from the channel region by a dielectric layer, wherein to form the gate electrodes a first conductor layer is applied to the semiconductor body provided with the dielectric layer, which conductor layer is subsequently removed again outside the first channel region, after which a second conductor layer is applied to the semiconductor body, and wherein, before the first conductor layer is applied, an intermediate layer is provided on the dielectric layer. Such a method, in which the first and the second gate electrode are made of a -metallic- conductor is very attractive for future (C)MOSFET (= Complementary Metal Oxide Semiconductor Field Effect Transistor) silicon devices, the series resistance being reduced, penetration of boron atoms into the gate oxide being counteracted, and the occurrence of depletion-layer effects in a gate electrode that would be composed of polycrystalline silicon being precluded. It is noted that the term gate oxide as used herein does not only refer to an oxide or oxynitride of silicon but also to a material such as silicon nitride.
A method of the type mentioned in the opening paragraph is known from United States patent specification US 6,383,879, published on 7 May 2002. In said document it is shown how two MOS transistors are made in, respectively, an n-type channel region (N- MOS transistor) and a p-type channel region (P-MOS transistor), with a so-termed N-metal and a so-termed P-metal being applied to a dielectric layer covering both regions. In this case, an N-metal and a P-metal are to be taken to mean a metal or metallic material whose work function is close to the Fermi level of, respectively, N-type doped and P-type doped poly crystalline silicon, the Fermi levels in question being approximately 4.15 and 5.2 eV, respectively. In the known method, a semiconductor body, wherein two transistors are formed in, respectively, an n-type region and a p-type region in a silicon semiconductor body, is provided with a dielectric layer on which two gate electrodes of a different metal are formed as follows: first, an intermediate layer of a material such as tantalum pentoxide, silicon nitride or aluminum oxide is provided. Next, at the location of the transistor to be formed first, a first conductor layer is provided and subsequently removed again outside the region of the first gate electrode. In this case, the intermediate layer serves as an etch-stop layer. Subsequently, a second conductor layer is deposited over the semiconductor body. By means of etching, said second conductor layer is removed again outside the first gate electrode already formed and outside the second gate electrode to be formed. In this case too, the intermediate layer serves as an etch-stop layer.
A drawback of the known method resides in that the transistors formed by means of said method have a relatively thick gate dielectric. After all, this is formed by two layers, i.e. the dielectric layer and the intermediate layer. Also the properties of such a gate dielectric composed of two different materials are less well defined.
Therefore, it is an object of the present invention to provide a method that enables both an N-MOS transistor and a P-MOS transistor to be readily made, and which, in addition, does not have the above-mentioned drawback.
To achieve this, a method of the type mentioned in the opening paragraph is characterized in accordance with the invention in that for the material of the intermediate layer use is made of a material that is selectively etchable with respect to the dielectric layer, and before the first conductor layer is provided, the intermediate layer is removed at the location of the first channel region, and after the first conductor layer has been provided and removed again outside the first channel region, and before the second conductor layer is provided, the intermediate layer is removed at the location of the second channel region. The invention is based on the recognition that in this manner the number of process steps to which the dielectric layer is exposed is minimized by virtue of the presence of the intermediate layer. The invention is further based on the recognition that a suitable choice of the material for the intermediate layer enables said layer to be selectively removed again, using comparatively mild etching techniques, at locations where it is not required. Said selective removal taking place, in particular, without removing also an undefined part of the dielectric layer, as occurs inevitably if a metallic conductor is provided on the dielectric layer and removed again by etching. This also depends on which metal is used. In a method in accordance with the invention, before the first conductor layer is provided, the intermediate layer is removed at the location of the first gate electrode to be formed, and before providing the second conductor layer, the intermediate layer is removed at the location of the second gate electrode. In the process of removing the superfluous parts of the first conductor layer, the intermediate layer can still serve as an etch-stop layer and protect the dielectric layer outside the first transistor. In the process of removing superfluous parts of the second conductor layer, the gate electrodes of both transistors are present already and protecting the dielectric layer is much less necessary because the parts of the dielectric layer forming the gate dielectric are and remain covered by, respectively, the first and the second conductor layer. An important advantage of the method in accordance with the invention finally is that the intermediate layer no longer fonns part of the gate dielectrics of the finished transistors. As a result, said dielectrics may be very thin and composed of a single material. In a first embodiment of a method in accordance with the invention, the intermediate layer is locally removed by means of photolithography and etching. This method is comparatively simple and fits in well with the customary technology.
In a further, also attractive, modification, prior to applying the first conductor layer, the intermediate layer is provided with a further intermediate layer the material of which is selectively etchable with respect to the material of the intermediate layer. This further intermediate layer is patterned by means of photolithography and etching. When the intermediate layer is being etched, the patterned part of the further intermediate layer can then be used as a mask. As a result, there is greater freedom as regards the choice of the etchants for the conductor layer because the intermediate layer is protected by the further intermediate layer instead of by a photoresist. An additional advantage in this connection is that also during the necessary removal of the photoresist, the intermediate layer is protected against the agents necessary for this operation.
A suitable material for the further intermediate layer is, for example, a metal such as aluminum. This is selectively etchable with respect to many materials and, in addition, many materials can be selectively removed with respect to this metal. Moreover, aluminum is a material that is frequently used as a connection conductor in the semiconductor technology. Thus, if aluminum is used, the method in accordance with this modification shows excellent compatibility with the customary silicon technology. The most suitable choice as regards the material for the intermediate layer depends on which material is chosen for the dielectric layer. If Si02 is chosen as the latter material, then an intermediate layer of Si is a very suitable choice. This material can be readily selectively removed with respect to Si02 and also effectively protects Si02. This is partly due to the fact that the element Si is common to both. If the dielectric layer comprises Si02 formed by thermal oxidation, then an intermediate layer of sputtered Si02 is an attractive variant. This material can also be readily selectively removed (akkoord?) with respect to thermal Si02 (ratio of the etching rates in a hydrogen fluoride solution is approximately 20:1). As both materials comprise the same elements, the risk of contamination of the dielectric layer by the intermediate layer is minimal.
Also if SixOyNz is chosen as the material for the dielectric layer, there are various suitable options for the material of the intermediate layer. If the oxygen content of the dielectric layer is chosen to be comparatively high, then S.3N or Si may be chosen as the material for the intermediate layer. If Si is chosen as the material for the intermediate layer, the risk of contamination of the dielectric layer is smallest and, in addition, selective removal of the intermediate layer is easiest. If the oxygen content of the SixOyNz of the dielectric layer is chosen to be comparatively low, then Si02 may advantageously be chosen as the material for the intermediate layer. In this case, the intermediate layer can be readily selectively removed. If the first conductivity type is chosen to be the n-conductivity type, preferably, for the first conductor a material is chosen from the group composed of tantalum, tungsten, titanium or a nitride of these materials, and for the second conductor preferably a metal suicide is chosen. Preferably the redundant parts of the first conductor layer as well as the redundant parts of the second conductor layer are removed by means of etching. Particularly a method in accordance with the invention enables the etching technique that is very customary in the field of silicon technology to be applied without inconvenience. The invention finally also comprises a semiconductor device obtained by means of a method in accordance with the invention.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. In the drawings: Figs. 1 through 10 are diagrammatic, cross-sectional views at right angles to the thickness direction, of a semiconductor device in successive stages of the manufacture by means of a first embodiment of a method in accordance with the invention, and
Figs. 11 through 19 are diagrammatic, cross-sectional views at right angles to the thickness direction, of a semiconductor device in successive stages of the manufacture by means of a second embodiment of a method in accordance with the invention.
The Figures are not drawn to scale and some dimensions, such as dimensions in the thickness direction, are exaggerated for clarity. Corresponding areas or parts in the different Figures bear the same reference numerals whenever possible.
Figs. 1 through 10 are diagrammatic, cross-sectional views at right angles to the thickness direction, of a semiconductor device in successive stages of the manufacture by means of an embodiment of a method in accordance with the invention. As a basis for the manufacture of the device 10, use is made (see Fig. 1) of a semiconductor body 2 with a substrate 1, here of silicon, in which a first MOSFET 3 will be formed at the location of an n- type semiconductor region 3 A provided in the, in this case, p-type substrate 1, which semiconductor region forms the channel region 3 A of the first transistor 3. The adjacent part of the substrate 1 serves as a channel region 5 A of a second MOSFET 5 to be formed. The channel regions 3, 5 are, in this case, electrically separated by means of insulating regions 11 of silicon dioxide, i.e. a so-termed trench insulation. The surface of the semiconductor body 2 is covered with a 0.5 to 1.5 nm thick dielectric layer 4 which contains, in this case, silicon dioxide. On said dielectric layer there is provided an intermediate layer 6, in this case, of silicon having a thickness in the range of 10 to 100 nm. Subsequently (see Fig. 2), a photoresist 7A on the intermediate layer 6 is patterned. Next (see Fig. 3), the intermediate layer 6 is removed, at the location of the first transistor 3 to be formed, by means of etching using a silicon etch such as a mixture of hydrogen fluoride and nitric acid or a solution of potassium hydroxide. Subsequently, the photoresist 7A is removed by means of a so-termed photoresist stripper. For this purpose, use can be made of a plasma etching process.
Next (see Fig. 4), a first conductor layer 33 is provided by means of CVD (= Chemical Vapor Deposition) or PVD (= Physical Vapor Deposition) such as sputtering. In this case, titanium is chosen as the material for the first conductor layer 33, and the thickness is chosen to be preferably at least 5 nm, in this case 10 nm. Subsequently (see Fig. 5), a photoresist layer 7B is patterned. Next, the redundant parts of the first conductor layer 33 are removed by means of etching using a buffered hydrogen peroxide solution or a mixture of hydrogen peroxide and ammonia. In this process, the intermediate layer 6 serves as an etch- stop layer. The remaining part of the first conductor layer 33 serves as a gate electrode 3B of the first transistor 3 to be formed.
Next (see Fig. 6), the photoresist 7B is removed in the same manner as described above with respect to the photoresist 7A. Subsequently (see Fig. 7), the intermediate layer 6 is removed, in the same manner as described above, at the location of the second resistor 5 to be formed,. Subsequently (see Fig. 8), a second conductor layer 55, in this case of molybdenum disilicide, is provided in a thickness of, preferably, at least 5 nm, here 10 nm. In this example a further conductor layer 56, preferably, like in this case, of polycrystalline silicon is subsequently provided in a thickness of 100 nm, which will serve as an etch mask for removing the redundant parts of the second conductor layer 55, and as an anti-reflection layer for photolithography and, of course, as a conductor. The layer 56 is patterned as desired by means of photolithography and etching, in this case by means of plasma etching. In this manner (see Fig. 9), the second gate electrode 5B and, at the same time, a stack of a part of the layers 55, 56 situated above the first gate electrode 3B are formed. Finally (see Fig. 10), the parts of the gate electrode 3B that are situated outside the stack are removed by means of etching. In this process, as shown in Fig. 10, the gate electrode 5B of the second transistor 5 may be protected by a layer 13 of silicon dioxide or silicon nitride. It is to be noted that, in addition, the layer 56 of polycrystalline silicon may be advantageously provided with, for example, a 30 nm thick layer of SixOyNz (not shown in the drawing).
The manufacturing process is subsequently continued in a manner that is customary in the CMOS technology. In this continuation of the process, in particular the source and drain regions, not shown, of the two transistors 3, 5 are formed by means of suitable implantations. Also, the semiconductor body 2 is covered with further insulating layers and provided with connection regions and, if necessary, connection conductors. Individual devices 10 are obtained by means of a separating technique such as sawing. Figs. 11 through 19 are diagrammatic, cross-sectional views at right angles to the thickness direction, of a semiconductor device in successive stages of the manufacture by means of a second embodiment of a method in accordance with the invention. The manufacture of this example corresponds substantially to that of the first example, and for the details reference is thus made to said part of the description. Here, only the most important differences will be briefly discussed. Immediately after the provision of the intermediate layer 6 (see Fig. 11), a further intermediate layer 8 is provided, in this case an aluminum layer having a thickness of 100 nm. By means of a photoresist 7A and etching, first (see Fig. 12) the further intermediate layer 8 is patterned (see Fig. 13) and the mask thus formed (see Fig. 14) is used to remove the intermediate layer 6 at the location of the first transistor 3. After the provision of the first conductor layer 33 (see Fig. 15), a photoresist 7B (see Fig. 16) is provided and the parts of the layer 33 situated outside said photoresist are removed. After the photoresist 7B (see Fig. 17) has been removed, the further intermediate layer 8 is removed entirely. Next (see Fig. 18), the intermediate layer 6 is removed completely. Finally (see Fig. 19), the second conductor layer 55 and the mask layer 56 are provided. From this point, the manufacturing process continues, for example, as described with respect to the first example.
The invention is not limited to the exemplary embodiment described herein, and within the scope of the invention many variations and modifications are possible to those skilled in the art. For example, devices having a different geometry and/or different dimensions may be manufactured. Instead of a substrate of Si, it is possible to alternatively use a substrate of glass, ceramic or a synthetic resin. The semiconductor body may then be formed by the so-termed SOI (= Silicon On Insulator). In this case, a so-termed substrate- transfer technique may or may not be used. It is to be noted further that materials other than those mentioned in the examples may be used within the scope of the invention. It is also possible to use different deposition techniques for the above-mentioned, or other, materials, such as epitaxy, CVD (= Chemical Vapor Deposition), sputtering and evaporation coating. Instead of wet-chemical etching methods, use may alternatively be made of "dry" techniques such as plasma etching, and conversely.
It is also noted that the dielectric layer does not necessarily have to be the same or of the same thickness for both transistors.
It is also noted that the device may comprise further active and passive semiconductor elements or electronic components, such as a larger number of diodes and/or transistors and resistors and/or capacitors, whether or not in the form of an integrated circuit. The manufacture is of course effectively adapted thereto.

Claims

CLAIMS:
1. A method of manufacturing a semiconductor device (10) with a substrate (1) and a semiconductor body (2) comprising a first field effect transistor (3) with a first source, drain and channel region (3 A) of a first conductivity type and a first gate electrode (3B) which includes a first conductor and which is separated from the channel region (3A) by a dielectric layer (4), and comprising a second field effect transistor (5) with a second source, drain and channel region (5 A) of a second conductivity type, opposite to the first conductivity type, and a second gate electrode (5B) which includes a second conductor that is different from the first conductor, and which is separated from the channel region (5 A) by a dielectric layer (4), wherein to form the gate electrodes (3B, 5B) a first conductor layer (33) is applied to the semiconductor body (2) provided with the dielectric layer (4), which conductor layer is subsequently removed again outside the first channel region (3A), after which a second conductor layer (55) is applied to the semiconductor body (2), and wherein, before the first conductor layer (33) is applied, an intermediate layer (6) is provided on the dielectric layer (4), characterized in that for the material of the intermediate layer (6) use is made of a material that is selectively etchable with respect to the dielectric layer (4), and before the first conductor layer (33) is provided, the intermediate layer (6) is removed at the location of the first channel region (3 A), and after the first conductor layer (33) has been provided and removed again outside the first channel region (3 A), and before the second conductor layer (55) is provided, the intennediate layer (6) is removed at the location of the second channel region (5A).
2. A method as claimed in claim 1, characterized in that the intermediate layer (6) is locally removed by means of a photoresist mask (7A, 7B) and etching.
3. A method as claimed in claim 1 or 2, characterized in that prior to applying the first conductor layer (33), the intermediate layer (6) is provided with a further intermediate layer (8) the material of which is selectively etchable with respect to the material of the intermediate layer (6).
4. A method as claimed in claim 3, characterized in that for the material of the further intermediate layer (8) a metal is chosen with respect to which the first conductor is selectively etchable.
5. A method as claimed in claim 4, characterized in that aluminum is chosen as the material for the further intermediate layer (8).
6. A method as claimed in claim 1, 2, 3, 4 or 5, wherein Si02 is chosen as the material for the dielectric layer (4), characterized in that Si is chosen as the material for the intermediate layer (6).
7. A method as claimed in claim 1, 2, 3, 4 or 5, wherein thermal Si02 is chosen as the material for the dielectric layer (4), characterized in that sputtered Si02 is chosen as the material for the intermediate layer (6).
8. A method as claimed in claim 1, 2, 3, 4 or 5, wherein SixOyNz having a comparatively high oxygen content is chosen as the material for the dielectric layer (4), characterized in that Si3N4 or Si is chosen as the material for the intermediate layer (6).
9. A method as claimed in claim 1, 2, 3, 4 or 5, wherein SixOyNz having a comparatively low oxygen content is chosen as the material for the dielectric layer (4), characterized in that Si02 is chosen as the material for the intermediate layer (6).
10. A method as claimed in any one of the preceding claims, characterized in that the first conductivity type is chosen to be the n-type, and for the first conductor layer (33) a material is chosen from the group composed of tantalum, tungsten, titanium or a nitride of these materials, and for the second conductor layer (55) a metal suicide is chosen.
11. A method as claimed in any one of the preceding claims, characterized in that the superfluous parts of the first conductor layer (33) as well as the superfluous parts of the second conductor layer (55) are removed by means of etching.
12. A semiconductor device obtained by means of a method as claimed in any one of the preceding claims.
PCT/IB2004/050030 2003-02-03 2004-01-16 Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method WO2004070834A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007031928A2 (en) * 2005-09-15 2007-03-22 Nxp B.V. Method of manufacturing semiconductor device with different metallic gates
JP2007524992A (en) * 2003-03-27 2007-08-30 フリースケール セミコンダクター インコーポレイテッド Method for forming a dual metal gate device
WO2007031930A3 (en) * 2005-09-15 2007-09-13 Nxp Bv Method of manufacturing semiconductor device with different metallic gates
US8178401B2 (en) 2005-08-25 2012-05-15 Freescale Semiconductor, Inc. Method for fabricating dual-metal gate device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4533155B2 (en) * 2005-01-12 2010-09-01 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
JP2007194592A (en) * 2005-12-20 2007-08-02 Tdk Corp Dielectric element, and method of manufacturing same
US20070152276A1 (en) * 2005-12-30 2007-07-05 International Business Machines Corporation High performance CMOS circuits, and methods for fabricating the same
JP2009021550A (en) * 2007-07-12 2009-01-29 Panasonic Corp Manufacturing method of semiconductor device
JP2009135419A (en) * 2007-10-31 2009-06-18 Panasonic Corp Semiconductor apparatus and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0802565A1 (en) * 1996-02-28 1997-10-22 Nec Corporation Method for forming stacked capacitor storage electrode
US20020119648A1 (en) * 2000-12-27 2002-08-29 Fujitsu Limited Method for fabricating semiconductor device
US20020151125A1 (en) 2001-04-11 2002-10-17 Samsung Electronics Co., Ltd. Method of forming a CMOS type semiconductor device having dual gates
US6479392B2 (en) * 2000-03-30 2002-11-12 Hitachi, Ltd. Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device
US20030080387A1 (en) * 2001-11-01 2003-05-01 Cho Heung Jae CMOS of semiconductor device and method for manufacturing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1156904C (en) * 1996-03-06 2004-07-07 皇家菲利浦电子有限公司 Method of mfg. a pic(power integrated circuit) device, and a pic device manufactured by such a method
US6693331B2 (en) * 1999-11-18 2004-02-17 Intel Corporation Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation
US6383879B1 (en) * 1999-12-03 2002-05-07 Agere Systems Guardian Corp. Semiconductor device having a metal gate with a work function compatible with a semiconductor device
JP2001284466A (en) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing it
JP2002198441A (en) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc Method for forming dual metal gate of semiconductor element

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0802565A1 (en) * 1996-02-28 1997-10-22 Nec Corporation Method for forming stacked capacitor storage electrode
US6479392B2 (en) * 2000-03-30 2002-11-12 Hitachi, Ltd. Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device
US20020119648A1 (en) * 2000-12-27 2002-08-29 Fujitsu Limited Method for fabricating semiconductor device
US20020151125A1 (en) 2001-04-11 2002-10-17 Samsung Electronics Co., Ltd. Method of forming a CMOS type semiconductor device having dual gates
US20030080387A1 (en) * 2001-11-01 2003-05-01 Cho Heung Jae CMOS of semiconductor device and method for manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007524992A (en) * 2003-03-27 2007-08-30 フリースケール セミコンダクター インコーポレイテッド Method for forming a dual metal gate device
US8178401B2 (en) 2005-08-25 2012-05-15 Freescale Semiconductor, Inc. Method for fabricating dual-metal gate device
WO2007031928A2 (en) * 2005-09-15 2007-03-22 Nxp B.V. Method of manufacturing semiconductor device with different metallic gates
WO2007031930A3 (en) * 2005-09-15 2007-09-13 Nxp Bv Method of manufacturing semiconductor device with different metallic gates
WO2007031928A3 (en) * 2005-09-15 2007-10-11 Nxp Bv Method of manufacturing semiconductor device with different metallic gates

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JP2006518547A (en) 2006-08-10
US7157337B2 (en) 2007-01-02

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