WO2004059731A1 - Structure silicium sur saphir (dispositif) avec couche tampon - Google Patents

Structure silicium sur saphir (dispositif) avec couche tampon Download PDF

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Publication number
WO2004059731A1
WO2004059731A1 PCT/US2002/041183 US0241183W WO2004059731A1 WO 2004059731 A1 WO2004059731 A1 WO 2004059731A1 US 0241183 W US0241183 W US 0241183W WO 2004059731 A1 WO2004059731 A1 WO 2004059731A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
silicon
sapphire
silicon oxide
interface
Prior art date
Application number
PCT/US2002/041183
Other languages
English (en)
Inventor
Louis L Hsu
Leathen Shi
Li-Kong Wang
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to PCT/US2002/041183 priority Critical patent/WO2004059731A1/fr
Priority to AU2002361847A priority patent/AU2002361847A1/en
Publication of WO2004059731A1 publication Critical patent/WO2004059731A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H01L29/6678—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates on sapphire substrates, e.g. SOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H01L29/78657—SOS transistors

Definitions

  • This invention relates to the field of integrated circuitry. More
  • the invention relates to the field of integrated circuits
  • CMOS devices built on the silicon on insulator (SOI) substrates can be any type of semiconductor material.
  • SOI silicon on insulator
  • Sapphire is a highly transparent
  • silicon and sapphire layer causes defects in the silicon device like
  • An object of this invention is an improved silicon on sapphire
  • An object of this invention is an improved a silicon on sapphire
  • An object of this invention is an improved silicon on sapphire
  • An object of this invention is an improved silicon on sapphire
  • An object of this invention is an improved a silicon on sapphire
  • An object of this invention is an improved silicon on sapphire
  • the present invention is an improved silicon on sapphire structure
  • the buffer layer is layer of silicon oxide material that
  • the buffer layer comprises two layers. A first
  • a second silicon oxide layer is formed between the silicon and the oxide layer.
  • oxide layers are then attached, e.g., by a wafer bonding technique.
  • This structure has no conductive paths beneath the oxide insulator(s)
  • Figure 1 is a block diagram perspective view of a silicon on sapphire
  • Figure 2 is a block diagram perspective view of a silicon on sapphire
  • passive components are built on sapphire
  • sapphire substrate is totally transparent to RF radiation and optical
  • silicate glass plastic, or any organic material like polyamide.
  • sapphire is a preferred embodiment because it has
  • the film structure of the silicon 107 on sapphire 103 is shown in
  • sapphire 103 are thermal grown oxide.
  • This layer 105 can provide improved adhesive property when the
  • substrate 103 is annealed during the device fabrication procedure.
  • oxide layer is designed to provide a viscous layer between the
  • CMOS FET devices 102 are fabricated on the sapphire
  • oxide 104 is either deposited or filled with a shallow trench isolation
  • the oxide layers serves
  • the silicon dioxide layer 105 is thermally grown from the silicon to preserve good interface property and device
  • a layer of silicon dioxide 105 is grown on the device wafer 107 to
  • layer can be as thin as 10-20 angstrom to 1 micron or greater.
  • silicon dioxide layer 105 is deposited on the device layer 107 by
  • silicon dioxide layer 105 and the device layer 107 may not be a
  • the silicon wafer and the sapphire 103 are bonded together and
  • CMP Chemical Mechanical Polishing
  • the material of the silicon device wafer can be remove to the thin final
  • the CMOS devices 102 can be fabricated using a conventional
  • the passive components 101 (capacitors, inductors, resistors, etc)
  • planar coil 101 is shown. Since there is no underlying
  • Figure 2 is a block diagram perspective view of an alternative
  • the upper silicon oxide layer 105 which directly
  • the upper oxide layer 105 a preferred embodiment, the
  • bottom silicon oxide layer 206 is a deposited oxide that is typically
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • This silicon oxide layer 206 is designed to
  • layer 105 can be
  • CMOS FET devices 102 are fabricated on the sapphire
  • isolation oxide 104 is either deposited or filled with a shallow trench
  • STI isolation
  • inductive coil component ( inductive coil ) is shown as 101.
  • oxide layers There two oxide layers
  • the thickness of layer 105 can be for 10-20 angstroms to 1 micron or
  • the thickness of the deposited oxide can be from 100-200
  • CMP Chemical Mechanical Polishing
  • the material of the silicon device wafer can be remove to the thin final
  • Shallow Trench Isolation process is used to form the isolation 104
  • this isolation structure 104 also can be used to make this isolation structure 104.
  • the isolation structure 104 is silicon oxide
  • the sapphire layer 103 are insulating layers that

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

Cette invention concerne une structure et/ou un dispositif de type silicium sur saphir comptant une ou plusieurs couches tampons. Dans un premier mode de réalisation préféré, la couche tampon est constituée par une couche de matériau à base d'oxyde de silicium qui empêche la formation de défectuosités dues à des contraintes dans la couche de silicium. Dans un autre mode de réalisation, la couche tampon comprend deux couches: une première couche en oxyde de silicium fixée au silicium et assurant une interface parfaite; et une seconde couche d'oxyde de silicium fixée à la couche de saphir. Les première et seconde couche de silicium sont ensuite fixées, notamment par une technique de liaison de tranches. Cette structure, qui est exempte de chemin conducteurs sous le ou les isolants d'oxyde, assure de meilleurs performances dans les applications en radiofréquence.
PCT/US2002/041183 2002-12-20 2002-12-20 Structure silicium sur saphir (dispositif) avec couche tampon WO2004059731A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2002/041183 WO2004059731A1 (fr) 2002-12-20 2002-12-20 Structure silicium sur saphir (dispositif) avec couche tampon
AU2002361847A AU2002361847A1 (en) 2002-12-20 2002-12-20 Silicon on sapphire structure (devices) with buffer layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/041183 WO2004059731A1 (fr) 2002-12-20 2002-12-20 Structure silicium sur saphir (dispositif) avec couche tampon

Publications (1)

Publication Number Publication Date
WO2004059731A1 true WO2004059731A1 (fr) 2004-07-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/041183 WO2004059731A1 (fr) 2002-12-20 2002-12-20 Structure silicium sur saphir (dispositif) avec couche tampon

Country Status (2)

Country Link
AU (1) AU2002361847A1 (fr)
WO (1) WO2004059731A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167068A1 (en) * 2001-05-09 2002-11-14 International Business Machines Corporation Silicon on sapphire structure (devices) with buffer layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167068A1 (en) * 2001-05-09 2002-11-14 International Business Machines Corporation Silicon on sapphire structure (devices) with buffer layer

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US10324496B2 (en) 2013-12-11 2019-06-18 Apple Inc. Cover glass arrangement for an electronic device
US10386889B2 (en) 2013-12-11 2019-08-20 Apple Inc. Cover glass for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
US9461357B2 (en) 2014-02-12 2016-10-04 Apple Inc. Antenna on sapphire structure
US9692113B2 (en) 2014-02-12 2017-06-27 Apple Inc. Antenna on sapphire structure
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components

Also Published As

Publication number Publication date
AU2002361847A1 (en) 2004-07-22

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