WO2004047164A1

WO2004047164A1 - Semiconductor device having elevated device isolation structure and production method therefor

Info

Publication number: WO2004047164A1
Application number: PCT/JP2003/014524
Authority: WO
Inventors: Hitoshi Wakabayashi; Jong-Wook Lee; Risho Koh; Shigeharu Yamagami; Yukishige Saito
Original assignee: Nec Corporation
Priority date: 2002-11-15
Filing date: 2003-11-14
Publication date: 2004-06-03
Also published as: AU2003280804A1; JP2004165566A

Abstract

A semiconductor device using an SOI substrate having an elevated device isolation structure, comprising a bird’s beak unit, where the thickness of a gate insulation film is gradually increases from a device center side toward a device isolation end, disposed at the end in contact with a device isolation area on a section being orthogonal to a channel current direction and including the gate electrode. The semiconductor device is excellent in characteristics such as resistance against antenna damage subjected to in the post-process, gate leak current, TDDB characteristics, and Vth (threshold voltage) controllability by Vsub (substrate potential).

Description

TECHNICAL FIELD The present invention relates to a semiconductor device having an elevated element isolation structure and a method of manufacturing the same.

The present invention relates to a structure of a MI SFET (metal-insulating film-silicon) having a raised element isolation structure and a method of manufacturing the same.

Background art

Conventionally, in an element structure using a silicon on insulator (SOI) substrate, isolation between element regions is performed by trench isolation technology such as STI (Shallow Trench Iso1 ation). There is an advantage that the element regions can be electrically separated.

However, a conventional normal STI trench isolation structure, that is, a substrate 101, a buried oxide film 102, a SOI film 103, a gate insulating film 104, a gate electrode 105, and a device as shown in FIG. In the case of a structure having the isolation film 107 and an element structure in which the height of the element isolation film is not higher than the gate insulating film, as shown by an arrow at a part of the upper corner of the end of the SOI film 103, the gate electrode faces the gate electrode. Electric field tends to concentrate on the part where In particular, after various processes such as etching, the isolation electrode embedded in the trench is etched as shown in Fig. 6 (b), so that the gate electrode surrounds the SOI edge. As a result, the electric field is more easily concentrated on the upper end of the SOI film 103. As a result, the leakage current increases at the upper corner of the SOI film, and the threshold voltage decreases.

Therefore, for the purpose of suppressing the occurrence of the parasitic channel at the end of the element region, suppressing the reverse narrow channel effect of the transistor, and suppressing the off-leak current of the transistor, the upper surface of the Si layer, In particular, an element isolation structure in which the surface of the element isolation film is raised more discontinuously than the gate oxide film has been proposed. For example, Japanese Unexamined Patent Publication No. 6-177239 (Patent Document 1) discloses that in a trench isolation structure on a bulk substrate, the upper end of a buried oxide film (an element isolation film in the present application) is located above a gate oxide film and at the same time. It is described that using a manufacturing method having a flat upper surface is effective in suppressing the inverse narrow channel effect. On the other hand, Japanese Unexamined Patent Application Publication No. 2001-24202 (Patent Document 2) discloses an example in which a lift-up element isolation structure is applied to an SO I-MI SFET in order to suppress a leakage current at an active region (SO I film) end. It is shown.

2002 Symposium on VLSI Technology, Digest of Technical Papers, pp. 42-43, "ELFIN (ELevated Field INsulator) and SEP (S / D Elevated by Poly-Si Plugging) Processor Ultra-Thin SOI MOSFETs with High Performance and High Reliability "Jong-Wook Lee et al. (Non-Patent Document 1) and IEEE Electron Device Letters, Vol.23, No.8, p.467 (Non-Patent Document 2) use a raised element isolation structure (ELFIN). It describes that the reverse narrow channel effect can be prevented.

A MOSFET having an elevated element isolation structure is manufactured as follows (JP-A-2001-24202).

First, FIG. 7 is a schematic plan view illustrating the arrangement relationship between the element region 122, the element isolation region 123 that partitions the element region, and the gate electrode 115. In this figure, the hatched lines indicate the end 121 of the element region below the gate electrode.

The cross-sectional views of the manufacturing process are shown in FIGS. 8 and 9 (a) to (e) and (f1-1 to 3), which are cross-sectional structures including the gate electrode on the active region, parallel to the current direction of the channel. explain.

As shown in FIG. 8 (a), after a SOI substrate having a buried oxide film 112 and an SOI film 113 provided thereon is prepared in advance on a silicon substrate 111, the gate insulating film 114 and the first (For example, a polycrystalline silicon film). Next, as shown in FIG. 3 (b), the first conductive film, the gate insulating film, and the SOI film at the portion 117a to be an element isolation region are exposed by an exposure step and an etching step so as to leave an element region. For example, it is removed by plasma etching.

Further, as shown in FIG. 8C, an element isolation insulating film 117 (silicon oxide film) is buried, and the surface heights of the first conductive film 115a and the element isolation insulating film 117 are increased by CMP.

Next, as shown in FIG. 8D, after forming a second conductive film 115b (for example, a polycrystalline silicon film), a resist 119 is applied as shown in FIG. Patterning. At this time, the pattern of the resist 119 is the same as the gate electrode pattern shown in FIG.

As shown in FIGS. 9 (f-1) to (f-13), the second conductive film 115b, the first conductive film 115a and the gate insulating film 114 are etched by using the resist 119 as a resist. After exposing the SOI film 113 in the region where the source / drain is to be formed, the resist 119 is removed. Here, (f-1 1) is the X-X 'cross-sectional view (the cross-sectional structure including the gate electrode on the active region perpendicular to the channel current direction), (f-1 2) is the channel current direction, and (f-1 3) Is a plan view.

In the lift-up element isolation structure, as shown in this figure, the upper surface of the element isolation insulating film 117 is at least as thick as the first conductive film 115a than the gate insulating film formed on the SOI film 113. It is located above. The SOI film 113, the gate insulating film 114, and the first conductive film (polycrystalline silicon film) 115a are cut almost vertically at the element separation end when viewed in FIG. 9 (f-1). It is a rectangular shape. That is, in such an elevated element isolation structure, since the upper corner of the SOI film 113 faces only the corner of the first conductive film 115a, as shown in FIG. There is no concentration of the electric field, and the reverse narrow channel effect can be prevented.

List of prior art

Patent Document 1: JP-A-6-177239

Patent Document 2: Japanese Patent Application Laid-Open No. 2001-1-24202

Non-Patent Document 1: 2002 Symposium on VLSI Technology, Digest of Technical Papers, p. 42-43,

Non-patent document 2: IEEE Electron Device Letters, Vol.23, No.8, p.467 Non-patent document 3: IEICE technical report, SDM99-229, p.29-36 Or, even though the suppression of the inverse narrow channel effect has been considerably improved, further improvement is desired. The antenna damage tolerance subjected in a subsequent step, TDDB (ti me depe nd dielec .tricbre akd own) characteristics, V _sub V by (substrate potential) _th (threshold Voltage is also required to be improved.

In MIS FET devices, it is known that levels and the like are formed in the insulating film due to plasma damage during plasma etching, etc., which causes an increase in leakage current and a reduction in reliability. It has been reported that the MISFET on the bulk substrate is more susceptible to plasma damage due to the unique structure in which a buried insulating film is provided below the semiconductor layer on which the device is formed (see IEICE Technical Report, SDM 99-229, p. 2936, Non-Patent Document 3). In the case of an SOI device with an elevated isolation structure, plasma damage in the etching process of the isolation region shown in Fig. 8 (b) may enter the gate insulating film and the buried oxide film. This is considered to be large when the SOI film 113, the gate insulating film 114, and the first conductive film 115a are rectangular.

Therefore, when applying device isolation to an SOI structure that is originally susceptible to plasma damage, compared to applying device isolation to a MOS FET on a bulk substrate, It can be said that a device for improving the characteristics is particularly necessary.

Further, according to the study of the present inventor, in the case of such a rectangular shape, the edge portion (between the SOI film 113 and the first conductive film 115a forming the gate electrode) sandwiching the gate insulating film is considered. At the edge of the SOI film facing the buried oxide film, the electric field is still likely to concentrate at the edge portion of the SOI film, even though it is mitigated by the raised element isolation structure as compared with the conventional structure, and this is completely recovered. It is thought that this combination with the unacceptable plasma damage hinders the above-mentioned property improvement. Disclosure of the invention

That is, the present invention has been made in order to solve such a problem. The antenna damage resistance, gate leakage current, TDDB characteristics, and V _th (threshold voltage) due to V _sub (substrate potential) in a later process are provided. It is an object of the present invention to provide a semiconductor device having excellent characteristics such as controllability, in particular, a SII device having a raised element isolation structure.

The present invention provides a buried insulating film formed on a base semiconductor layer, A device isolation film reaching the film, a semiconductor active layer partitioned by the device isolation film and located on the buried insulating film, a gate insulating film provided on a part of the semiconductor active layer, A semiconductor device having a gate electrode provided to face the semiconductor active layer with a film interposed therebetween, wherein the element isolation film has an upper surface raised above the gate insulating film surface as viewed from the substrate. An element isolation structure, wherein in a cross section orthogonal to the current direction of the channel and including the gate electrode, at least a part of an end in contact with the element isolation film, from the element center side to the element isolation film side end, The present invention relates to a semiconductor device having a parse beak portion in which the thickness of a gate insulating film is gradually increased.

According to this configuration, at the edge of the gate insulating film, the semiconductor active layer (ie, the SOI film)

) And the reduction of the electric field concentration between the gate electrodes improves the characteristics of the gate insulating film, such as antenna damage resistance in later processes, reliability of the gate insulating film, gate leak current, and TDDB characteristics. .

The present invention also provides a buried insulating film formed on a base semiconductor layer, an element isolation film reaching the buried insulating film, and a semiconductor active layer partitioned by the element isolation film and located on the buried insulating film. A gate insulating film provided on a part of the semiconductor active layer; and a gate electrode provided facing the semiconductor active layer via the gate insulating film. The device isolation film has a raised device isolation structure in which the upper surface is above the gate insulating film surface as viewed from the substrate, and is in contact with the device isolation film in a cross section orthogonal to the channel current direction and including the gate electrode. The bottom of the semiconductor active layer gradually recedes upward from the element center side to the element isolation film side end at least at a part of the end, and the thickness becomes thinner. Thick It relates to a semiconductor device and having a bottom Pazubiku portion and summer.

According to this configuration, since the electric field concentration is reduced at the end of the island-shaped semiconductor on the side of the buried insulating film, regarding the characteristics of the buried insulating film, the antenna damage resistance and the V _th due to V _sub (substrate potential) in a later process are reduced. (Threshold voltage) Characteristics such as controllability are improved.

Note that a configuration having both of the above two configurations is most preferable. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a cross-sectional view showing one example of the semiconductor device of the present invention.

FIG. 2 is a sectional process view showing one example of the manufacturing method of the present invention.

FIG. 3 is a cross-sectional view of the semiconductor device manufactured in the example. '

FIG. 4 is a graph showing the gate width dependence of the threshold voltage of the semiconductor device manufactured in the example.

FIG. 5 is a graph showing the gate voltage dependence of the gate leak current of the semiconductor device manufactured in the example.

FIG. 6 is a diagram showing an element isolation structure of a conventional semiconductor device.

FIG. 7 is a top view of the semiconductor device.

FIG. 8 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 9 is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 10 is a diagram illustrating electric field concentration in the structure of a conventional semiconductor device. FIG. 11 is a diagram illustrating electric field concentration in the structure of a conventional semiconductor device. FIG. 12 is a diagram illustrating electric field concentration in the structure of a conventional semiconductor device. FIG. 13 is a cross-sectional view showing one example of the semiconductor device of the present invention.

FIG. 14 is a sectional view showing an example of the semiconductor device of the present invention.

FIG. 15 is a cross-sectional view showing one example of the semiconductor device of the present invention.

Explanation of symbols:

1 Base semiconductor, base silicon layer

2 Embedded insulation layer

3 Semiconductor active layer (S〇I film)

4 Gate insulating film

5 Gate electrode

5a First gate electrode material, first polycrystalline silicon film

5 b Second gate electrode material, second polycrystalline silicon film

6 Silicon nitride film

7 Element separation membrane Element isolation groove

Partial separation membrane

Side oxide film

Notch

Body contact area

Body area

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 [(c) is a top view, (a) is an XX ′ cross-sectional view, and (b) is a YYY ′ cross-sectional view] shows a characteristic portion of the semiconductor device of the present invention. Layer 1, buried insulating layer 2, semiconductor active layer (hereinafter referred to as SII film) 3, gate insulating film 4, gate electrode 5 (in this example, first gate electrode material 5a and second And a device isolation film 7.

In the raised element isolation structure, the upper surface of the element isolation film 7 is located above the gate insulating film. In a later step, an interlayer insulating film or the like may be further formed on the element isolation film 7, but the upper surface of the element isolation film is provided with a gate electrode (the second gate electrode material 5b in this example). It is defined by the lower surface of the part. The upper surface of the element isolation film 7 is located usually at least 20 nm or more, preferably at least 50 nm or more above the central flat portion of the gate insulating film 4. Usually, the position is less than 200 nm.

Although not shown in this figure, a source region and a drain region are formed in the SOI film 3 by a subsequent process, and a contact hole or the like is provided after being filled with an interlayer insulating film in a normal structure. The present invention includes a semiconductor device having such a structure.

According to the present invention, the thickness of the gate insulating film increases from the element center side toward the element isolation end at the portion A in FIG. 1A, that is, at the element isolation end of the gate insulating film. In the present invention, a portion where the thickness of the gate insulating film at the element isolation end is increased is called a parse beak portion. In such a shape in which the thickness of the gate insulating film increases toward the end, the electric field concentration can be reduced. In the prior art in which lift-up element isolation is applied to a MISFET, as shown in FIG. 12, electric field concentration occurs at a part of the upper corner of the SOI layer 113. In this case, unlike the case of FIG. 6 (a) or FIG. 6 (b), the gate electrode 115a does not extend to the element isolation insulating film 117. In comparison, the degree of electric field concentration is small.

Here, if lift-up element isolation is applied to a normal MOSFET on a bulk substrate, the electric field concentration shown in Fig. 12 causes the potential at the upper corner of the element region to fluctuate and the leakage current to increase. And no reverse short channel effect occurs. This is due to the fact that conventional MOSFETs on bulk substrates are implanted with enough impurity below the field concentration to stabilize the threshold voltage.

However, in the case of SOI devices, all the impurities for adjusting the threshold voltage are concentrated on the thin SOI layer, which is considered to be affected by electric field concentration. Even with a weak electric field concentration as shown in (1), characteristic degradation such as the reverse short channel effect and generation of leak current will occur.

On the other hand, in the present invention, as shown by the symbol A in FIG. 1 (a), a parse beak portion is provided above the S0I layer 3, and the upper corner of the S〇I layer is rounded. Therefore, the electric field is alleviated, and the generation of leakage current at the upper corner, the deterioration of the sub-threshold characteristics due to the generation of the leakage current (the deterioration of the ON / OFF ratio due to the increase of the S factor), and the deterioration of characteristics such as the inverse narrow channel effect are reduced. Be suppressed. Here, as shown in FIG. 1 (a), the portion that is wider than the center of the gate insulating film is defined as the penetration distance, and the penetration distance L l from the end of the first gate electrode material 5a, SO I Expressed as the penetration distance L 2 from the edge of the film 3. If the penetration distances L 1 and L 2 are larger than 0, that is, if there is any penetration, the concentration of the electric field can be prevented, but usually both L 1 and L 2 are 1 nm or more. It is preferably at least 2 nm, more preferably at least 5 nm. On the other hand, if it is too large, an effective channel width cannot be secured and an inverse narrow channel effect appears. Therefore, it is preferably 25 nm or less, more preferably 20 nm or less. At the same time, it is preferably 5% or less of the channel width. In addition, the effect of the divergence of the purse beak is at least as long as it is larger than the gate insulating film thickness. If it is too large, the adverse effect of the inverse narrow channel effect will appear.

Usually, the thickness is preferably within 10 times the thickness of the gate insulating film.

The thickness is preferably 50% or less of the I film thickness.

Also, L 1 and L 2 may be equal or different. However, in particular, if the penetration distance L2 on the SOI film side is too large, the inverse narrow channel effect becomes large, and the fluctuation of the threshold becomes large. Therefore, it is preferable that the penetration is not larger than necessary. Therefore, it is preferable that L2 and L1. For L 2, it is more preferably 25 nm or less and 5% or less of the channel width. On the other hand, since L1 is less affected by the inverse narrow channel effect, it is preferable to increase L1 as compared with L2 to reduce electric field concentration. Even when comparing the radii of curvature of the corners, the upper one has a larger radius of curvature than the lower one, and the corners are more rounded. The method of forming asymmetrically is described in the manufacturing method. '

Further, the S〇I layer may be flat (L 2 = 0), and the gate insulating film may be thickened (L 1> 0) only on the gate electrode side.

In part B of FIG. 1 (a), the bottom of the SOI film 3 gradually recedes upward from the center of the device toward the isolation end, and the thickness of the buried insulating film decreases. However, it is gradually thicker than the center of the device. In the present invention, such a thick portion is referred to as a bottom parse peak portion. As the thickness of the buried insulating layer increases toward the end and the distance from the base semiconductor layer 1 of the substrate increases, the electric field concentration at the bottom end of the SOI film is reduced.

In the SOI element, the electric field generated by the charge 132 in the buried oxide film and the charge 131 in the element isolation insulating film concentrates on the lower corner portion 133 of the SOI layer. Usually, the electric charge 131 in the buried oxide film and the electric charge 131 in the device isolation effect film have a positive electric charge, so that the potential of the lower corner portion 133 of the SOI layer is lowered. As a result, in the n-channel SO I-M〇S FET, a leakage current occurs at the lower corner portion 133, and an inverse narrow channel effect occurs as the threshold voltage at the end decreases. . Also, in the p-channel SO I-M〇S FET, the threshold voltage at the end rises, so the narrow channel effect, that is, the reduction of the channel width This has the effect of increasing the threshold voltage (Figure 10). This is a problem peculiar to the SOI element, which does not exist in the MOSFET on the bulk substrate.

On the other hand, in the present invention, as shown by the symbol B in FIG. 1 (a), a bottom bird's beak portion is provided on the bottom surface of the S01 layer 3, and the lower corner portion 133 is rounded. Therefore, the electric field concentration in the lower corner part 133 is reduced, and the lower corner of the n-channel SOI-MOS FET caused by the charge 131 in the buried oxide film and the charge 131 in the element isolation insulating film is reduced. The leak current and the reverse narrow channel effect in the section 133 and the narrow channel effect in the p-channel SOI-MOSFET can be prevented. '

Also, in an SOI-MOS FET having a short gate length, as shown in FIG. 11, the effect that the electric field 134 generated from the drain region 136 affects the SOI film under the gate electrode to the potential of 113 is remarkable. However, also in this case, as in the case of FIG. 10, the electric field concentration at the lower corner portion 133 of the SOI layer becomes remarkable, and in the case of the n-channel SOI-MOS FET, the potential at the lower corner portion 133 decreases. However, in the case of a p-channel SO I-MOS FET, the potential of the lower corner 133 increases. As a result, in both the n-channel SOI-MOS FET and the p-channel SOI-MO SFET, the occurrence of leakage current in the lower corner part 133 and the deterioration of the subthreshold characteristics due to the leakage current ( The deterioration of the ON / OFF ratio due to the increase of the S factor) and the characteristic deterioration such as the inverse narrow channel effect are caused. FIG. 11 (b) is a cross-sectional view in the Χ_ 'direction of FIG. 11 (a), which is a plan view, and FIG. 11 (c) is a Y—Y of FIG. 11 (a), which is a plan view. FIG. Reference numeral 135 denotes a source region. This is also a problem unique to SOI devices that does not exist in MOS FETs on the PARK substrate.

On the other hand, in the present invention, as shown by the symbol B in FIG. 1 (a), a bottom parse beak portion is provided on the bottom surface of the S01 layer 3, and the lower corner portion 133 is rounded. The concentration of the electric field from the drain in the lower corner portion 133 is reduced, and a leak current is generated in the lower corner portion 133, and the sub-threshold characteristic is deteriorated due to the leak current (the ON / OFF ratio is deteriorated due to an increase in the S factor). ) And characteristic degradation such as the inverse narrow channel effect are suppressed. Fig. 11 shows the direction of the electric field in n-channel SOI-M 一 SFET, but in the p-channel SOI-MOS FET, the direction of the electric field is opposite to that in Fig. 11 except that it is opposite. The problems and the effects and effects of the invention are the same.

Here, as shown in FIG. 1A, the portion where the bottom end of the SOI film is receded upward is defined as L3. L3 is also usually 1 nm or more, preferably 2 nm. Further, since an effective channel width cannot be ensured even if it is too large, it is preferably 25 nm or less, more preferably 20 nm or less, and most preferably 15 nm or less. At the same time, it is preferably 5% or less of the channel width (ie, gate width). The present invention has a large effect when the S 層 I layer is thin, and is preferably applied to an SOI substrate in which the thickness of the SOI layer is 100 nm or less, preferably 50 nm or less. At that time, the rate at which the SII film is thinned at the edge of the SOI layer is 20% or less, particularly preferably 10% or less, of the SOI film thickness immediately below the gate electrode. Incidentally, the thickness of the SOI layer is usually 1 nm or more.

In the example shown in Fig. 1, the insulating film is thicker from both the center and the end of the element in both the A and B sections, but only the parse beak of the gate insulating film or the bottom bird's beak The effect can be seen even if it has only. Usually, it is preferable to have both a bird's beak portion and a bottom parse beak portion of the gate insulating film portion.

Further, in the example of FIG. 1, in the cross section including the gate electrode, the parse beak portion of the gate insulating film and the bottom parse beak portion of the bottom of the semiconductor active layer are formed over the entire end portion in contact with the element isolation film. The form was shown. However, the effect can be obtained even if it is formed in a part of each region (for example, only on one side viewed from the central part of the element). That is, in the present invention, even if a parse beak is provided on at least a part of the end in contact with the element isolation film, or a bottom parse beak is provided on at least a part of the end in contact with the element isolation film. If it is, the effect can be seen.

For example, the present invention includes a partial isolation structure having a body contact region in which a SOI film is partially pulled out to make contact. FIG. 13 is an example of such a case, and when viewed in an X--X 'section, which is a section including a gate electrode in a plan view, as shown in FIG. 12 is separated from the MOSFET element region by the partial isolation film 8, while the SOI film is divided by the partial isolation film 8. The structure is such that the body region 13 (p− in the case of nMOS) and the body contact region 12 (P + in the case of nMOS) are connected under the partial isolation film 8. In the body contact region, a contact hole is provided in a later step to make electrical connection.

In the structure shown in this figure, the SOI film is dug partway and the partial isolation film 8 is buried, and a parse beak is formed at the end of the gate insulating film even at the end in contact with the partial isolation film 8, so that the electric field concentration The mitigation effect is equivalent to that shown in Figure 1.

In addition, FIG. 14 shows that the SOI film is left flat without digging the SOI film in the partial isolation region, and only the gate electrode side (in this case, the first gate electrode material 5a) is recessed, and the parse beak is performed. Is formed. The partial separation film 8 has a structure embedded up to the surface of the SII film.

FIG. 15 shows a structure in which the SOI film is left flat without digging the SOI film and no bird's beak is provided. In this structure, the parse beak portion is provided only on one side of the channel region.

14 and 15, the effect of bird's beak formation is reduced, but it is still superior to the conventional technique in which no bird's beak is provided.

Since the members constituting the semiconductor device of the present invention usually use a silicon substrate as the substrate, the base semiconductor layer is preferably silicon. The buried insulating film is formed by a SIMOX method or a bonding method, and is usually a silicon oxide layer. The thickness of the buried insulating film is not limited, but in the present invention, particularly when a lower parse beak portion is formed, the effect is great when applied to a film having a thickness of 200 nm or less, preferably 15 O nm or less. It is. The SOI film is usually preferably a single crystal silicon layer. When the present invention is applied, the effective thickness is 10 Onm or less, preferably 50 nm or less, as described above.

The element isolation film is generally a silicon oxide film, which is formed by ordinary plasma CVD (chemical deposition), but other insulating films mainly composed of silicon oxide such as BSG, PSG, BPSG, and silicon nitride films It may be a silicon oxynitride film, Si OF, or a stacked film of these.

The gate insulating film is not particularly limited as long as it satisfies the characteristics as a gate insulating film. In addition, a high-dielectric-constant insulating film other than Si-based insulating films such as a silicon oxide film, a silicon oxynitride film (Si〇N film) and a silicon nitride film (SiN film) may be used. As the high dielectric constant insulation _{緣膜, H f 0 2, H f} ON, H f S I_〇 and H f S i ON like the H f based insulation Enmaku, Z r0 _2, Z R_〇_N, Z r S i O and Z r S i Z r based insulating film ON like, a 1 ₂ 0 _3, a 1_Rei_N, a 1 S i 0, a 1 S i a 1 2 〇 ₃ based insulating film such as ON , L a ₂ 0 _3, L A_〇_N, L a S i 0, L a S i L a 2 0 3 based insulating film such as ON is exemplified et be. Here, the composition of the ON-containing film and the composition ratio of the Si-containing system can be arbitrarily selected.

The first gate electrode material can be a conductive material such as a metal, but is preferably formed of polycrystalline silicon or polycrystalline silicon germanium.

The second gate electrode material is not particularly limited and can be formed of a normal electrode material, and a conductive material such as polycrystalline silicon (including silicide), metal, etc. can be used. However, it is preferably polycrystalline silicon or polycrystalline silicon germanium (both include silicide).

Other conductive materials used as the first and second gate electrode materials include refractory metals such as Ti, W, Ta, Co, and Mo and alloys thereof, and nitrides or silicides of these metals. However, any material can be used as long as it is suitably used for the gate electrode. Also, the first and second gate electrode materials may have a laminated structure of different conductive materials from the viewpoint of preventing impurity diffusion, improving adhesion, controlling threshold voltage (work function control), and the like.

Although not shown in this figure, a side oxide film may be present between the SOI film and the first gate electrode material and the element isolation film as described in a manufacturing method described later. In that case, the side oxide film forms a part of the element isolation film.

Next, an example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. 2 in the case where a silicon-based material is used.

Process a)

First, an SOI substrate having a buried insulating film 2 and an SOI film 3 on a base silicon layer 1 is prepared. This SOI substrate structure is formed by, for example, a SI MOX method or a bonding method. As shown in FIG. 2A, first, a gate insulating film 4 is formed on the SOI film 3 by a thermal oxidation method or the like. Next, as a part of the gate electrode, a first polycrystalline silicon film 5a is deposited to a thickness of, for example, 200 to 10 nm by a CVD method or the like. Further, for example, a silicon nitride film 6 having a thickness of, for example, 0 to 300 nm is deposited as a stopper film in the CMP step. The silicon nitride film is also effective for suppressing the oxidation of the surface of the first polycrystalline silicon film when forming the side oxide film in a later step. However, a stopper film such as a silicon nitride film may not be formed as long as it can be planarized with an acceptable level of controllability in the planarization step.

Step b)

Next, as shown in FIG. 2 (b), after a resist 9 is formed on the silicon nitride film 6, patterning is performed using a normal exposure and development process so that the resist remains in a portion to be an element region. The silicon nitride film 6, the first polycrystalline silicon film 5a, the gate insulating film 4 and the SOI film 3 are etched by plasma etching until the buried insulating film 2 is exposed. To form

Process)

Next, as shown in FIG. 2 (c), after removing the resist 9, a cleaning step is performed. By optimizing the cleaning step and the side oxidation step to be performed next, it is possible to form a bird's beak portion of the present invention. After the resist is stripped, it is preferable to wash the resist. As a cleaning method, SPM cleaning (aqueous solution of sulfuric acid and hydrogen peroxide) or a combination of SPM cleaning and APM cleaning (aqueous solution of ammonia and hydrogen peroxide) is preferable. By this cleaning, the edge of the gate insulating film 4 is etched, and the penetration distance of the parse beak varies depending on the degree of the etching. The degree of the etching of the gate insulating film depends on the selection of the cleaning solution.

In the SPM cleaning, the etching rate of the silicon oxide film is extremely low (for example, 1/47) compared to the processing using both the SPM cleaning and the APM cleaning. Therefore, only the SPM is required to reduce the penetration distance. Is preferred. As the SPM cleaning liquid, a commonly used mixture of about 96% by weight of concentrated sulfuric acid and about 30% by weight of hydrogen peroxide having a mixing volume ratio of about 1: 1 to 10: 1 can be used. The washing time can be appropriately selected, but is usually 1 to 10 minutes. SPM cleaning solution concentration, cleaning Depending on the time, the bird's beak penetration does not seem to have much effect.

For the APM cleaning liquid, use a commonly used mixture of about 30% by weight of ammonia, about 30% by weight of hydrogen peroxide, and pure water with a mixing volume ratio of about 1: 1: 20 to 1:10:20. be able to. The washing time can be appropriately selected, but is usually 1 to 30 minutes. However, since the penetration distance of the parse beak differs depending on the concentration of the APM cleaning solution and the cleaning time, it is preferable to appropriately set the penetration depth in accordance with the intended penetration amount.

Process d)

Next, as shown in FIG. 2D, in order to improve the reliability of element isolation, the side surfaces of the SOI film and the first polycrystalline silicon film are oxidized to form side surface oxide films 10. The penetration distance of the purse beak can also be controlled by the conditions of this oxidation step. In order not to increase the penetration distance excessively, it is preferable to use an atmosphere in which oxygen is diluted with nitrogen without using hydrogen gas. The oxidation is preferably performed by thermal oxidation under dry conditions.

The thickness of the side oxide film is 1 nm or more, usually about the thickness of the gate insulating film (1 to 2 nm) or more, preferably 3 nm or more. Also, if the side oxide film is made thicker, the penetration distance of the pulse beak becomes larger, so that it is preferably 25 nm or less, more preferably 20 nm or less.

Further, by changing the conditions of the oxidation step, the gate insulating film can be formed vertically asymmetrically, that is, the gate insulating films can be formed so that the penetration distances L1 and L2 are different. In particular, at relatively high temperatures, 850-1100, e.g., 950 ° C, L1 and L2 are formed almost equally, and at lower temperatures, 600-850 ° C, e.g., 700 ° C, L1 is greater than L2. growing. Also, at that time, the radius of curvature is larger on the upper side of the gate insulating film than on the lower side.

In this step, the edge of the gate insulating film etched in the previous cleaning step is also oxidized to form a purge peak. The buried oxide film is also thickened near the SOI end. It is also effective in annihilating the level formed in the element isolation region etching process, and is effective in reducing the leak current of the gate insulating film and improving the reliability.

Step e) Next, as shown in FIG. 2E, an element isolation film 7 is deposited in the element isolation groove 7a, for example, a silicon oxide film having a thickness of 50 to 500 nm, for example, about 300 nm, is deposited by a normal plasma CVD method. .

Cleaning is preferably performed as a pretreatment, and a cleaning method with a very low etching rate of the silicon oxide film, for example, SPM cleaning is preferably used. By using a cleaning method in which the etching rate of the silicon oxide film is very low, the space between the first polysilicon film 5 and the SOI film 3 is constituted only by the gate insulating film or the silicon oxide film 71. You. In general, an insulating film formed by CVD or the like has inferior insulating properties to an insulating film formed by thermal oxidation, but by using a cleaning method with a very low etching rate, an element isolation film formed by CVD or the like can be used. It does not enter the gate insulating film.

After that, the element isolation film 7 is planarized by chemical mechanical polishing (CMP) using the silicon nitride film 6 as a stopper to form the structure shown in FIG. 2 (e). Is done.

Process f)

Next, as shown in FIG. 2 (f), the silicon nitride film 6 is removed, and the first polycrystalline silicon film 5 is exposed. When the silicon nitride film 6 is removed, it is preferable to use, for example, a wet etching using a phosphoric acid solution, and thereafter to perform a treatment before the polycrystalline silicon deposition, for example, with a hydrofluoric acid solution. When isotropic etching such as treatment with a phosphoric acid solution and a hydrofluoric acid solution is performed, the upper end of the element isolation film 7 is also isotropically etched to form notches 11.

When the silicon nitride film 6 is removed, the silicon nitride film 6 and the silicon oxide film (element isolation film) 7 are etched at a constant rate, instead of the selective removal of silicon nitride as described above. By doing so, it is possible to remove the silicon nitride film while keeping the flat shape, so that the notch 11 is not formed.

Process

Next, as shown in FIG. 2 (g), a second polycrystalline silicon film 5b is deposited to a thickness of 10 to 200 nm, for example, 5 O nm thick by a normal CVD method as a gate electrode for contact extraction. . When the notch 1 1 is formed as in this example, the second The polycrystalline silicon film 5b extends to the element isolation film 7 more than the end of the first polycrystalline silicon film 5a. With such a notch, the resistance of the gate electrode can be reduced accordingly. For this purpose, a desirable spread distance L4 of the notch is, for example, from:! To 50 nm, and preferably about 5 to 10 nm. Further, the step is desirably 200 nm or less, and more desirably 10 nm or less, from the viewpoint of ensuring alignment during manufacturing.

Step h)

Next, as shown in FIG. 2 (h), the gate electrode is etched by a normal high-density plasma etching technique after patterning by a normal exposure technique so as to leave a resist in a portion to be a gate electrode. Next, the resist is peeled off by an ordinary method to complete a gate electrode having a laminated structure of the second polycrystalline silicon film 5b and the first polycrystalline silicon film 5a.

After that, the gate sidewall insulating film, source / drain regions, and silicide film are formed, an interlayer insulating film is deposited, and wiring is formed to complete the MISFET. Example

In the manufacturing method described in the embodiment, conditions were set as described below. In step a), an SOI substrate having a 100 nm buried insulating film formed on a silicon substrate by a SI MOX method and a 30 nm thick silicon SOI film is prepared, and a gate insulating film 4 is formed using an oxygen nitride gas (NO Using a mixed gas of) and oxygen, a 1.9 nm thick silicon oxynitride film (SiON film) was formed by thermal oxidation at 950. Next, as a part of the gate electrode, a first polycrystalline silicon film 5 is deposited to a thickness of 50 nm by a normal CVD method at 620 ° C., and then silicon nitride used as a stopper film in the CMP process is formed. Film 6 was deposited to a thickness of 100 nm by CVD at 160 ° C.

In the step b), the element isolation groove 7a was formed by the steps described in the embodiment. At this time, the mask pattern was changed to form each gate width (0.3 m to 10 m) of FIG. 6 described later. In step c), after the resist 9 was stripped, the resist 9 was washed using an SPM cleaning solution (containing concentrated sulfuric acid and hydrogen peroxide). In step d), using a gas obtained by diluting oxygen with nitrogen (oxygen: nitrogen = 1: 4), dry oxidation is performed at 950 ° C. on the side surfaces of the SOI layer and the first polycrystalline silicon film. 71 was formed to a thickness of 20 nm.

In step e), after forming an element isolation groove and performing SPM cleaning (the cleaning liquid is the same as that used in step c)), a 300 nm thick element isolation insulating film 7 is formed by a normal plasma CVD method. A silicon oxide film was formed. Thereafter, the element isolation insulating film 7 was planarized by a chemical mechanical polishing method using the silicon nitride film 6 as a stopper. In the step), the silicon nitride film 6 was removed with a phosphoric acid solution, and then with a hydrofluoric acid solution. Pre-processed.

In step g), a second polycrystalline silicon film 8 was deposited to a thickness of 50 nm by a normal CVD method as a gate electrode for contact extraction. The second polycrystalline silicon film 8 was formed so as to be wider by 5 nm on the element isolation insulating film 7 side than the end of the first polycrystalline silicon film 8.

In step h), the MOS SFET was fabricated by patterning the gate length to 50 nm and performing the steps after the formation of the gate-side wall insulating film.

In Example 1, the cleaning after removing the resist 9 in the step c) was performed using an SPM cleaning liquid (containing concentrated sulfuric acid and hydrogen peroxide) and an APM cleaning liquid (containing ammonia and hydrogen peroxide). Example 1 was repeated except that after the cleaning, the APM cleaning was further performed.

FIGS. 3A and 3B show XX and cross-sectional views of the semiconductor devices formed in Example 1 and Example 2 in the direction perpendicular to the channel direction, respectively.

From these figures, it can be seen that the distance between the first polycrystalline silicon film 5 and the SOI film 3 becomes gradually thicker from the device center toward the device isolation end. Also, SO It can be seen that the distance between the I film 3 and the silicon substrate 1 gradually increases in thickness from the element center to the element isolation end at the end. The thickness of the SOI film 3 is gradually reduced from the center of the device to the isolation end.

In the M〇S FET manufactured in Example 1, 1 was 1 511111, 2 was 1 511111, and L3 was 5 nm. The ratio of the S〇I film thickness to be thinned was less than 20% of the SOI film thickness in the element region.

In the semiconductor device manufactured in Example 2, 1 ^ 1 was 2511111, 2 was 25! 1111, and L3 was 5 nm.

FIG. 4 is a graph showing the gate width dependence of the threshold voltage of an nMOS FET having a gate length of 1 m formed by changing the gate width in Examples 1 and 2. FIG. 5 is a graph showing IV measurement results of 5000 MOS FETs having a gate length of 1 _m and a gate width of 2 m manufactured in Example 1 and Example 2 in parallel.

Both the MOSFET manufactured by the manufacturing method of Example 1 and the MOSFET manufactured by the manufacturing method of Example 2 show a decrease in the threshold voltage and a decrease in the gate leakage current, but the MOSFET manufactured in Example 1 However, as compared with the MOSFET manufactured in Example 2, the threshold voltage fluctuation can be further suppressed, and the inverse narrow channel effect is significantly suppressed. In the MOSFET of the first embodiment, for example, when the gate width is 0.4 m, the threshold voltage fluctuation width is 5 OmV or less.

In the present invention, the presence of the bird's beak reduces the electric field concentration at the upper end of the SOI film. However, it can be seen that the penetration distance of the parse beak is preferably not too large.

In Example 3, in Step d) of Example 1, the temperature of the formation of the side oxide film was lowered, and thermal oxidation was performed at a relatively low temperature of 700. Under these conditions, the oxidation rate of polycrystalline silicon is higher than that of single crystal silicon, and as a result, the upper and lower asymmetry of the gate insulating film increases. The oxidation rate of polycrystalline silicon at 700 ° C is about 10 to 20% faster than that of monocrystalline silicon, depending on the film quality. When side oxidation is performed under such conditions, the penetration distances L l and L 2 are also approximately the oxidation rate ratio. And an asymmetrical pearlsby formation is realized. Industrial applicability

According to the present invention, antenna damage resistance, gate leak current,

It is possible to improve the characteristics of TDDB (time delay dielectric breakdown) and the controllability of V _Lh (threshold voltage) by V _sub (substrate potential).

In addition, when the penetration distance of the bird's-beak is not too large, even in the case of an element having a very small gate width, it is effective in preventing the threshold voltage from lowering and reducing the leak current.

Claims

The scope of the claims

1. a buried insulating film formed on the base semiconductor layer;

An element isolation film reaching the buried insulating film;

A semiconductor active layer partitioned by the element isolation film and located on the buried insulating film;

A gate insulating film provided on a part of the semiconductor active layer;

A gate electrode provided opposite to the semiconductor active layer via the gate insulating film.

A semiconductor device having

The device isolation film has a lift-up device isolation structure whose upper surface is above the gate insulating film surface as viewed from the substrate,

In a cross section orthogonal to the current direction of the channel and including the gate electrode, the thickness of the gate insulating film is formed at least at a part of the end in contact with the element isolation film from the element center side toward the element isolation film side end. A semiconductor device characterized by having a bird's beak portion that is gradually thicker. '

2. The semiconductor device according to claim 1, wherein the length of the parse beak portion in the gate width direction is 25 nm or less.

3. The semiconductor device according to claim 1, wherein a length of the parse beak portion in a gate width direction is 5% or less of a channel width.

4. The penetration distance of the parse beak portion is vertically asymmetric, and the penetration distance on the gate electrode side is longer than the penetration distance on the semiconductor active layer side. 13. The semiconductor device according to claim 1.

5. In the cross section orthogonal to the current direction of the channel and including the gate electrode, at least a part of the end in contact with the element isolation film, from the element center side to the element isolation film side end, 5. The semiconductor device according to claim 1, further comprising a bottom bird's beak in which the bottom of the semiconductor active layer gradually recedes upward, the thickness becomes thinner, and the buried insulating film becomes gradually thicker. 13. A semiconductor device according to claim 1.

6. The semiconductor device according to claim 5, wherein the length of the bottom bird's beak in the gate width direction is 25 nm or less.

7. a buried insulating film formed on the base semiconductor layer;

An element isolation film reaching the buried insulating film;

A gate insulating film provided on a part of the semiconductor active layer;

A semiconductor device having

In a cross section orthogonal to the current direction of the channel and including the gate electrode, the bottom of the semiconductor active layer is located above at least a part of the end in contact with the element isolation film, from the element center side toward the element isolation film side end. A buried insulating film having a bottom bird's beak portion which gradually retreats and becomes thinner and thinner.

8. The semiconductor device according to claim 7, wherein the length of the bottom parse beak in the gate width direction is 25 nm or less.

9. The semiconductor device according to claim 1, wherein the semiconductor active layer has a thickness of 200 nm or less.

10. The semiconductor device according to claim 1, wherein an upper surface of the element isolation film is located at least 20 nm or more above a central portion of the gate insulating film. 10.

11. The gate electrode is in contact with a gate insulating film, a first gate electrode material located below an upper surface of the element isolation film, and a portion drawn out in contact with the first gate insulating film. Composed of a second gate electrode material forming

In a cross section orthogonal to the current direction of the channel and including the gate electrode, a notch is provided at an end of the upper surface of the element isolation film,

The method according to any one of claims 1 to 10, wherein the second gate electrode material is drawn out to the upper surface of the element isolation film while covering a cutout portion to form a gate electrode. 13. The semiconductor device according to claim 1.

1 2. A buried insulating film formed on the base semiconductor layer,

An element isolation film reaching the buried insulating film;

A gate insulating film provided on a part of the semiconductor active layer;

A semiconductor device having a gate electrode provided to face the semiconductor active layer via the gate insulating film,

The gate electrode is in contact with a gate insulating film, a first gate electrode material located below an upper surface of the element isolation film, and a second material forming a lead portion in contact with the first gate insulating film. Composed of gate electrode material,

In a cross section orthogonal to the channel current direction and including the gate electrode, a notch is provided at an end of the upper surface of the element isolation film,

A semiconductor device, wherein the second gate electrode material is drawn out to the upper surface of the element isolation film while covering a cutout portion to form a gate electrode.

13. A step of preparing a semiconductor substrate having a laminated structure of a base semiconductor layer, a buried insulating film, and a semiconductor layer;

Forming a gate insulating film material on the semiconductor layer;

Depositing a first gate electrode material on the gate insulating film material, forming a resist pattern covering an element region portion, and using this as a resist

Etching a first gate electrode material, a gate insulating film material, and a semiconductor layer to expose at least a part of the buried insulating film, and form an element isolation groove for partitioning the semiconductor layer into a semiconductor active layer. ,

At the same time as oxidizing the exposed side surfaces of the semiconductor active layer, the gate insulating film material and the first gate electrode material to form side oxide films,

(a) a parse beak where the thickness of the insulating film gradually increases from the center of the device toward the end of the isolation trench at the exposed end of the gate insulating film material; and

(b) A bottom parse beak portion in which the bottom portion of the semiconductor active layer gradually recedes upward from the device center side toward the device isolation film side end and becomes thinner, and the buried insulating film becomes gradually thicker.

Forming at least one of:

Depositing a device isolation film material to a thickness at least equal to or greater than the height of the first gate electrode material while filling the device isolation trenches;

Forming a device isolation film by flattening the surface of the device isolation film material, and depositing a second gate electrode material while making electrical connection with the first gate electrode material.

A method of manufacturing a semiconductor device having:

14. a step of preparing a semiconductor substrate having a laminated structure of a base semiconductor layer, a buried insulating film, and a semiconductor layer;

Forming a gate insulating film material on the semiconductor layer;

Depositing a first gate electrode material on the gate insulating film material; depositing a chemical mechanical polishing stopper film on the first gate electrode material; Forming a resist pattern covering the element region on the stopper film, using the resist pattern as a resist, etching the stopper film, the first gate electrode material, the gate insulating film material, and the semiconductor layer; Exposing at least a part of the film to form an element isolation trench for partitioning the semiconductor layer into a semiconductor active layer; exposing the semiconductor active layer, the gate insulating film material and the first gate electrode material; At the same time as oxidizing the side surface to form a side oxide film,

(a) a parse peak portion where the thickness of the insulating film gradually increases from the center of the device toward the end of the isolation trench at the exposed end of the gate insulating film material; and

Forming at least one of:

Depositing an element isolation film material to a thickness of at least the height of the stopper film while filling the element isolation groove;

Forming a device isolation film by flattening the surface of the device isolation film material using the stopper film as a stopper;

Removing the stopper film and then depositing a second gate electrode material.

15. The method according to claim 1, wherein after the step of forming the element isolation trench, at least one of the gate insulating film material and the buried insulating film is cleaned with a cleaning liquid having an etching action. 3. The method for manufacturing a semiconductor device according to 3 or 14.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the cleaning liquid is at least one of a cleaning liquid containing sulfuric acid and hydrogen peroxide and a cleaning liquid containing ammonia and hydrogen peroxide.

17. After the step of forming the element isolation groove, contains ammonia and hydrogen peroxide 15. The method for manufacturing a semiconductor device according to claim 13, wherein cleaning is performed using a cleaning solution containing sulfuric acid and hydrogen peroxide without using a cleaning solution.

18. The semiconductor device according to claim 14, wherein, when the stopper film is removed, a notch is formed by retreating an end surface of an upper surface of the element isolation film by isotropic etching. Production method.