JP2008171910A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device that can reduce fluctuation and deterioration in characteristics. <P>SOLUTION: As a material for offset spacer, a HfSiON film 15 is formed covering a silicon substrate 10 and a gate structure by nitriding the front surface after deposition of HfSiO. Next, the anisotropic dry etching is conducted to the HfSiON film 15 to largely damage only a region along the top surfaces of the silicon substrate 10 and gate electrode layer 14. Next, only the largely damaged region of the HfSiON film 15 is selectively removed with the wet-etching process by conducting the cleaning process for about 90 seconds using the aqueous solution of hydrofluoric acid in the concentration of about 5%. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for reducing variation in characteristics and deterioration.

  In a MOS transistor product having a gate length of 0.1 μm or more and a manufacturing method thereof, a transistor structure using an offset spacer and a process for forming the transistor are generally used (for example, see Non-Patent Document 1). The offset spacer is used to reduce the source-drain leakage and improve the short channel characteristics by separating the starting point for diffusing impurities from the side surface (edge) of the gate electrode layer. A manufacturing method of a semiconductor device including a fine MOS transistor using an offset spacer is as follows.

  First, an element isolation film, a well structure, a gate insulating film, and a gate electrode layer are formed in this order on a silicon substrate.

  Next, a silicon oxide film of 5 to 20 nm is deposited by CVD as an offset spacer material.

  Next, anisotropic dry etching is performed to form a silicon oxide film as an offset spacer leaving only 3 to 18 nm in the vicinity of the side surface (edge) of the gate electrode layer.

  Next, an impurity for SDE (source / drain / extension) and a halo impurity called a punch-through stopper are implanted into the silicon substrate by lithography and ion implantation starting from a position separated from the side surface of the gate electrode layer by the offset spacer length. Thus, the SDE region is formed. Then, an LDD (Lightly Doped Drain) sidewall is formed so that the sidewall length is about 30 to 80 nm. Then, after implanting source / drain impurities deeper than the SDE region, the source / drain regions are formed by diffusing and activating the impurities using a technique such as RTA (Rapid Thermal Annealing).

  Through the above steps, a semiconductor device including a fine MOS transistor is formed. A process for forming such a MOS transistor is described in, for example, Patent Document 1.

JP 2004-356576 A Symp. VLSI Technology, 2003, p. 140

  As described above, in the conventional method for manufacturing a semiconductor device, an offset spacer is formed by depositing a silicon oxide film as an offset spacer material and then performing only anisotropic dry etching. In this anisotropic dry etching, since the selection ratio of silicon oxide to silicon has a predetermined (finite) value, the silicon oxide film is left only in the vicinity of the side surface of the gate electrode layer uniformly within the surface of the silicon substrate. In such a case, the silicon substrate outside the offset spacer is etched by 5 to 15 nm by overetching. As a result, the junction depth in the SDE region becomes deeper than the channel region. Accordingly, since the short channel characteristics of the MOS transistor are deteriorated, there is a problem that the influence of the characteristic variations such as the threshold voltage and the drive current becomes large with respect to the gate length variation that is always generated in the manufacturing process of the semiconductor device such as ULSI. there were.

  In order to prevent deterioration of short channel characteristics, it is conceivable to increase the concentration of impurities implanted as a punch-through stopper, but in this case, since channel mobility decreases, There is a problem in that the junction capacity increases and the junction leakage current increases, and the characteristics deteriorate.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce variation and deterioration in characteristics.

  A method of manufacturing a semiconductor device according to the present invention includes: (a) forming a gate structure in which a gate insulating film and a gate electrode layer are stacked in a predetermined region on a silicon substrate; and (b) the silicon substrate and the gate structure. Forming a first high dielectric film so as to cover the surface, (c) applying anisotropic dry etching to the first high dielectric film and damaging the first high dielectric film, and (d) following the step (c), the first high dielectric film. Leaving the first high dielectric film as an offset spacer on the side surface of the gate structure by performing wet etching using hydrofluoric acid on the film and partially removing the first high dielectric film; and (e) the step (d) And a step of implanting impurities into the silicon substrate later.

  A method of manufacturing a semiconductor device according to the present invention includes: (a) forming a gate structure in which a gate insulating film and a gate electrode layer are stacked in a predetermined region on a silicon substrate; and (b) the silicon substrate and the gate structure. Forming a first high dielectric film so as to cover the surface, (c) applying anisotropic dry etching to the first high dielectric film and damaging the first high dielectric film, and (d) following the step (c), the first high dielectric film. Leaving the first high dielectric film as an offset spacer on the side surface of the gate structure by performing wet etching using hydrofluoric acid on the film and partially removing the first high dielectric film; and (e) the step (d) And a step of implanting impurities into the silicon substrate later. Therefore, since the selection ratio of the offset spacer material to silicon can be increased, the amount of the silicon substrate that is scraped by over-etching outside the offset spacer can be greatly reduced. Therefore, it is possible to reduce the influence of variation in characteristics such as threshold voltage and driving current on variation in gate length that occurs in the manufacturing process of the semiconductor device.

  In the method for manufacturing a semiconductor device according to the present invention, when an offset spacer is formed, a high-k film (high dielectric film) such as Hf silicate is deposited instead of a silicon oxide film as an offset spacer material, and then anisotropic. In addition to reactive dry etching, wet etching using hydrofluoric acid is performed. As a result, the offset spacer material can be etched with little etching of the silicon substrate (in other words, in the wet etching using hydrofluoric acid, the selection ratio of the high-k substance to silicon is almost infinite). Accordingly, it is possible to greatly reduce the amount of silicon substrate to be shaved by over-etching, compared to a conventional method for manufacturing a semiconductor device in which a silicon oxide film is used as an offset spacer material and etching is performed only by anisotropic dry etching. . Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention can be applied to MOS transistor products having a gate length of 0.1 μm or later, but is particularly applicable to all SoC (System On a Chip) products having a 65 nm node or later.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a structure of a semiconductor device 100 including a fine MOS transistor according to the first embodiment. FIG. 2 is a cross-sectional view showing the structure of a conventional semiconductor device for comparison. In FIG. 2, the silicon substrate 10 is shaved and recessed outside the offset spacer made of the silicon oxide film 150, but in FIG. 1, the silicon substrate 10 is shaved outside the offset spacer made of the HfSiON film 15. It is not depressed and not depressed. Therefore, in the semiconductor device 100 of FIG. 1, the junction depth in the SDE region 16 can be made shallower than that of the conventional semiconductor device of FIG.

  3 to 8 are cross-sectional views showing a method for manufacturing the semiconductor device 100 of FIG.

  First, as shown in FIG. 3, a silicon substrate 10 is prepared.

  Next, as shown in FIG. 4, an element isolation film 11 made of a shallow trench silicon oxide film is partially formed in the upper surface of the silicon substrate 10. Then, a well structure is formed by introducing channel impurities.

  Next, as shown in FIG. 5, a gate structure is formed in which a gate insulating film 13 and a gate electrode layer 14 are stacked in a predetermined region of the element region sandwiched and separated between the element isolation films 11. The gate insulating film 13 is formed by forming a high-k film (second high dielectric film) such as HfSiON so that the equivalent oxide thickness (EOT) is about 1.4 nm. The gate electrode layer 14 is formed by forming polycrystalline silicon (polysilicon) so as to have a thickness of about 140 nm.

  Next, as shown in FIG. 6, after depositing HfSiO, which is a high-k substance, as an offset spacer material at a temperature of about 500 ° C. by MO-CVD or the like, it is about 5 to 20 nm (preferably about 10 nm). By nitriding the surface by plasma nitridation or the like, an HfSiON film 15 (first high dielectric film) that covers the silicon substrate 10 and the gate structure is formed (or not only plasma nitridation but also nitridation by other methods) Also good).

  Next, as shown in FIG. 7, the HfSiON film 15 is damaged by performing anisotropic dry etching. Since this damage is thinly applied from the direction perpendicular to the upper surface of the silicon substrate 10, the HfSiON film 15 is greatly damaged in the region 15a along the upper surfaces of the silicon substrate 10 and the gate electrode layer 14, but the HfSiON film The region 15b excluding the region 15a from 15 (that is, the region along the side surface of the gate electrode layer 14) is hardly damaged.

  Next, as shown in FIG. 8, only 90% of the region 15a in the HfSiON film 15 that has been greatly damaged is selectively wet by cleaning with a hydrofluoric acid solution having a concentration of about 5% for about 90 seconds. Etched away. That is, it is possible to make an offset spacer having a thickness of 3 to 18 nm by selectively leaving only the region 15b that is hardly damaged. Since the hydrofluoric acid aqueous solution etches only the HfSiON film 15 without substantially scraping the silicon substrate 10, a removal process with a high selectivity (almost infinite) can be realized by using the hydrofluoric acid aqueous solution. As a result, the offset spacer can be formed with almost no shaving of the silicon substrate 10. Since a cleaning process for removing foreign matters is performed after this, the silicon substrate 10 is slightly cut, but the amount is as small as 1 nm or less.

  Next, as shown in FIG. 1, SDE (source / drain extension) impurities and punch-through are performed by lithography and ion implantation starting from a position separated from the side surface (edge) of the gate electrode layer 14 by the offset spacer length. SDE regions 16 are formed by implanting halo impurities called stoppers into the silicon substrate 10. Then, an LDD (Lightly Doped Drain) sidewall 17 composed of the silicon oxide film 18 and the silicon nitride film 19 is formed so that the sidewall length is about 30 to 80 nm. Then, after implanting source / drain impurities deeper than the SDE region 16, the source / drain regions 20 are formed by diffusing and activating the impurities by a technique such as RTA (Rapid Thermal Annealing). Then, the silicon of the silicon substrate 10 and the gate electrode layer 14 is partially silicided with a metal such as Ni to form a silicide layer 21. Although not shown in FIG. 1, when the source / drain regions 20 are formed, it is possible to increase the thickness by, for example, about 10 to 30 nm using a selective silicon growth technique.

  Through the above steps, the semiconductor device 100 is formed.

  As described above, in the method of manufacturing the semiconductor device 100 according to the present embodiment, when forming the offset spacer, a high-k film such as Hf silicate is used instead of the silicon oxide film 150 as the material for the offset spacer. In addition to anisotropic dry etching, wet etching using hydrofluoric acid is performed. Thereby, since the selection ratio of the material for the offset spacer with respect to silicon can be increased, the amount of the silicon substrate 10 to be shaved by overetching outside the offset spacer can be greatly reduced. Therefore, the junction depth in the SDE region 16 can be prevented from becoming deeper than the channel region, so that the short channel characteristics in the MOS transistor can be prevented from deteriorating. Therefore, it is possible to reduce the influence of variation in characteristics such as threshold voltage and driving current on variation in gate length that occurs in the manufacturing process of the semiconductor device.

  In addition, since it is not necessary to increase the concentration of impurities implanted as a punch-through stopper, channel mobility does not decrease, and drive current, junction capacitance, and junction leakage current characteristics do not deteriorate.

  Further, by using a high-k substance as the offset spacer material, the gate electric field leaking to the SDE region 16 immediately below the LDD sidewall 17 can be increased. Therefore, since the resistance in the SDE region 16 can be lowered, the drive current can be increased.

  In addition, by using a high-k substance as the material for the gate insulating film 13, the gate electric field leaking to the SDE region 16 immediately below the gate insulating film 13 can be increased. Therefore, since the resistance in the SDE region 16 can be lowered, the drive current can be increased.

In the above description, the case where the HfSiON film 15 is used as the offset spacer material has been described. However, the HfSiON film 15 is not limited to the HfSiON film 15, but other Hf silicate films such as an HfSiO film may be used. Further, not only the Hf silicate film but also another Hf oxide film such as HfO ₂ may be used. Further, the film is not limited to the Hf silicate film or the Hf oxide film, or a film containing an oxide or silicate of Zr, La, Pr, or Al may be used.

  In addition, the first high dielectric film constituting the offset spacer and the second high dielectric film constituting the gate insulating film are preferably made of different high-k materials. For example, the first high dielectric film and the second high dielectric film may be combined with each other differently from SiON, Hf oxide, Hf silicate, Zr / La / Pr / Al oxide, or silicate. That's fine.

<Embodiment 2>
In the first embodiment, the silicide layer 21 is formed by siliciding the silicon of the silicon substrate 10 and the gate electrode layer 14 with a metal such as Ni in the same process. However, the present invention is not limited thereto, or the silicon of the silicon substrate 10 and the gate electrode layer 14 may be silicided in another process. By performing silicidation in another process, the amounts of silicon to be silicided can be made different from each other.

  FIG. 9 is a cross-sectional view showing the structure of the semiconductor device 101 including the fine MOS transistor according to the second embodiment. The semiconductor device 101 in FIG. 9 is the same as the semiconductor device 100 in FIG. 1, except that the gate electrode layer 14 made of polysilicon and the silicide layer 21 on the gate electrode layer 14 are replaced by a silicide only (full silicide) gate electrode layer. 14a is formed.

  10 to 17 are cross-sectional views illustrating a method for manufacturing the semiconductor device 101 of FIG.

  First, as shown in FIG. 10, a silicon substrate 10 is prepared.

  Next, as shown in FIG. 11, an element isolation film 11 made of a shallow trench silicon oxide film is partially formed in the upper surface of the silicon substrate 10. Then, a well structure is formed by introducing channel impurities.

  Next, as shown in FIG. 12, the gate insulating film 13, the gate electrode layer 14, and the dummy gate insulating film 31 are laminated in a predetermined region of the element region sandwiched and separated between the element isolation films 11. A gate structure is formed. The gate insulating film 13 is formed by forming a high-k film such as HfSiON so that the equivalent oxide thickness EOT is about 1.4 nm. The gate electrode layer 14 is made of polysilicon so that the film thickness is about 140 nm. The dummy gate insulating film 31 is a silicon nitride film formed so as to have a thickness of about 30 nm.

  Next, as shown in FIG. 13, after depositing HfSiO, which is a high-k substance, as a material for an offset spacer at a temperature of about 500 ° C. by MO-CVD or the like, it is about 5 to 20 nm (preferably about 10 nm). By nitriding the surface by plasma nitridation or the like, an HfSiON film 15 (first high dielectric film) that covers the silicon substrate 10 and the gate structure is formed (or not only plasma nitridation but also nitridation by other methods) Also good).

  Next, as shown in FIG. 14, the HfSiON film 15 is damaged by performing anisotropic dry etching. Since this damage is thinly applied from the direction perpendicular to the upper surface of the silicon substrate 10, the HfSiON film 15 is greatly damaged in the region 15a along the upper surfaces of the silicon substrate 10 and the gate electrode layer 14, but the HfSiON film The region 15b excluding the region 15a from 15 (that is, the region along the side surface of the gate electrode layer 14) is hardly damaged.

  Next, as shown in FIG. 15, only the region 15a in the HfSiON film 15 that has been damaged greatly is selectively wet by performing cleaning for about 90 seconds with a hydrofluoric acid aqueous solution having a concentration of about 5%. Etched away. That is, it is possible to make an offset spacer having a thickness of 3 to 18 nm by selectively leaving only the region 15b that is hardly damaged. Since the hydrofluoric acid aqueous solution etches only the HfSiON film 15 without substantially scraping the silicon substrate 10, a removal process with a high selectivity (almost infinite) can be realized by using the hydrofluoric acid aqueous solution. As a result, the offset spacer can be formed with almost no shaving of the silicon substrate 10. Since a cleaning process for removing foreign matters is performed after this, the silicon substrate 10 is slightly cut, but the amount is as small as 1 nm or less.

  Next, as shown in FIG. 16, an SDE impurity and a halo impurity called a punch-through stopper are introduced into the silicon substrate 10 by lithography and ion implantation starting from a position separated from the side surface of the gate electrode layer 14 by the offset spacer length. By implanting, the SDE region 16 is formed. Then, the LDD sidewall 17 composed of the silicon oxide film 18 and the silicon nitride film 19 is formed so that the sidewall length is about 30 to 80 nm. Then, after implanting source / drain impurities deeper than the SDE region 16, the source / drain regions 20 are formed by diffusing and activating the impurities by a technique such as RTA. Then, the silicide layer 21 is formed by partially siliciding the silicon of the silicon substrate 10 with a metal such as Ni. Although not shown in FIG. 16, when the source / drain regions 20 are formed, it is possible to increase the thickness by, for example, about 10 to 30 nm using a selective silicon growth technique.

  Next, as shown in FIG. 17, a silicon nitride film 41 is deposited by about 30 nm by CVD or the like, and then a silicon oxide film 42 is deposited by about 400 nm. Then, the silicon nitride film 41 and the silicon oxide film 42 are polished by CMP (Chemical Mechanical Polishing) until the dummy gate insulating film 31 made of a silicon nitride film is exposed.

Next, as shown in FIG. 9, the dummy gate insulating film 31 made of a silicon nitride film is selectively removed by wet etching using hot phosphoric acid. Then, after depositing about 100 nm of Ni by sputtering or the like and silicidizing by RTA at about 300 ° C., unreacted Ni is selectively removed with a chemical solution containing hydrogen peroxide (H ₂ O ₂ ). . Thereby, the gate electrode layer 14a made of Ni silicide obtained by reacting the polysilicon of the gate electrode layer 14 with Ni can be formed.

  Through the above steps, the semiconductor device 101 is formed.

  As described above, in the method of manufacturing the semiconductor device 101 according to the present embodiment, the dummy gate insulating film 31 is used, so that the silicon substrate 10 is hardly over-etched outside the offset spacer, and the gate electrode made of polysilicon is used. Instead of the layer 14 and the silicide layer 21 on the gate electrode layer 14, a fully silicided gate electrode layer 14a is formed. Therefore, in addition to the effect of the first embodiment, there is an effect that the resistance in the gate electrode layer can be lowered.

<Embodiment 3>
In the first and second embodiments, the semiconductor devices 100 to 101 are manufactured using the silicon substrate 10, but not limited to the silicon substrate 10, an SOI (Silicon On Insulator) substrate may be used.

  FIG. 18 is a cross-sectional view showing the structure of the semiconductor device 102 including the fine MOS transistor according to the third embodiment. A semiconductor device 102 in FIG. 18 uses an SOI substrate 10a instead of the silicon substrate 10 in the semiconductor device 100 in FIG. Note that there are SOI type MOS transistors that perform a partial depletion operation and those that perform a full depletion operation, but the semiconductor device 102 of FIG. 18 shows a type that performs a partial depletion operation (SDE region). (When 16 reaches the buried oxide film 10c, a full depletion operation is performed, and when the SDE region 16 does not reach the buried oxide film 10c, a partial depletion operation is performed).

  19 to 24 are cross-sectional views illustrating a method of manufacturing the semiconductor device 102 of FIG.

  First, as shown in FIG. 19, an SOI substrate 10a is prepared. This SOI substrate 10a is obtained by sequentially forming a buried oxide film (BOX) 10c and an SOI layer 10d on a silicon substrate 10b. For example, in a MOS transistor having a gate length of 50 nm, the thickness of the SOI layer 10d is about 30 to 50 nm when performing a partial depletion operation, and about 20 nm when performing a full depletion operation.

  Next, as shown in FIG. 20, an element isolation film 11 made of a shallow trench silicon oxide film is partially formed in the upper surface of the SOI substrate 10a. When a partial depletion operation is performed, a well structure is formed by introducing channel impurities (when a full depletion operation is performed, no channel impurities are introduced). The element isolation film 11 is formed so as to penetrate the SOI layer 10d and reach the buried oxide film 10c and stop. Although not shown in FIG. 20, the SOI layer 10d may be separated by dry etching.

  Next, as shown in FIG. 21, a gate structure is formed in which a gate insulating film 13 and a gate electrode layer 14 are stacked in a predetermined region of the device region sandwiched and separated between the device isolation films 11. The gate insulating film 13 is formed by forming a high-k film such as HfSiON so that the equivalent oxide thickness EOT is about 1.4 nm. The gate electrode layer 14 is made of polysilicon so that the film thickness is about 140 nm.

  Next, as shown in FIG. 22, after depositing HfSiO, which is a high-k substance, as an offset spacer material at a temperature of about 500 ° C. by MO-CVD or the like, it is 5 to 20 nm (preferably about 10 nm). By nitriding the surface by plasma nitriding or the like, an HfSiON film 15 (first high dielectric film) that covers the SOI substrate 10a and the gate structure is formed (or not only plasma nitridation but also nitriding by other methods) Also good).

  Next, as shown in FIG. 23, the HfSiON film 15 is damaged by performing anisotropic dry etching. Since this damage is thinly applied from the direction perpendicular to the upper surface of the silicon substrate 10, the HfSiON film 15 is greatly damaged in the region 15 a along the upper surfaces of the SOI substrate 10 a and the gate electrode layer 14. The region 15b excluding the region 15a from 15 (that is, the region along the side surface of the gate electrode layer 14) is hardly damaged.

  Next, as shown in FIG. 24, only the region 15a in the HfSiON film 15 which is greatly damaged is selectively wet by performing cleaning for about 90 seconds with a hydrofluoric acid aqueous solution having a concentration of about 5%. Etched away. That is, it is possible to make an offset spacer having a thickness of 3 to 18 nm by selectively leaving only the region 15b that is hardly damaged. Since the hydrofluoric acid aqueous solution etches only the HfSiON film 15 without substantially scraping the silicon substrate 10, a removal process with high selectivity (almost infinite) can be realized by using the hydrofluoric acid aqueous solution. As a result, it is possible to form an offset spacer without substantially removing the SOI substrate 10a (SOI layer 10d). In addition, since a cleaning process for removing foreign matters and the like is performed thereafter, the SOI substrate 10a (SOI layer 10d) is slightly cut, but the amount is as small as 1 nm or less.

  Next, as shown in FIG. 18, an SDE impurity and a halo impurity called a punch-through stopper are introduced into the silicon substrate 10 by lithography and ion implantation, starting from a position separated from the side surface of the gate electrode layer 14 by the offset spacer length. By implanting, the SDE region 16 is formed. Then, the LDD sidewall 17 composed of the silicon oxide film 18 and the silicon nitride film 19 is formed so that the sidewall length is about 30 to 80 nm. Then, after implanting source / drain impurities deeper than the SDE region 16, the source / drain regions 20 are formed by diffusing and activating the impurities by a technique such as RTA. Then, the silicide layer 21 is formed by siliciding the silicon of the SOI layer 10d and the gate electrode layer 14 partially with a metal such as Ni. Although not shown in FIG. 18, when the source / drain regions 20 are formed, it is possible to increase the thickness by, for example, about 10 to 30 nm using a selective silicon growth technique. Although not shown in FIG. 18, in the case of performing a full depletion operation, the SDE region 16 is formed to reach the buried oxide film 10c.

  Through the above steps, the semiconductor device 102 is formed.

  As described above, in the method for manufacturing the semiconductor device 102 according to the present embodiment, the SOI substrate 10a is used in place of the silicon substrate 10, so that the SOI type MOS is hardly over-etched on the outside of the offset spacer without over-etching the SOI substrate 10a. A transistor is formed.

  Therefore, when the partial depletion operation is performed, the same effects as those of the first embodiment are obtained.

  Further, in the case of performing the full depletion operation, the SOI layer 10d has a thickness as thin as about 20 nm as compared with the case of performing the partial depletion operation, and thus the parasitic resistance tends to increase. However, overetching of the SOI layer 10d is prevented. Thus, increase in parasitic resistance can be prevented. Therefore, in addition to the effect of the first embodiment, the drive current can be increased.

<Embodiment 4>
In the first to third embodiments, the case where the offset spacer made of the HfSiON film 15 is formed outside after forming the gate structure in which the gate insulating film 13 and the gate electrode layer 14 are stacked has been described. However, the present invention is not limited to this, or the gate structure may be formed inside the offset spacer after forming the offset spacer by using a known replacement gate electrode forming process.

  FIG. 25 is a cross-sectional view showing the structure of the semiconductor device 103 including the fine MOS transistor according to the fourth embodiment. A semiconductor device 103 in FIG. 25 is obtained by forming a gate structure in which the gate insulating film 13 and the gate electrode layer 14 are stacked in the semiconductor device 100 in FIG. 1 by using a replacement gate electrode formation process.

  26 to 35 are cross-sectional views illustrating a method for manufacturing the semiconductor device 103 of FIG.

  First, as shown in FIG. 26, a silicon substrate 10 is prepared.

  Next, as shown in FIG. 27, an element isolation film 11 made of a shallow trench silicon oxide film is partially formed in the upper surface of the silicon substrate 10. Then, a well structure is formed by introducing channel impurities.

  Next, as shown in FIG. 28, in a predetermined region of the element region sandwiched and isolated between the element isolation films 11, a dummy gate insulating film 51, a dummy gate electrode layer 52, and a dummy gate insulating layer 53 are formed. A dummy gate structure is formed. The dummy gate insulating film 51 is a silicon oxide film formed so as to have a film thickness of 5 nm or less. The dummy gate electrode layer 52 is made of polysilicon so that the film thickness is about 140 nm. The dummy gate insulating film 53 is a silicon nitride film formed so as to have a thickness of about 30 nm.

  Next, as shown in FIG. 29, an SDE impurity and a halo impurity called a punch-through stopper are implanted into the silicon substrate 10 from the side surface of the gate electrode layer 14 by lithography and ion implantation. Form. Then, an LDD sidewall made of only the silicon oxide film 54 is formed so that the sidewall length is about 30 to 80 nm. Then, after implanting source / drain impurities deeper than the SDE region 16, the source / drain regions 20 are formed by diffusing and activating the impurities by a technique such as RTA. Then, the silicide layer 21 is formed by partially siliciding the silicon of the silicon substrate 10 with a metal such as Ni. Although not shown in FIG. 29, when the source / drain regions 20 are formed, it is possible to use a selective silicon growth technique to increase the thickness by, for example, about 10 to 30 nm.

  Next, as shown in FIG. 30, a silicon oxide film 55 is deposited to a thickness of about 400 nm by CVD or the like. As a result, the silicon oxide film 54 is integrated with the silicon oxide film 55, and the dummy gate structure is covered with the silicon oxide film 55. Then, the silicon oxide film 55 is polished by CMP until the dummy gate insulating film 53 made of a silicon nitride film is exposed.

  Next, as shown in FIG. 31, the dummy gate insulating film 53 made of a silicon nitride film is selectively removed by wet etching using hot phosphoric acid. Then, the dummy gate electrode layer 52 made of polysilicon is removed by performing isotropic polysilicon etching or the like. Thus, a gate region which is a groove-like opening for providing the gate electrode layer 14b in a later step is formed. Then, the dummy gate insulating film 51 made of a silicon oxide film and a part of the silicon oxide film 55 outside the gate region are removed by wet etching with a hydrofluoric acid aqueous solution or the like. Thereby, the dummy gate structure is removed. At this time, by adjusting the etching time, the amount of the silicon oxide film 55 to be removed can be adjusted to adjust the width of the gate region. That is, as shown in FIG. 25, in a later step, the gate electrode layer 14b made of W or the like, the gate insulating film made of the bottom surface of the HfSiO film 56, the side surface of the HfSiO film 56, and the offset spacer made of the HfSiON film 15 are formed. When formed, the overlap amount (arrow) of the SDE region 16 with respect to the gate electrode layer 14b can be easily adjusted according to the thickness of the offset spacer.

  Next, as shown in FIG. 32, after depositing HfSiO, which is a high-k material, as a material for an offset spacer at a temperature of about 500 ° C. by MO-CVD or the like, it is 5 to 20 nm (preferably about 10 nm). By nitriding the surface by plasma nitridation or the like, an HfSiON film 15 (first high dielectric film) is formed so as to cover the silicon substrate 10 and the silicon oxide film 55 (or nitridation is not limited to plasma nitridation but by other methods) You may).

  Next, as shown in FIG. 33, the HfSiON film 15 is damaged by performing anisotropic dry etching. Since this damage is thinly applied from the direction perpendicular to the upper surface of the silicon substrate 10, the HfSiON film 15 is greatly damaged in the region 15a along the upper surfaces of the silicon substrate 10 and the gate electrode layer 14b. The region 15b excluding the region 15a from 15 (that is, the region along the side surface of the gate region) is hardly damaged.

  Next, as shown in FIG. 34, cleaning is performed for about 90 seconds with a hydrofluoric acid aqueous solution having a concentration of about 5%, so that only the heavily damaged region 15a of the HfSiON film 15 is selectively wetted. Etched away. That is, it is possible to make an offset spacer having a thickness of 3 to 18 nm by selectively leaving only the region 15b that is hardly damaged. Since the hydrofluoric acid aqueous solution etches only the HfSiON film 15 without substantially scraping the silicon substrate 10, a removal process with a high selectivity (almost infinite) can be realized by using the hydrofluoric acid aqueous solution. As a result, the offset spacer can be formed in the gate region without substantially removing the silicon substrate 10. Since a cleaning process for removing foreign matters is performed after this, the silicon substrate 10 is slightly cut, but the amount is as small as 1 nm or less.

  Next, as shown in FIG. 35, after adjusting the impurity concentration of the channel region by ion implantation or the like, HfSiO as a high-k material is deposited by about 5 nm at a temperature of about 500 ° C. by the MO-CVD method or the like. Thus, the HfSiO film 56 is formed. The HfSiO film 56 may be oxidized and nitrided as necessary.

  Next, as shown in FIG. 25, after depositing about 200 nm of a metal such as W as a material for the gate electrode layer 14b on the gate region by a sputtering method, a CVD method, or the like, The HfSiO film 56 is polished. As a result, a gate structure is formed in which the gate electrode layer 14b and the HfSiO film 56 (the bottom surface thereof) as the gate insulating film are stacked only in the groove-shaped gate region. That is, in the HfSiO film 56, the region along the lower surface of the gate electrode layer 14b functions as the gate insulating film or the second high dielectric film according to the present invention, and the region along the side surface of the gate electrode layer 14b is (the HfSiON film 15 and It functions as an offset spacer according to the present invention.

  Through the above steps, the semiconductor device 103 is formed.

  Thus, in the method of manufacturing the semiconductor device 103 according to the present embodiment, when forming the offset spacer using the replacement gate electrode formation process, the high-k film such as Hf silicate is used as the material for the offset spacer. In addition to anisotropic dry etching, wet etching using hydrofluoric acid is performed. Thereby, since the selection ratio of the material for the offset spacer with respect to silicon can be increased, the amount of the silicon substrate 10 scraped by over-etching inside the offset spacer can be greatly reduced.

  In the semiconductor device manufacturing method using the conventional replacement gate electrode formation process, the silicon substrate 10 is over-etched inside the offset spacer, so that the junction depth in the SDE region 16 becomes shallower than the channel region. Since the SDE region 16 and the channel region are connected in a region having a low impurity concentration, there is a problem that parasitic resistance increases. In the manufacturing method of the semiconductor device 103 according to the present embodiment, it is possible to prevent the silicon substrate 10 from being over-etched inside the offset spacer, so that an increase in parasitic resistance can be prevented and a drive current can be increased.

  Further, in the conventional method for manufacturing a semiconductor device using a replacement gate electrode formation process, a high-k film in which a gate insulating film and an offset spacer are integrated is formed in the same process. In the method for manufacturing the semiconductor device 103, after the high-k film (HfSiON film 15) functioning as an offset spacer is formed, the high-k film (HfSiO film 56) functioning as an offset spacer and a gate insulating film is formed in another process. Form with. Therefore, the film thickness of the offset spacer and the film thickness of the gate insulating film can be adjusted independently (the film thickness of the gate insulating film <the film thickness of the offset spacer can be freely adjusted). .

  Similarly to the first embodiment, by using a high-k substance as the offset spacer material, the gate electric field leaking to the SDE region 16 immediately below the LDD sidewall can be increased. Therefore, as in the first embodiment, the resistance in the SDE region 16 can be reduced, and the drive current can be increased.

  Further, as in the first embodiment, by using a high-k substance as the gate insulating film material, the gate electric field leaking to the SDE region 16 immediately below the gate insulating film can be increased. Therefore, as in the first embodiment, the resistance in the SDE region 16 can be reduced, and the drive current can be increased.

1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment. It is sectional drawing which shows the structure of the semiconductor device for a comparison. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. FIG. 6 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view showing a structure of a semiconductor device according to a third embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. 6 is a cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment.

Explanation of symbols

  10, 10b Silicon substrate, 10a SOI substrate, 10c buried oxide film, 10d SOI layer, 11 element isolation film, 13 gate insulating film, 14, 14a, 14b gate electrode layer, 15 HfSiON film, 15a, 15b region, 18, 33 , 42, 54, 55, 150 Silicon oxide film, 16 SDE region, 17 LDD sidewall, 19, 32, 41 Silicon nitride film, 20 source / drain region, 21 silicide layer, 31, 51, 53 dummy gate insulating film, 52 dummy gate electrode layer, 56 HfSiO film, 100-103 semiconductor device.

Claims (11)

(A) forming a gate structure in which a gate insulating film and a gate electrode layer are stacked in a predetermined region on a silicon substrate;
(B) forming a first high dielectric film so as to cover the silicon substrate and the gate structure;
(C) applying anisotropic dry etching to the first high dielectric film to cause damage;
(D) Subsequent to the step (c), the first high dielectric film is wet-etched using hydrofluoric acid to partially remove the first high dielectric film, whereby the first high dielectric film is formed on the side surface of the gate structure. Leaving the dielectric film as an offset spacer;
(E) A method of manufacturing a semiconductor device comprising a step of implanting impurities into the silicon substrate after the step (d). A method of manufacturing a semiconductor device according to claim 1,
The method (a) is a method of manufacturing a semiconductor device, including a step of forming a second high dielectric film as the gate insulating film. A method of manufacturing a semiconductor device according to claim 1 or 2,
The step (b) is a method of manufacturing a semiconductor device, which includes a step of forming a film containing Hf oxide or Hf silicate as the first high dielectric film. A method of manufacturing a semiconductor device according to claim 3,
The method (b) is a method of manufacturing a semiconductor device, which includes a step of forming a film containing HfO ₂ , HfSiO, or HfSiON as the first high dielectric film. A method of manufacturing a semiconductor device according to claim 1 or 2,
The method (b) is a method of manufacturing a semiconductor device, comprising forming a film containing an oxide or silicate of Hf, Zr, La, Pr, or Al as the first high dielectric film. A method of manufacturing a semiconductor device according to claim 2,
A method of manufacturing a semiconductor device, wherein the second high dielectric film formed in the step (a) and the first high dielectric film formed in the step (b) are made of different materials. A method for manufacturing a semiconductor device according to any one of claims 1 to 6,
The step (a) includes a step of forming a polysilicon layer as the gate electrode layer,
(F) A method of manufacturing a semiconductor device, further comprising a step of causing the polysilicon layer to undergo a silicide reaction with a predetermined metal. A method of manufacturing a semiconductor device according to claim 7,
Following the step (a), forming a silicon nitride film on the polysilicon layer;
And a step of removing the silicon nitride film on the polysilicon layer and forming the predetermined metal after the step (e) and before the step (f). A method for manufacturing a semiconductor device according to any one of claims 1 to 8,
A method for manufacturing a semiconductor device using an SOI substrate in which a buried oxide film and an SOI layer are provided on a silicon substrate instead of the silicon substrate. (A-1) forming a dummy gate structure in a predetermined region on the silicon substrate;
(A-2) forming a planarized silicon oxide film with the dummy gate structure;
(A-3) removing the dummy gate structure and forming an opening;
(B-1) forming a first high dielectric film so as to cover the silicon substrate and the silicon oxide film;
(C) applying anisotropic dry etching to the first high dielectric film to cause damage;
(D-1) Subsequent to the step (c), the first high dielectric film is wet-etched using hydrofluoric acid to partially remove the first high dielectric film, whereby the silicon oxide film in the opening is removed. Leaving the first high dielectric film as an offset spacer on the side surface of
(E-1) a step of implanting impurities into the silicon substrate after the step (d-1);
(G) forming a gate structure in which a gate insulating film and a gate electrode layer are stacked in the predetermined region. A method of manufacturing a semiconductor device according to claim 10,
The method (g) is a method of manufacturing a semiconductor device, which includes a step of forming a second high dielectric film as the gate insulating film.

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