WO2004034547A1

WO2004034547A1 - A charge controlling method for a batterywith dinamic negative increment of voltage and its charging circuit

Info

Publication number: WO2004034547A1
Application number: PCT/CN2003/000848
Authority: WO
Inventors: Yuhuan Liu
Original assignee: Yuhuan Liu
Priority date: 2002-10-09
Filing date: 2003-10-08
Publication date: 2004-04-22
Also published as: CN2574279Y; AU2003299393A1

Abstract

A charge controlling method for a battery with dynamic -ΔV voltage and its charging circuit are disclosed, in which the method includes: a range(V4∼V5) of negative increment of voltage and the minimum rising rate of the sample-and-hold point are set; the voltage of the sample-and-hold point moves to the lower point (V5) of the range of the negative increment of voltage when the rising rate of the charging cell voltage is higher than the minimum rising rate of the sample-and-hold point, and charging is continued after reaching the lower point (V5); on the contrary, the voltage of the sample-and-hold point moves to the higher point (V4) of the range of negative increment of voltage, and charging is finished when reaching the higher point (V4); during the rise of the voltage of the sample-and-hold point, if the cell voltage drops charging is finished when the higher point (V4) of the range of negative increment of voltage meets the sample-and-hold point (V6). And the circuit includes a voltage peak sample-and-hold and input voltage comparison controlling circuit.

Description

Dynamic voltage negative incremental battery charging control method and charging circuit

The invention relates to a dynamic voltage negative incremental battery charging control method and a charging circuit thereof. Background technique

Ni-Cd-Ni-MH batteries can be detected by negative voltage increment (-Δ ν) during charging (that is, the voltage will increase when the battery is charged, the voltage will be the maximum when fully charged, and the voltage will decrease when it is overcharged. That is, the characteristics of "-Δ" appear to complete the automatic control of the charging process), which effectively makes the battery fully charged and prevents overcharging and undercharging.

At present, a dedicated chip is generally used in a battery charging circuit. The -Δ ν detection value of a single battery does not change during the charging process. The structure is shown in FIG. 1, which includes a battery voltage dividing voltage sampling circuit 1 ′, and a sample and hold circuit. The comparison control circuit 2 'and the controlled charging circuit 3' are composed of: the sample-and-hold comparison control circuit 2 'includes an A / D (Analog / Digital) conversion module 21' and-Δ ν charge state control module 22 '. Because this special chip uses the A / D conversion method to detect the battery voltage, it requires high accuracy (especially the detection accuracy of the nickel-metal hydride battery voltage is higher than that of the nickel-cadmium battery), so there are many A / D conversion digits, most of which use 12 to 13 Bit A / D conversion causes cost increase.

The disadvantages of the aforementioned dedicated-Δ ν charge control chip are:

(1) The product manufacturing cost is high.

(2) Its single block-A V value is fixed and cannot be adjusted.

(3) The accuracy of charging control for a battery pack higher than 10 cells is slightly poor, and the control ability is insufficient. Most of the A / D conversion microcontrollers are used to implement -Δν control. The control accuracy refers to the percentage of the battery pack voltage, and the control accuracy of 0.25% refers to 0.25% of the total battery pack voltage. Therefore, when there are many battery cells, the The absolute control accuracy is worsened, and sometimes the desired control accuracy cannot be achieved.

(4) The minimum charging rate is not small enough, generally 0.2C to 0.25C, it is difficult to apply to the occasions requiring extra long time charging. Some applications, such as charging large-capacity battery packs, usually require a lower current and longer time to charge, which is beneficial to reducing the overall cost of the product and extending the battery life. The smaller the charging current, the lower the requirements for the device, and the higher the cost required. small.

There is another battery charging circuit, as shown in FIG. 2, which includes voltage peak sampling and input voltage comparison control. Control circuit and controlled charging circuit 2 ", in which the voltage peak sample and input voltage comparison control circuit Γ includes a battery voltage divider sampling circuit 11", a peak sample-and-hold circuit 12 ", and-Δν comparison control circuit 13". As shown in Figure 3, the battery voltage divider sampling circuit 11 "is composed of resistors R1, R2 and battery BT; the peak sample and hold circuit 12" is composed of integrated operational amplifier U1B, diodes D1, D2 and capacitor C1;-Δ ν The comparison control circuit 13 "uses an integrated operational amplifier U1C.

The battery charging circuit has the following disadvantages:

1) The bias current of the 10-pin input terminal of the op amp U1C (direction flows out of the op amp input terminal) The charging effect of the capacitor C1, the LM324 input bias current is about 45nA. If an op amp with a very low input bias current is used, its input The bias current can reach 50pA and its input impedance is 10 ¹² Ω. If a discrete circuit is used, the cost will increase, but if it is used in an integrated circuit chip, it will not cause too much cost increase.

2) The reverse leakage current of diode D2 is relatively small as 25ηΑ, and its value is related to the ambient temperature. The higher the temperature, the greater the leakage current.

3) The leakage of capacitor C1. The leakage of a capacitor is mainly related to the voltage on it. The higher the voltage, the larger the leakage, so as the battery voltage increases, the leakage current also increases. If a battery pack consisting of 6 Ni-MH batteries is directly input without resistance voltage division, the maximum voltage on C1 is 9 volts. The leakage problem of the capacitor is serious. The leakage current per unit capacitance cannot be ignored, and the price cannot be adopted. Low-cost large-capacity electrolytic capacitors. If C1 uses a small-capacitance capacitor such as 220η, the bias current of the U1 10-pin and the reverse leakage current of D2 have a greater impact on C1. If it is input after being divided by a resistor, if the 1/3 divided voltage is 3 volts, the leakage current will be significantly reduced, but the voltage sampling accuracy and C1 voltage change rate will be reduced to 1/3 of the original. This method has certain safety hazards. If the capacitor fails or its leakage current becomes large, and the battery voltage drops slowly, the voltage of capacitor C1 will follow the decline when the battery voltage drops, so the charging cannot be completed and the battery will be charged. burst. The leakage current of the capacitor C1 is also related to the voltage on it and the ambient temperature.

4) Unable to achieve true-AV control. The reason is that if it can be achieved, when a voltage drop is detected, if the 2mv drop causes the U1B 7 pin to be low, the reverse voltage will always be applied to D2 until the voltage continues to drop to the set -AV value. Due to the leakage current of D2, during this time, the voltage on capacitor C1 may drop with the battery voltage, so the charging cannot be terminated or the value of-Δ ν cannot be determined, causing the battery to be charged and damaged. Therefore, it is not appropriate to use a voltage drop of Δ ν Charging ends at the time of charging, but can only be used when the battery voltage starts to drop. Therefore, this circuit essentially uses a zero-voltage slope system with extremely high sensitivity, but poor anti-interference ability. Lack of adaptability to battery voltage fluctuations caused by temperature changes, etc. Power, it is easy to terminate charging early due to external interference, resulting in insufficient battery charging. True-One of the benefits of AV control is that its anti-interference threshold is Δ ν. Interference less than Δ ν will not cause malfunction, and will not cause insufficient charging of the battery. Charging ensures that the battery is fully charged and has no adverse effects on the battery.

In summary, it is difficult to implement the _ Δ ν charger with this charging circuit. If it is implemented, its cost is also high, and there are also safety issues.

Summary of the Invention

The purpose of the present invention is to provide a new dynamic-AV charging control method and a battery charging circuit designed according to the method. By using this method and circuit, the AV detection accuracy of more than 8 battery packs can be improved. Lower charging rate and reduce the product cost of Ni-MH-Ni-Cd battery charger with Δ ν detection method, and realize safe and reliable charging. After the design is made into an integrated circuit, the product cost of the Δ ν charge control chip can be greatly reduced.

The invention provides a dynamic voltage negative incremental battery charging control method, which includes the following steps: fixedly or dynamically setting a range of negative voltage increase from high to low, and fixedly setting or dynamically setting a sample and hold point The minimum voltage rising speed of the battery; when the voltage rising rate of the rechargeable battery is higher than the set minimum rising rate of the sample-and-hold point, the voltage of the sample-and-hold point moves to the low point in the negative voltage range and finally reaches the low point. When the voltage at the sample hold point stops falling relative to the low point, the battery continues to charge; when the voltage rise rate of the rechargeable battery is lower than the set minimum rate of the sample hold point, the voltage at the sample hold point increases toward the negative voltage increase range Point movement, when the high point is reached, charging ends; during the voltage rise of the sample and hold point, if the voltage of the rechargeable battery drops, the high end of the negative voltage increase region moves down; If the point voltages are met, charging ends.

The battery charging circuit provided by the present invention includes a voltage peak sample-hold and input voltage comparison control circuit, which is characterized in that the voltage peak sample-hold and input voltage comparison control circuit includes a battery voltage division voltage sampling circuit, a peak sample-hold circuit, and a voltage. Negative incremental comparison control circuit, peak sampling diode D1 reverse leakage current suppression circuit, stable voltage as peak sample holding capacitor positive terminal reference voltage circuit and sample and hold point minimum rising voltage speed setting circuit; of which: peak sample and hold circuits are respectively It is connected to the battery voltage divider sampling circuit, D1 reverse leakage current suppression circuit, stable voltage as peak sampling and holding capacitor positive terminal reference voltage circuit, sampling and holding point minimum rising voltage speed setting circuit and voltage negative incremental comparison control circuit; Negative The incremental comparison control circuit is also connected to the battery voltage divider sampling circuit.

The above battery charging circuit further includes a bias current suppression circuit at the input end of the op amp, and the bias current suppression circuit at the input end of the op amp is connected between the peak sample-and-hold circuit and the voltage negative incremental comparison control circuit.

The above battery charging circuit further includes a controlled charging circuit and an overvoltage protection circuit, and both are connected to a negative voltage increase comparison control circuit.

By adopting the above technical solution, that is, the dynamic voltage negative incremental battery charging control method of the present invention, by adjusting the minimum voltage rise rate of the sample-and-hold capacitor to an optimal value, the accuracy of-Δ ν can be improved, and the duration of zero Δ ν can be reduced. Anti-interference ability. In order to implement this method, the influence of other factors such as leakage current on the minimum voltage rise rate of the sample-and-hold capacitor must be minimized. Therefore, the battery charging circuit of the present invention controls the influence of the sample capacitor from three aspects: ① the bias current suppression circuit at the input end of the op amp is used To suppress the bias current at the input of the op amp, an op amp with an input bias current of approximately zero is formed. ② Adopt D1 reverse leakage current suppression circuit. When the sampling diode (D1) is reverse biased, a voltage of about thirty millivolts higher than the sampling point (V5) is applied to its negative terminal. This voltage passes through a pair of ends. The dynamic resistance formed by the connected diodes (D2, D4) reaches the negative terminal of the sampling capacitor (C3). When it is at the critical point of charging termination, this voltage becomes several millivolts. The dynamic resistance of the diode at this voltage is Dozens of megabytes, so the current flowing through this pair of diodes is very small and has no effect on the sample capacitor. ③ Reduce the voltage on the sample-and-hold capacitor, select a stable voltage as the reference voltage of the positive terminal of the peak sample-and-hold capacitor, and connect its negative terminal to the sample-and-hold point. Therefore, the present invention can use an integrated operational amplifier (LM324) to implement-A V detection, the quad op amp LM324 is inexpensive, and reduces the product cost of the-Δ ν detection nickel-metal-hydride-nickel-cadmium battery charger to achieve safe and reliable charging. Overview of the drawings

FIG. 1 is a block diagram of a circuit structure of a conventional battery charging circuit;

2 is a block diagram of another circuit structure of a conventional battery charging circuit;

3 is a schematic diagram of the circuit structure shown in FIG. 2;

4 is a block diagram of a circuit structure of the present invention;

FIG. 5 is a schematic circuit diagram of the present invention; a preferred embodiment of the present invention

A new dynamic-ΔV charging control method provided by the present invention is: setting a fixed-ΔV voltage negative The increment range is V4-V5. Set the minimum voltage rise rate of the sample-and-hold point. When the voltage rise rate of the rechargeable battery is higher than the minimum rise-rate of the sample-and-hold point, the voltage of the sample-and-hold point goes to the-voltage range area. The low point V5 moves and finally reaches the low point V5. At this time, the voltage of the sample and hold point stops falling relative to V5, and the battery continues to charge. When the rising rate of the charging voltage is lower than the set minimum rising rate of the sample and hold point, the voltage of the sample holding point moves to the high point V4 of the voltage range of-Δν, and when the high point V4 is reached, the charging ends. During the voltage increase of the sample and hold point, if the voltage of the rechargeable battery drops, the high-end V4 of the SP-Δν region moves downward. When the high-end voltage V4 of the -Δν region meets the sample-and-hold voltage V6, the charging process ends.

As shown in FIG. 4, the battery charging circuit of the present invention includes a voltage peak sample-hold and input voltage comparison control circuit 1, an overvoltage protection circuit 3, and a controlled charging circuit 2, wherein: the voltage peak sample-hold and input voltage comparison control circuit 1 includes Battery voltage divider sampling circuit 11, peak sample and hold circuit 12,-AV comparison control circuit 13, D1 reverse leakage current suppression circuit 14, stable voltage for peak sample and hold capacitor positive terminal reference voltage circuit 15, minimum rising voltage of sample and hold point The speed setting circuit 17 and the bias current suppression circuit 16 at the input end of the operational amplifier are composed.

In the embodiment shown in FIG. 5, the integrated operational amplifiers are all of the type LM324, and the power supply voltage VCC is 12 volts.

The battery voltage dividing sampling circuit 11 is composed of a battery BT, resistors R17, R19, R4, R18, R5, R20, R7, diodes D3, D6, and capacitors C4, C5. Its input is the battery voltage VI to be charged, and its output is various control voltage samples formed by the battery voltage via a voltage divider network. Function: ① The highest sample voltage V2 that can be reached at the negative terminal of C3. This voltage ensures that the battery can be terminated under various adverse conditions through R2 / 20M. At the same time, it provides the minimum sample voltage rise rate setting through R2; Voltage V3 for suppressing reverse leakage current of D1; ③ Voltage V4 for comparison with the peak sample-and-hold voltage; ④ The set voltage for peak sampling V5, the voltage difference between V4 and V5 is set-AV ⑤ A constant voltage V8 lower than V2 by a certain value, here is about 640mv, D3 can also be replaced by other circuits that generate a stable voltage. The main purpose is to obtain a stable voltage so that the voltage at each divided sampling point and the input voltage V2 has the same amount of voltage change, while reducing the voltage range of each sampling point.

The peak sample-and-hold circuit 12 is composed of an integrated operational amplifier U2A, diodes D1, D2, D4, a resistor R1, and a capacitor C3. Its input is the battery voltage divided voltage sampling V5 signal. When V5 rises, the op amp U2A sets the voltage of the negative terminal of the sampling capacitor C3 (that is, V6 point) to V5 through Dl, D2, and R1. When V5 drops, U2A 1 Pin output goes low, D1 cuts in the reverse direction, and sampling capacitor C3 will The V6 voltage is kept at a maximum value, thereby realizing the peak sampling of the sampling voltage V5.

-△ V comparison control 13 adopts integrated operational amplifier U2B. Its inputs are: 1. The voltage at the battery voltage divided sampling point V4; 2. The peak sample-and-hold voltage V6 is output after the bias current suppression circuit at the input end of the op amp, and its value is equal to V6. During the charging process, when the battery voltage reaches the maximum value, because V4 is always higher than the voltage on V5, the voltage on R5 is V4-V5 = 25mv, and V5 = V6, so V4-V6 = 25mv, so U2B 6-pin ratio The voltage of pin 5 is 25mv high. When the battery voltage drops, the voltage of pin 5 of U2B is basically unchanged due to the function of the sample-and-hold capacitor C3. The pin 6 drops with the drop of the battery voltage. When it drops below the voltage of pin 5, U2B 7 The pin output goes high and terminates the battery charging process. By adjusting the resistance of R5, the magnitude of-Δ ν can be changed.

D1 reverse leakage current suppression circuit 14 is composed of an integrated operational amplifier U2D and a resistor R3. Its input is the voltage at point V3. The voltage at point V3 is a voltage 8mv higher than the voltage at point V4. The output is at point V7. U2D functions as a voltage follower with an amplification factor of 1. Therefore, when D1 is reverse biased, V3 = V7. At this time, the variation range of V7-V6 is within 8mv + 25mv = 33mv. In this way, the leakage current through D2, Rl, and D4 is very small. Assuming that the resistance between V7 and V6 is 10M, the maximum leakage current is 33mv / 10M = 3.3nA, when the voltage of V7 to V6 is 8mv, that is, at the charge cut-off point (because V4 = V6, that is, U2B 6 pin = 5 pin voltage), the leakage current is 8mv / 10M = 0.8nA, and At this time, the reverse leakage current on D1 is generally 25nA, and the sample-and-hold capacitor C3 is no longer affected by the leakage current of D1. D1 reverse leakage current suppression circuit 14 also has the function of pulling down the negative terminal of capacitor C3 through diode D4 after removing the battery after charging. It is used to start the next charging process when the battery is inserted.

The positive voltage reference circuit 15 for the stable voltage as the peak sampling and holding capacitor is composed of a 78L09 integrated chip Ul, capacitors C7, C6, C2, resistors R23, R22. Obtaining a stable voltage and supplying it to the positive terminal of the sample-and-hold capacitor C3 is very important for charging control. A three-terminal voltage regulator circuit is used to obtain a stable voltage output, and any other reference voltage circuit can also be used. Capacitor C3 is positively terminated with a stable reference voltage, and its negative end is connected to the sample-and-hold point voltage structure. Compared with the structure in Figure 3, the negative end of the sample-and-hold capacitor is grounded and the positive-terminated sample-and-hold point voltage has the following advantages: ① During battery charging, the higher the battery voltage, the lower the voltage applied across the sample-and-hold capacitor, and the lower the leakage current. The maximum voltage applied to the sample-and-hold capacitor is actually the initial voltage after the battery starts charging and the end of charging. The amount of voltage change at this time is smaller than the battery voltage, so it reduces leakage current greatly compared to the connection method in the prior art (shown in Figure 3), and because the voltage across the capacitor is low, Low-cost, large-capacity electrolytic capacitors can be used. In this way, the leakage depends mainly on the leakage of the capacitor itself (at low voltages, the leakage of the capacitor can meet the charging requirements here). At the same time, the leakage of other aspects of the circuit to the capacitor is due to the large capacitance. The impact is further reduced. ② The leakage of the capacitor increases, fails, and damages will cause the voltage at the sample and hold point to rise, thus ending the charging without causing damage to the battery, so it is safe. If a reference voltage is provided to the negative terminal of the electrolytic capacitor, and the positive terminal is the sample-and-hold point, the leakage current can also be reduced, but the increased leakage of the capacitor will cause safety problems. Non-polarized capacitors can also be used.

The bias current suppression circuit 16 at the input end of the op amp is composed of an integrated operational amplifier U2C, resistors R8, R13, and capacitor C6. The input of this circuit is the voltage taken from the sample-and-hold point (that is, the negative terminal of C3), and the output is-Δ ν. The control circuit (pin 5 of U2B) is mainly used to suppress the influence of the bias current at the input end of the op amp on the sample-and-hold capacitor C3. Resistor R13 is used to detect the bias current of the input terminals of pins 9 and 5 of U2C. At the same time, this current is converted into a voltage. Due to the function of pin 8 of U2C, this voltage is added to R8, and the current formed by U2 offsets 10 and 2 of U2. The input of the pin is biased, so the effect on the sample-and-hold capacitor C3 is minimal. If there is no complete offset, if the result of the offset is a small amount of current (such as about 2ηΑ) to charge C3, it will be offset by the current on R2 (about 5ηΑ). After the offset, it will become 3ηΑ to discharge the capacitor. If the result of the offset is that a small amount of current (such as about 2ηΑ) is discharged to the C3 capacitor, plus the current on R2, a total of 7ηΑ is discharged to the capacitor. In contrast to the 45ηΑ input bias current at the input of the op amp, Great restraint. In addition, because the final result is the discharge of the capacitor, it will only speed up the end of the charge, and will not cause the situation where the charge cannot be terminated. C6 is an anti-shock capacitor. Here R2 plays the role of ensuring that the circuit can terminate charging under unfavorable conditions and set the minimum sampling point voltage rising rate according to the situation. By increasing the sampling capacitor capacity and increasing the R2 current, the setting accuracy of the minimum sampling point voltage rising speed can be improved. . For the suppression of the bias current of the op amp input terminal of the sampling capacitor C3, other circuits can also be used, such as the current itself is very small, it may not be suppressed.

The controlled charging circuit 2 is composed of a transistor Ql, a light emitting diode D7, a diode D8, resistors R14, R15, and R16. Its input is a charging control signal, and the battery is charged through the D8 output.

The overvoltage protection circuit 3 is composed of voltage regulator D5, resistors R21, R24, and transistor Q2. The input is the voltage of the battery to be charged, and the output goes to pin 6 of U2B. It is used to stop charging when the battery voltage exceeds the specified value.

The sample and hold point minimum rising voltage speed setting circuit (17) is composed of R2, which cooperates with the sample and hold capacitor C3 to set the minimum rising rate of the sample and hold point, and C3 can take different values as required. The end of R2 connected to the V2 point can also be disconnected, and another control point related to the battery charging voltage is used to achieve The corresponding minimum voltage rising speed of the sample and hold point is used in different charging stages of the battery, and other methods can also be used to adjust the minimum voltage rising speed of the sample and hold point according to different charging stages of the battery.

The dynamic voltage negative incremental battery charging control method of the present invention has the following advantages:

1) During normal charging, the battery voltage rise rate is higher than the minimum rise rate of the sample-and-hold point. The sample-and-hold point is fixed at a set point-Δν region is low, such as V5. At this time, it has a higher noise margin and anti-interference ability. Strong.

2) The actual value of -Δν when the battery is stopped is the voltage drop of the battery voltage when V4 and V6 are equal, which is less than the set value of -Δν, so the detection accuracy is improved. By setting the minimum rising rate of different sample and hold points in different battery charging stages, such as using a faster sample and hold point voltage rising speed in the battery voltage region at the end of charging, the duration of zero AV can be saved. Unlike the monitoring voltage change used by some smart chips, if it does not rise, wait for a certain value of _Δν to fall. If it does not wait, it will delay a specific time to stop charging or wait until it reaches, so it is also a certain -Δν value. This new method improves the detection accuracy.

3) The method of the present invention is applicable to charging at a low charging rate, such as 0.13C, because it can conveniently set the minimum sampling voltage rising rate, and can determine the charging voltage rising rate and the set minimum sampling voltage rising rate It is determined dynamically to increase the final -Δν value or decrease the final -AV value. For example: The detection above or below the set lmv / 250 second rise rate does not need to wait for 250 seconds to detect, it can be obtained and responded in real time. At present, smart chips cannot adapt well to low-rate charging.

4) Both fast charging and slow charging can be considered. When fast charging, because the battery voltage rises and falls quickly, the rising voltage of the sample and hold point can be ignored at this time. At this time, the value of -Δν is the circuit setting value, which is the same as that of the smart chip.

Claims

Rights request

1. A dynamic voltage negative incremental battery charging control method, comprising the following steps-fixedly or dynamically setting a voltage negative incremental range (V4 ~ V5), and fixedly setting or dynamically setting a minimum voltage of a sample and hold point Rising speed

When the rising rate of the voltage of the rechargeable battery is higher than the set minimum rising rate of the sample and hold point, the voltage of the sample and hold point moves to the low point (V5) of the negative voltage increase range area, and finally reaches the low point (V5). The voltage at the holding point stops falling relative to the low point (V5), and the battery continues to charge;

When the voltage rise rate of the rechargeable battery is lower than the set minimum increase rate of the sample-and-hold point, the voltage of the sample-and-hold point moves to the high point (V4) of the negative voltage increase range. When it reaches the high point (V4), it ends. Charge

During the voltage increase of the sample and hold point, if the voltage of the rechargeable battery drops, the high end (V4) of the negative voltage increase region moves down. When the high voltage (V4) of the negative voltage increase region meets the sample and hold point voltage (V6), , The charging ends.

2. A battery charging circuit, comprising a voltage peak sample-hold and input voltage comparison control circuit (1), characterized in that:

The voltage peak sample-and-hold and input voltage comparison control circuit (1) includes a battery voltage division voltage sampling circuit (11), a peak sample-and-hold circuit (12), a voltage negative incremental comparison control circuit (13), and a peak-sampling diode (D1). Reverse leakage current suppression circuit (14), stable voltage as peak sample and hold capacitor positive terminal reference voltage circuit (15) and sample and hold point minimum rising voltage speed setting circuit (17); of which:

The peak sample-and-hold circuit (12) is respectively connected to the battery voltage divider sampling circuit (11), the D1 reverse leakage current suppression circuit (14), the stable voltage is used as the peak sample-and-hold capacitor positive terminal reference voltage circuit (15), and the sample-and-hold point is the smallest. The rising voltage speed setting circuit (17) is connected to the voltage negative incremental comparison control circuit (13); the voltage negative incremental comparison control circuit (13) is also connected to the battery voltage partial voltage sampling circuit (11).

3. A battery charging circuit according to claim 2, further comprising a bias current suppression circuit (16) at the input terminal of the operational amplifier, the bias current suppression circuit (16) at the input terminal of the operational amplifier is connected to Between the peak sample-and-hold circuit (12) and the voltage negative incremental comparison control circuit (13).

4. A battery charging circuit according to claim 2 or 3, characterized in that: the circuit It also includes a controlled charging circuit (2) and an overvoltage protection circuit (3), both of which are connected to the voltage negative incremental comparison control circuit (13).