CN115065117A - Active and passive combined super capacitor equalization system and method - Google Patents
Active and passive combined super capacitor equalization system and method Download PDFInfo
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- CN115065117A CN115065117A CN202210747891.1A CN202210747891A CN115065117A CN 115065117 A CN115065117 A CN 115065117A CN 202210747891 A CN202210747891 A CN 202210747891A CN 115065117 A CN115065117 A CN 115065117A
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- H02J7/54—
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
- H02J7/342—The other DC source being a battery actively interacting with the first one, i.e. battery to battery charging
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- H02J7/56—
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- H02J7/80—
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- H02J7/82—
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/60—Other road transportation technologies with climate change mitigation effect
- Y02T10/70—Energy storage systems for electromobility, e.g. batteries
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Abstract
本发明提供了一种主被动结合的超级电容均衡系统及方法，所述系统包括超级电容模组、采集模块、均衡模块以及电池管理芯片，所述采集模块用于采集超级电容模组中每个超级电容单体的电压、电流和温度参数，所述电池管理芯片根据采集的超级电容单体的电压、电流和温度参数估算每个超级电容单体的剩余电量，在充放电过程中，当超级电容模组中剩余电量最高的超级电容单体与剩余电量最低的超级电容单体的剩余电量差值超过第一均衡阈值时，所述均衡模块采用主动均衡电路，即将模组内剩余电量最高的超级电容单体的电量传递给最低的超级电容单体，当剩余电量差值小于第一均衡阈值但大于第二均衡阈值时，所述均衡模块采用被动均衡电路。
The present invention provides an active-passive combined supercapacitor equalization system and method. The system includes a supercapacitor module, an acquisition module, an equalization module and a battery management chip. The acquisition module is used to acquire each of the supercapacitor modules. The voltage, current and temperature parameters of the supercapacitor cells, the battery management chip estimates the remaining power of each supercapacitor cell according to the collected voltage, current and temperature parameters of the supercapacitor cells. When the difference between the remaining power of the supercapacitor cell with the highest remaining power and the supercapacitor cell with the lowest remaining power in the capacitor module exceeds the first balance threshold, the balance module adopts an active balance circuit, that is, the cell with the highest remaining power in the module. The power of the supercapacitor cell is transferred to the lowest supercapacitor cell, and when the remaining power difference is less than the first equalization threshold but greater than the second equalization threshold, the equalization module adopts a passive equalization circuit.
Description
Technical Field
The invention relates to the technical field of super capacitor equalization, in particular to an active and passive combined super capacitor equalization system and method.
Background
With the topic of energy crisis gradually stepping into the field of the public, people have stronger desire to find clean energy, and the super capacitor is gradually applied to various industries as an efficient clean energy storage element by virtue of the aspects of large capacity, long cycle life, high charging speed, high charging and discharging efficiency, wide working temperature range, high power density, convenient energy detection, environmental friendliness and the like, wherein the research of the super capacitor as a battery applied to the automobile industry gradually becomes a hot topic, the design of a balancing circuit of the super capacitor becomes a key technical link of battery life and safety, the voltage, the capacity, the internal resistance and the like of the single unit of the super capacitor inevitably exist in the manufacturing and using processes, the process is a continuously accumulated process, the difference generated among the single units of the super capacitor is larger when the time is longer, and the single unit of the super capacitor can be influenced by the use environment, the inconsistency of the unit cells is gradually amplified during the use process, thereby causing the accelerated degradation of the performance of some unit cells.
In the prior art, the design of a super capacitor equalization circuit mainly stays on a single equalization scheme, and mainly includes two schemes of active equalization and passive equalization, wherein the passive equalization is divided into a resistance method and a voltage regulator tube method, and the active equalization mainly includes three major types of inductance method, capacitance method and transformer method. When a passive equalization design circuit is adopted, a resistance equalization method is adopted, namely, the single battery electric quantity with higher voltage is consumed through the heating of equalization resistors to achieve a voltage equalization state, however, the adjacent single batteries cannot be simultaneously balanced, namely, the maximum path number of balanced opening is half of the total path number, so that the mutual interference of equalization currents and the heat generated by the discharge of an equalization circuit are prevented from being too concentrated, and when the voltage difference of a capacitor is larger, the quick response cannot be achieved, and the energy consumption is larger.
If an active equalization circuit is adopted, when the capacitance differential pressure is small, the equalization speed is slow, in order to meet the requirement of high-precision equalization under low tolerance, high requirements are put on the equalization circuit, the circuit design is complex, and high cost can be generated. Therefore, the design of the equalizing circuit with a single scheme cannot achieve rapid equalization for complicated and variable charging and discharging requirements.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide an active and passive combined super capacitor equalization system and method which combine active equalization and passive equalization so as to effectively reduce energy loss and increase the charge-discharge efficiency of a super capacitor.
In order to solve the problems, the technical scheme of the invention is as follows:
an active and passive combined super capacitor balancing system comprises a super capacitor module, an acquisition module, a balancing module and a battery management chip, wherein the acquisition module is used for acquiring voltage, current and temperature parameters of each super capacitor monomer in the super capacitor module, the battery management chip estimates the residual electric quantity of each super capacitor monomer according to the acquired voltage, current and temperature parameters of the super capacitor monomers, when the residual electric quantity difference value of the super capacitor monomer with the highest residual electric quantity and the super capacitor monomer with the lowest residual electric quantity in the super capacitor module exceeds a first balancing threshold value in the charging and discharging process, the balancing module adopts an active balancing circuit, namely, the electric quantity of the super capacitor monomer with the highest residual electric quantity in the module is transmitted to the lowest super capacitor monomer, and when the residual electric quantity difference value is smaller than the first balancing threshold value but larger than a second balancing threshold value, the balancing module adopts a passive balancing circuit, namely the electric quantity of the super capacitor monomer with more residual electric quantity is discharged through the passive balancing circuit.
Optionally, the first equalization threshold is set to 5% and the second equalization threshold is set to 1%.
Optionally, the active equalization circuit includes a first MOS transistor, a second MOS transistor, a first resistor, and a flying capacitor, the power management chip controls the first MOS transistor and the second MOS transistor to be turned on, the electric quantity of the super capacitor monomer with the highest residual electric quantity charges the flying capacitor along the first MOS transistor, the first resistor, and the flying capacitor, and a charging loop is formed through the second MOS transistor.
Optionally, when it is detected that the electric quantity of the super capacitor single body with the highest residual electric quantity is reduced to be close to a normal value, the power management chip controls the first MOS transistor and the second MOS transistor to be closed, and the charging loop is disconnected.
Optionally, the power management chip controls the fourth MOS transistor and the fifth MOS transistor to be turned on, the flying capacitor fully charged by the super capacitor monomer with the highest residual capacity starts to charge the super capacitor monomer with the lowest residual capacity, and when it is detected that the electric quantity of the super capacitor monomer with the lowest residual capacity is restored to a normal value, the power management chip controls the fourth MOS transistor and the fifth MOS transistor to be turned off, and the charging circuit of the super capacitor monomer with the lower electric quantity is turned off.
Optionally, the passive equalization circuit includes a third MOS transistor, a fuse, a second resistor, and a third resistor, the power management chip controls the third MOS transistor to be turned on, and the electric quantity of the single super capacitor performs passive equalization discharge along a loop of the fuse, the third MOS transistor, the second resistor, the third resistor, and the single super capacitor.
Optionally, the second resistor and the third resistor are two load resistors connected in parallel, so that the electric energy flowing through the resistors can be converted into heat energy with high efficiency and lost, thereby playing a role in discharging the electric energy.
Optionally, the system further includes a current loop for indicating which supercapacitor cell is currently in passive equilibrium discharge, where the current loop includes a fuse, a third MOS, a diode, a fourth resistor, and the supercapacitor cell, where the fourth resistor is a current-limiting resistor, and the fuse is used to prevent the circuit from being damaged due to excessive current when the supercapacitor discharges.
Further, the invention also provides an active and passive combined super capacitor equalization method, which comprises the following steps:
accurately estimating the residual electric quantity of each super capacitor monomer of the super capacitor module, and setting a first equalization threshold value and a second equalization threshold value;
in the charging and discharging process, if the difference value of the residual electric quantity of the super capacitor monomer with the highest residual electric quantity and the super capacitor monomer with the lowest residual electric quantity in the super capacitor module exceeds a first balance threshold value, an active balance mode is adopted, namely the electric quantity of the super capacitor monomer with the highest residual electric quantity in the module is transmitted to the super capacitor monomer with the lowest residual electric quantity;
when the residual electric quantity difference value of the super capacitor monomer with the highest residual electric quantity and the super capacitor monomer with the lowest residual electric quantity in the super capacitor module is smaller than a first balance threshold value but larger than a second balance threshold value, a passive balance mode is adopted, namely, the electric quantity of the super capacitor monomer with more residual electric quantity is discharged through a passive balance circuit.
Optionally, the first equalization threshold is set to 5%, and the second equalization threshold is set to 1%.
Compared with the prior art, the invention has the following advantages:
1. through the design of the super capacitor equalization circuit with active and passive combination, the super capacitor battery management system can dynamically select an equalization mode according to an equalization threshold value during equalization, and combine active equalization and passive equalization, so that energy loss is effectively reduced, and the equalization precision of the whole energy storage system is further optimized;
2. by setting different tolerance thresholds, the rapid response of the super capacitor equalization under various conditions can be realized, the problem of large energy loss caused by single passive equalization is solved, the charging and discharging efficiency of the super capacitor can be increased, the charging and discharging time is shortened, and the use efficiency of the super capacitor is improved;
3. in the design of the active equalization circuit, two transistors and a flying capacitor are matched in a single storage unit, so that the capacity interconversion between any two storage units in a group of super capacitor modules can be realized, and the equalization response speed in the super capacitor battery management system is improved.
4. The passive equalizer circuit is in the design, considers super capacitor's quick charge-discharge's characteristic, and in passive equalizer circuit, the load resistance return circuit adopts parallel connection's mode in the design, can increase the overcurrent ability for the corresponding speed of passive circuit, also increased safety design in passive circuit simultaneously, can fuse the circuit when the electric current is too big, can prevent that the electric current is too big to lead to the heat too big, influences the security of super capacitor during operation.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of a super capacitor equalization system framework connection according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an active and passive combined super capacitor balancing module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a MOS control circuit according to an embodiment of the invention;
fig. 4 is a flowchart of an active-passive combined super capacitor equalization method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Fig. 1 is a schematic connection diagram of a frame of an active-passive combined super capacitor balancing system according to an embodiment of the present invention, and as shown in fig. 1, the super capacitor balancing system includes a super capacitor module 1, an acquisition module 2, a balancing module 3, and a battery management chip 4.
The acquisition module 2 comprises a voltage acquisition module, a current acquisition module and a temperature acquisition module, when the system works, a front-end acquisition chip firstly acquires the voltage and the current of each super capacitor monomer in the super capacitor module 1 and is used for estimating the SOC capacity of the super capacitor monomers, because the capacity of the super capacitor is also related to the temperature and slightly different capacities under different temperature environments, the temperature acquisition module is added during front-end acquisition, acquired current, voltage, temperature and other key parameter signals are transmitted to the battery management chip 4 through an ISO-SPI twisted pair for capacity estimation, the calculated capacity is compared with an active and passive equalization threshold value, and when the SOC difference value delta SOC of the highest monomer in the super capacitor module and the lowest monomer in the SOC exceeds a first equalization threshold value in the charging process, the equalization module 3 adopts an active equalization circuit, that is, the supercapacitor with the highest residual electric quantity in the module is transferred to the lowest supercapacitor, and when the Δ SOC is smaller than the first balancing threshold but larger than the second balancing threshold, the balancing module 3 adopts a passive balancing circuit. In this embodiment, the first equalization threshold is set to 5% and the second equalization threshold is set to 1%.
Specifically, as shown in fig. 2, taking the super capacitor B1 in fig. 2 as an example, assuming that the current super capacitor has the highest capacity of B1, the current super capacitor has the lowest capacity of B4, and the capacity difference is greater than 5%, at this time, the active equalization mode is started first, the power management chip 4 controls the PIN1 and the PIN2, outputs a high level, the first MOS transistor Q7 and the second MOS transistor Q9 are turned on, the electric quantity of the super capacitor B1 charges the flying capacitor C13 along the first MOS transistor Q7, the first resistor R37, and the flying capacitor C13, and a charging loop is formed through the second MOS transistor Q9. When the fact that the electric quantity of the B1 is reduced to be close to a normal value is detected, the power management chip 4 controls the PIN1 and the PIN2 to output a low level, the first MOS tube Q7 and the second MOS tube Q9 are closed, the charging loop is disconnected, the 1% difference value of the super capacitor monomer B1 is passively balanced, the power management chip 4 controls the PIN13 to output a high level, the third MOS tube Q1 is opened, the electric quantity of the super capacitor monomer B1 is in a passive balanced discharging mode along the loop of the fuse F6, the third MOS tube Q1, the second resistor R19, the third resistor R25 and the super capacitor B1, wherein the second resistor R19 and the third resistor R25 are two load resistors connected in parallel, the electric energy flowing through the resistors can be converted into heat energy to be lost at a high efficiency, and the effect of discharging quantity is achieved. In the embodiment, a mode of connecting two resistors in parallel is adopted, so that two functions are achieved, firstly, due to the basic characteristic of the super capacitor, the super capacitor has a high charging and discharging speed, large current can be generated in a short time, and the overcurrent capacity of the load resistor can be increased in a parallel connection mode; secondly, because adopt two load resistance to carry out the mode of bleeding, can be more quick convert the electric energy into heat energy and consume to remedy the unhappy shortcoming of traditional passive balanced speed. And finally, the power management chip 4 controls PINs PIN7 and PIN8 to output high level, the fourth MOS tube Q14 and the fifth MOS tube Q15 are opened, the flying capacitor C13 fully charged by the super capacitor cell B1 starts to charge the super capacitor cell B4 with the lowest electric quantity, when the electric quantity of the super capacitor cell B4 is detected to be recovered to a normal value, the power management chip 4 controls PINs PIN7 and PIN8 to output low level, the fourth MOS tube Q14 and the fifth MOS tube Q15 are disconnected, the charging circuit of the super capacitor cell B4 is disconnected, and the balancing mode of the complete active and passive combined super capacitor is completed at this time.
In this embodiment, when the super capacitor B1 of the battery storage cell starts passive equalization, the cell B1 further has a current loop along with the fuse F6, the third MOS transistor Q1, the diode D1, the fourth resistor R31, and the super capacitor B1, where the current loop is used to indicate which storage cell is currently used when performing passive equalization discharge, where the fourth resistor R31 is a current-limiting resistor, and the F6 in the circuit is a fuse to prevent the super capacitor from being damaged due to excessive current when discharging; T1-T5 in the equalizing circuit are test points for arranging super capacitor monomers, and various test circuits can be connected through the test points to monitor various performance parameters of the super capacitor monomers in real time under the working state.
Fig. 3 is a schematic diagram of an MOS control circuit according to an embodiment of the present invention, as shown in fig. 3, the chip pin controls the on/off of the equalizing circuit and the discharging loop of the capacitance and the electric quantity during equalization by controlling the on/off of the MOS transistor, wherein R001 is a current-limiting resistor, which is connected in series in the chip pin control circuit, because the grid terminal of the MOS tube has a capacitor, a stray inductor, a wiring inductor and the like, when the grid of the MOS tube is driven, the capacitor inductors form an LC oscillation circuit, the amplitude of oscillation may exceed the grid safety voltage (about 20V), the resistor R001 can play a role of inhibiting oscillation, the larger the resistance value of the resistor R001 is, the more gradual the change of the grid driving voltage is, the longer the device conducting time is, the smaller the resistance value of the resistor R001 is, the shorter the conducting time is, however, the gate driving voltage varies dramatically, so the value is generally selected according to the specific circuit, and is generally about 0 to 20R. When the MOS tube is conducted, voltage between a drain electrode and a source electrode suddenly changes and is coupled to a grid electrode through an internal parasitic capacitor, so that quite high grid peak voltage is generated, the transient voltage can break down a very thin oxide layer on the grid electrode, charges are easily accumulated on the grid electrode of the MOS tube due to charge induction, a voltage relief resistor R002 and a voltage stabilizing diode D001 need to be connected, the voltage relief resistor R002 and the voltage stabilizing diode D001 respectively form a loop and are connected to the grid electrode of the MOS tube, and the voltage stabilizing diode D001 plays a role in limiting the voltage of the grid electrode and preventing the grid oxide layer from breaking down. The effect of pressure release resistor R002 not only can provide the return circuit of releasing for the electric charge of grid capacitance, can also be as pull-down resistance, guarantees that the chip is when no pin control signal, and grid potential is the low level, and MOS pipe Q001 is in the off-state. When the chip pin is at high level, the MOS tube is switched on, the equalizing circuit starts to execute, and when the chip pin signal is at low level, the MOS tube is switched off, and the equalizing circuit stops working.
Fig. 4 is a flowchart of an active and passive combined super capacitor equalization method according to an embodiment of the present invention, and as shown in fig. 4, the method includes the following steps:
s1: accurately estimating the residual electric quantity of each super capacitor monomer of the super capacitor module, and setting a first equalization threshold value and a second equalization threshold value;
s2: in the charging and discharging process, if the difference value of the residual electric quantity of the super capacitor monomer with the highest residual electric quantity and the super capacitor monomer with the lowest residual electric quantity in the super capacitor module exceeds a first balance threshold value, an active balance mode is adopted, namely the electric quantity of the super capacitor monomer with the highest residual electric quantity in the module is transmitted to the super capacitor monomer with the lowest residual electric quantity;
s3: when the residual electric quantity difference value of the super capacitor monomer with the highest residual electric quantity and the super capacitor monomer with the lowest residual electric quantity in the super capacitor module is smaller than a first balance threshold value but larger than a second balance threshold value, a passive balance mode is adopted, namely, the electric quantity of the super capacitor monomer with more residual electric quantity is discharged through a passive balance circuit.
In this embodiment, the first equalization threshold is set to 5%, and the second equalization threshold is set to 1%, so that the active equalization mode and the passive equalization mode are combined, and the energy loss of the system is effectively reduced.
Compared with the prior art, the invention has the following advantages:
1. through the design of the super capacitor equalization circuit with active and passive combination, the super capacitor battery management system can dynamically select an equalization mode according to an equalization threshold value during equalization, and combine active equalization and passive equalization, so that energy loss is effectively reduced, and the equalization precision of the whole energy storage system is further optimized;
2. by setting different tolerance thresholds, the rapid response of the super capacitor equalization under various conditions can be realized, the problem of large energy loss caused by single passive equalization is solved, the charging and discharging efficiency of the super capacitor can be increased, the charging and discharging time is shortened, and the use efficiency of the super capacitor is improved;
3. in the design of the active equalization circuit, two transistors and a flying capacitor are matched in a single storage unit, so that the capacity interconversion between any two storage units in a group of super capacitor modules can be realized, and the equalization response speed in the super capacitor battery management system is improved.
4. The passive equalizer circuit is in the design, considers super capacitor's quick charge-discharge's characteristic, and in passive equalizer circuit, the load resistance return circuit adopts parallel connection's mode in the design, can increase the overcurrent ability for the corresponding speed of passive circuit, also increased safety design in passive circuit simultaneously, can fuse the circuit when the electric current is too big, can prevent that the electric current is too big to lead to the heat too big, influences the security of super capacitor during operation.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. An active and passive combined super capacitor equalization system is characterized by comprising a super capacitor module, an acquisition module, an equalization module and a battery management chip, wherein the acquisition module is used for acquiring voltage, current and temperature parameters of each super capacitor monomer in the super capacitor module, the battery management chip estimates the residual electric quantity of each super capacitor monomer according to the acquired voltage, current and temperature parameters of the super capacitor monomers, when the residual electric quantity difference value of the super capacitor monomer with the highest residual electric quantity and the super capacitor monomer with the lowest residual electric quantity in the super capacitor module exceeds a first equalization threshold value in the charging and discharging process, the equalization module adopts an active equalization circuit, namely, the electric quantity of the super capacitor monomer with the highest residual electric quantity in the module is transmitted to the super capacitor monomer with the lowest residual electric quantity, and when the residual electric quantity difference value is smaller than the first equalization threshold value but larger than a second equalization threshold value, the balancing module adopts a passive balancing circuit, namely the electric quantity of the super capacitor monomer with more residual electric quantity is discharged through the passive balancing circuit.
2. The active-passive combined supercapacitor equalization system according to claim 1, wherein the first equalization threshold is set to 5% and the second equalization threshold is set to 1%.
3. The active-passive combined super capacitor equalization system according to claim 1, wherein the active equalization circuit comprises a first MOS transistor, a second MOS transistor, a first resistor and a flying capacitor, the power management chip controls the first MOS transistor and the second MOS transistor to be turned on, the electric quantity of the super capacitor monomer with the highest residual electric quantity charges the flying capacitor along the first MOS transistor, the first resistor and the flying capacitor, and a charging loop is formed by the second MOS transistor.
4. The active-passive combined super capacitor equalization system as claimed in claim 3, wherein when it is detected that the electric quantity of the super capacitor single body with the highest remaining electric quantity is reduced to be close to a normal value, the power management chip controls the first MOS transistor and the second MOS transistor to be closed, and the charging loop is disconnected.
5. The active-passive combined super capacitor equalization system as claimed in claim 4, wherein the power management chip controls the fourth MOS transistor and the fifth MOS transistor to be turned on, the full-charged flying capacitor with the super capacitor single body with the highest residual capacity starts to charge the super capacitor single body with the lowest residual capacity, when the situation that the electric quantity of the super capacitor single body with the lowest residual capacity is restored to a normal value is detected, the power management chip controls the fourth MOS transistor and the fifth MOS transistor to be turned off, and the charging circuit of the super capacitor single body with the lower electric quantity is turned off.
6. The active-passive combined super capacitor equalization system according to claim 1, wherein the passive equalization circuit comprises a third MOS transistor, a fuse, a second resistor and a third resistor, the power management chip controls the third MOS transistor to be turned on, and the electric quantity of the super capacitor monomer is passively equalized and discharged along a loop of the fuse, the third MOS transistor, the second resistor, the third resistor and the super capacitor monomer.
7. The active-passive combined super capacitor balance system according to claim 6, wherein the second resistor and the third resistor are two load resistors connected in parallel, and the electric energy flowing through the resistors can be converted into heat energy with high efficiency and lost, thereby playing a role of discharging the electric energy.
8. The active-passive combined super capacitor balancing system according to claim 6, further comprising a current loop for indicating which super capacitor cell is currently in passive balanced discharge, wherein the current loop comprises a fuse, a third MOS, a diode, a fourth resistor, and the super capacitor cell, wherein the fourth resistor is a current limiting resistor, and the fuse is used for preventing the super capacitor from being discharged with excessive current and causing damage to the circuit.
9. An active and passive combined super capacitor equalization method is characterized by comprising the following steps:
accurately estimating the residual electric quantity of each super capacitor monomer of the super capacitor module, and setting a first equalization threshold value and a second equalization threshold value;
in the charging and discharging process, if the difference value of the residual electric quantity of the super capacitor monomer with the highest residual electric quantity and the super capacitor monomer with the lowest residual electric quantity in the super capacitor module exceeds a first balance threshold value, an active balance mode is adopted, namely the electric quantity of the super capacitor monomer with the highest residual electric quantity in the module is transmitted to the super capacitor monomer with the lowest residual electric quantity;
when the residual electric quantity difference value of the super capacitor monomer with the highest residual electric quantity and the super capacitor monomer with the lowest residual electric quantity in the super capacitor module is smaller than a first balance threshold value but larger than a second balance threshold value, a passive balance mode is adopted, namely, the electric quantity of the super capacitor monomer with more residual electric quantity is discharged through a passive balance circuit.
10. The active-passive combined supercapacitor equalization method according to claim 9, wherein the first equalization threshold is set to 5% and the second equalization threshold is set to 1%.
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| CN116799915A (en) * | 2023-06-29 | 2023-09-22 | 航天锂电科技(江苏)有限公司 | Voltage reduction equalization circuit of lithium battery pack and control method thereof |
| CN120049578A (en) * | 2025-04-23 | 2025-05-27 | 安徽优旦科技股份有限公司 | Cloud full-time equilibrium capacity estimation method based on single voltage and electronic device |
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