WO2004031790A1

WO2004031790A1 - Pattern generator, memory controller, and test device

Info

Publication number: WO2004031790A1
Application number: PCT/JP2003/012574
Authority: WO
Inventors: Satoru Ohashi
Original assignee: Advantest Corporation
Priority date: 2002-10-01
Filing date: 2003-10-01
Publication date: 2004-04-15
Also published as: JPWO2004031790A1; DE10393444T5

Abstract

A pattern generator generates a test pattern for testing an electronic device. The pattern generator includes: a main memory for storing test data corresponding to a test pattern; a memory control section for controlling the main memory; and a test pattern output section for receiving the test data from the main memory and outputting a test pattern based on the test data. The memory control section has: a memory sequence storage section for rewritably storing a memory sequence indicating the order to give an input signal to an input pin of the main memory; and a memory access section for receiving the memory sequence from the memory sequence storage section, giving the input signal to the input pin of the main memory according to the memory sequence, and accessing the main memory.

Description

Description Pattern generator, memory controller, and test equipment

The present invention relates to a pattern generator, a memory controller, and a test device. In particular, the present invention relates to a pattern generator for generating a test pattern for testing an electronic device. This application is related to the following Japanese patent application. For those designated countries that are allowed to be incorporated by reference to the literature, the contents described in the following application are incorporated into this application by reference and are incorporated as part of the description of this application.

Japanese Patent Application No. 2 0 0 2— 2 8 8 4 1 1 Filing date October 1, 2004 Background technology

Conventionally, a pattern generator has been used in a test apparatus for testing an electronic device. The pattern generator generates a test pattern, which is an input signal to an electronic device, for testing an electronic device. The pattern generator generates test patterns from test data. The test apparatus has a main memory for storing test data.

As the main memory, for example, a large-capacity memory such as a dynamic random access memory is used. The dynamic random access memory has different interface specifications depending on the access speed, capacity, and type.

In the conventional test apparatus, a memory controller for controlling the main memory was designed in accordance with the interface specification of the dynamic random access memory to be used. For this reason, it was difficult to change the main memory for storing test data to a memory with a different interface specification.

Therefore, an object of the present invention is to provide a pattern generator, a memory controller, and a test device that can solve the above-described problems. The purpose is This is achieved by a combination of the features described in the independent claims in the boxes. The dependent claims define further advantageous embodiments of the present invention. Disclosure of the invention

In order to achieve such an object, according to a first aspect of the present invention, there is provided a pattern generator for generating a test pattern for testing an electronic device, the test data corresponding to a test pattern. A main memory for storing the test data, a memory control unit for controlling the main memory, and a test pattern output unit for receiving test data from the main memory and outputting a test pattern based on the test data. A memory sequence storage unit for rewritably storing a memory sequence indicating an order in which an input signal is to be applied to an in-memory input pin; a memory sequence received from the memory sequence storage unit; A memory access unit for supplying an input signal and accessing the main memory.

The main memory is a dynamic random access memory, the memory sequence storage unit stores a memory sequence corresponding to at least one of read, write, and refresh for the main memory, and the memory access unit stores the memory sequence. According to the memory sequence stored in the storage unit,

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The test pattern output unit outputs an access instruction instructing access to the main memory to the memory control unit, and the memory control unit sequentially stores and stores a plurality of access instructions received from the test pattern output unit. An access instruction storage unit for sequentially supplying a plurality of access instructions to the memory access unit, wherein the memory access unit performs an access corresponding to the access instruction in response to the access instruction sequentially received from the access instruction storage unit. May be received from the memory sequence storage unit, and the main memory may be accessed according to the memory sequence. The test pattern output unit outputs an access instruction including the address of the main memory. The memory access unit stores the correspondence between the access instruction and the row address of the main memory in a rewritable manner. A column address generator for generating a column address corresponding to the access instruction, and a column address generator for storing a correspondence between the access instruction and the column address of the main memory in a rewritable manner. An address signal output unit for applying an address signal to an address input pin of the main memory based on the generated row address and the column address generated by the dynamic address generation unit may be included. Further, the main memory is a dynamic random access memory, the memory sequence storage unit stores a memory sequence corresponding to the initialization memory access for initializing the main memory, and the memory access unit corresponds to the initialization memory access. The main memory may be initialized according to the memory sequence.

The memory access unit further includes a setting information storage unit for storing information to be set in a mode register for setting an operation of the main memory, and in a memory sequence corresponding to the initialization memory access, the memory access unit includes: Information to be set may be set in the mode register of the memory.

Further, the memory access unit may set at least one of the burst length, the wrap type, or the CAS latency in the mode register.

Further, the pattern generator may further include a nonvolatile memory for storing the memory sequence, and the memory sequence storage unit may read the memory sequence from the nonvolatile memory and store the read memory sequence.

According to a second aspect of the present invention, there is provided a memory controller for controlling a memory, comprising: a memory sequence storage unit for rewritably storing a memory sequence indicating an order in which an input signal should be applied to an input pin of the memory; A memory access unit that receives the memory sequence from the sequence storage unit, applies an input signal to an input pin of the memory according to the memory sequence, and accesses the memory.

According to a third aspect of the present invention, there is provided a test apparatus for testing an electronic device, comprising: A main memory that stores test data corresponding to a test pattern for testing a child device, a memory control unit that controls the main memory, receives test data from the main memory, and outputs a test pattern based on the test data. A memory including: a test pattern output unit; a waveform shaper for shaping the test pattern; and a determination unit for judging pass / fail of the electronic device based on an output signal output by the electronic device based on the test pattern. The control unit includes a memory sequence storage unit that rewritably stores a memory sequence indicating an order in which an input signal is to be applied to an input pin of the main memory, a memory sequence storage unit that receives the memory sequence from the memory sequence storage unit, and stores the main sequence according to the memory sequence. Apply input signals to the memory input pins to access the main memory And a memory access unit. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram illustrating an example of a configuration of a test apparatus 100 according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the configuration of the pattern generator 50.

FIG. 3 is a diagram showing an example of a detailed configuration of the memory control unit 70.

FIG. 4 is a diagram showing an example of a memory sequence stored in the memory sequence storage unit 204.

FIG. 5 is a flowchart showing an example of the operation of the memory control unit 70. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims, and all combinations of the features described in the embodiments are inventions. Is not necessarily essential to the solution of the above.

FIG. 1 shows an example of a configuration of a test apparatus 100 according to an embodiment of the present invention. The test apparatus 100 tests the electronic device 200. The test apparatus 100 includes a pattern generator 50, a waveform shaper 40, a signal input / output unit 30, and a judgment unit 20. The pattern generator 500 generates a test pattern for testing the electronic device 200 based on the test data stored in the internal main memory, for example, according to an instruction from the tester control unit 150. The tester control unit 150 is, for example, a computer such as a workstation. The pattern generator 500 may generate an expected value signal indicating an expected value that the electronic device 200 should output based on the input test pattern. The main memory may be provided in the tester control unit 150. In this case, the pattern generator 50 receives the test data from the tester controller 150.

The waveform shaper 40 receives the test pattern and shapes the test pattern. Further, the waveform shaper 40 supplies the test pattern received at a desired timing to the signal input / output unit 30.

The signal input / output unit 30 supplies the received test pattern to the electronic device _200, and receives an output signal output from the electronic device ₂₀₀ based on the test pattern. Further, the signal input / output unit 30 supplies the received output signal to the determination unit 20.

The determination unit 200 determines the quality of the electronic device 200 based on the received output signal. For example, the determination unit 20 receives the expected value signal from the pattern generator 50, and compares the expected value signal with the output signal of the electronic device 200 to determine the quality of the electronic device 200. I do.

FIG. 2 shows an example of the configuration of the pattern generator 50. The pattern generator 50 includes a main memory 60, a memory control unit 70, a test pattern output unit 85, an algorithm pattern generation unit 120, a capture unit 130, a capture control unit 140, and a failure memory. 10 is provided.

The main memory 60 is a memory for storing test data for generating a test pattern. The test data is divided into a plurality of test data blocks and stored. For example, the main memory 600 includes a plurality of pattern data blocks obtained by dividing pattern data indicating signals to be supplied to the electronic device 200, and sequence data indicating an order in which the pattern data should be supplied to the electronic device 200. The sequence data block obtained by dividing the above is stored as a test data block. Also, the main memory 60 The pattern data block and the sequence data block are stored in association with each other. The test pattern output section 85 has a path control section 110, a pattern generation section 80, and a sequencer 90. The path control unit 110 receives, from the tester control unit 150, instruction information indicating the order in which the test data blocks are to be supplied to the pattern generation unit 80 and the Z or sequencer 90. Then, the bus control unit 110 sequentially instructs the memory control unit 70 which pattern data block and / or sequence data block should be read from the main memory 60 based on the instruction information. In this case, the bus control unit 110 outputs an access instruction instructing access to the main memory 60 to the memory control unit 70. The memory control unit 70 sequentially reads the pattern data block and the sequence data block from the main memory 60 in response to the access command received from the path control unit 110. Then, the memory control unit 70 sequentially supplies the read pattern data blocks to the pattern generation unit 80, and sequentially supplies the read sequence data blocks to the sequencer 90.

The pattern generation unit 80 sequentially receives the pattern data blocks and generates a test pattern based on the pattern data blocks. The sequencer 90 sequentially stores the received sequence data blocks, and controls the pattern generator 80 based on the stored sequence data blocks. The sequence data block is, for example, a program for designating an order in which data in the pattern data block is to be output and generating a test pattern. The test pattern according to the program is generated in the pattern generation unit 80. Let it. The sequencer 90 may sequentially instruct the pattern generator 80 on the address of the pattern data block to be received by the pattern generator 80 based on the sequence data block.

When the electronic device 200 to be tested is a memory, the sequencer 90 may supply an instruction signal for generating pattern data for a memory test to the algorithm pattern generator 120. Upon receiving the instruction signal, the algorithm pattern generation unit 120 generates pattern data for a memory test based on a preset algorithm. In this case, the pattern generator 80 sets the pattern for the memory test. A test pattern is further generated based on the input data.

The capture unit 130 and the capture control unit 140 store the determination result in the determination unit 20 in the fail memory 10. The capture unit 130 receives the address of the pattern data block instructed by the sequencer 90 to the pattern generation unit 80 or the memory test data generated by the algorithm pattern generation unit 120, or both. The capture unit 130 adds one or both of the address of the corresponding pattern data block and the corresponding memory test data to the determination result. The capture control unit 140 receives, from the tester control unit 150, an instruction signal for instructing whether or not a force to store the determination result in the fail memory 10 is present, and in response to the instruction signal, determines the determination result in the fail memory. Supply 10

In addition, when the test using one pattern data block is completed, the capture control unit 140 may notify the bus control unit 110 of the determination result in the pattern data block. In this case, the path control unit 110 notifies the tester control unit 150 of the determination result.

Further, the fail memory 10 stores the judgment result in the judgment unit 20. The tester control unit 150 may read the judgment result stored in the fail memory 10 and analyze the test result of the electronic device 200.The tester control unit 150 may determine the test result based on the judgment result of each pattern data block. An analysis may be performed. In this example, the pattern generator 50 has the fail memory 10, but in other examples, the pattern generator 50 does not have the fail memory 10 and the test apparatus 100 May have a fail memory 10, and the tester controller 150 may have a fail memory 10. FIG. 3 shows an example of a detailed configuration of the memory control unit 70. The memory control unit 70 is a memory controller that controls the main memory 60, and includes a memory sequence storage unit 204, an access instruction storage unit 202, a memory access unit 206, and a nonvolatile memory 208. Having.

Here, in the present embodiment, the main memory 60 is a dynamic random access memory. In addition, the path control unit 110 in the test pattern output unit 85 (Fig. 2) outputs an access instruction including the address of the main memory 60 to the memory control unit 70.

The memory sequence storage unit 204 rewritably stores a memory sequence indicating an order in which an input signal should be given to an input pin of the main memory 60. Then, when the memory control unit 70 receives an access command from the test pattern output unit 85, the memory sequence storage unit 204 supplies a memory sequence corresponding to the access command to the memory access unit 206. .

Note that, in the present embodiment, the memory sequence storage unit 204 reads out and stores the memory sequence in advance from the non-volatile memory 208 that stores the memory sequence. In another embodiment, the memory sequence storage unit 204 may receive and store the memory sequence from the tester control unit 150 (see FIG. 1) via the path control unit 110. . In addition, the memory sequence storage unit 204 may read a part of the plurality of memory sequences from the nonvolatile memory 208 and receive another part from the tester control unit 150.

The access instruction storage unit 202 is a first-in first-out (FIFO) memory, sequentially stores a plurality of access instructions received from the test pattern output unit 85, and stores the plurality of stored access instructions in the memory access unit 2 0 to 6 sequentially.

The memory access unit 206 receives, from the memory sequence storage unit 204, a memory sequence for performing an access corresponding to the access instruction in response to the access instruction sequentially received from the access instruction storage unit 202. Then, the memory access unit 206 gives an input signal to an input pin of the main memory 60 according to the memory sequence and accesses the main memory 60. The memory access unit 206 includes a row address generation unit 303, a column address generation unit 308, a setting information storage unit 310, an address signal output unit 310, a command generation unit 304, and the like. The data control unit 302 is included. The row address generator 306 generates a row address of the main memory 60 in response to the access command, and supplies the generated address to the address signal output unit 312. In the present embodiment, the row address generation unit 303 is configured to execute an access instruction and a row address of the main memory 60. Is stored in a rewritable manner, and a row address of the main memory 60 is generated based on this correspondence. The column address generator 308 generates a column address of the main memory 60 in response to the access command, and supplies the column address to the address signal output unit 312. In the present embodiment, the column address generation unit 308 stores the correspondence between the access instruction and the column address of the main memory 60 in a rewritable manner. Based on this correspondence, the column address of the main memory 60 Generate an address.

The setting information storage section 310 stores information to be set in a mode register for setting the operation of the main memory 60. Further, the address signal output unit 312 receives the row address and the column address from each of the row address generation unit 310 and the column address generation unit 308, and based on the row address and the column address. Then, an address signal is applied to an address input pin of the main memory 60. The address signal output unit 312 further sets a mode register of the main memory 60 by outputting a predetermined signal to an address input pin of the main memory 60.

The command generation unit 304 generates a command corresponding to the access instruction, and provides the command to the main memory 60 according to a memory sequence. Further, the data control unit 302 controls input / output of a data signal to / from a data pin of the main memory 60 based on the access command and the memory sequence. Then, the data control section 302 receives the test data from the main memory 60 and supplies it to the test pattern output section 85. .

As described above, in the present embodiment, the memory control unit 70 reads test data from the main memory 60 according to the access instruction and supplies the test data to the test pattern output unit 85. As a result, the test pattern output unit 85 receives the test data from the main memory 60. Then, the test pattern output section 85 outputs a test pattern based on the test data.

Further, in the present embodiment, the memory sequence storage unit 204 stores the memory sequence in a rewritable manner. Therefore, according to the present embodiment, the memory sequence can be easily changed. FIG. 4 shows an example of a memory sequence stored in the memory sequence storage unit 204 (see FIG. 3). The memory sequence storage unit 204 stores a plurality of types of memory sequences corresponding to a plurality of types of access instructions.

The memory sequence storage unit 204 may store, for example, a memory sequence corresponding to at least one of read, write, and refresh for the main memory 60. The memory sequence storage unit 204 may store a memory sequence corresponding to an initialization memory access for initializing the main memory 60.

Each of the plurality of memory sequences includes a sequence of signals corresponding to an input signal to be provided to an input pin of main memory 60. For example, as shown in FIG. 4, the memory sequence corresponding to the read access command includes the signal sequence (1) to signal (k). The memory sequence storage unit 204 sequentially supplies each of the signals (1) to (k) to the memory access unit 206, and the memory access unit 206 responds to each of the received signals (1) to (k). To the input pin of the main memory 60. Note that each of the signals (1) to (k) may be a set of parallel signals to be simultaneously supplied to a plurality of input pins in the main memory 60.

In this case, the memory access unit 206 (see FIG. 3) first supplies a row address and an ACT (bank active) command to the main memory 60 in response to the signal (1), and responds to the signal (3). Supply column address and READ command to main memory 60. Then, the memory access unit 206 receives data output from the main memory 60 in response to the signals (5) to (k). The memory access unit 206 performs a no-operation (NOP) in response to the signal (2) and the signal (4).

According to the present embodiment, by rewriting the memory sequence stored in the memory sequence storage unit 204, it is possible to access a dynamic random access memory having different interface specifications.

FIG. 5 is a flowchart showing an example of the operation of the memory control unit 70. First, the memory sequence storage unit 204 reads a memory sequence from the non-volatile memory 208. And store it (S102).

Next, the memory access unit 206 initializes the main memory 60 according to an initialization memory sequence corresponding to the initialization memory access (S104). Here, the memo V access unit 206 may set at least one of burst length, wrap type, or CAS latency in the mode register of the main memory 60.

Next, each of the command generator 304, the row address generator 303, and the column address generator 308 sends an access command from the test pattern output unit 85 via the access command storage unit 202. Then, based on the access instruction and the memory sequence, a command, a row address, and a column address are generated (S106).

Then, each of the command generation section 304, the address signal output section 3122, and the data control section 302 supplies an input signal to the input pin of the main memory 60 according to the memory sequence (S108) ). In this case, each of the command generation unit 304, the address signal output unit 312, and the data control unit 302 supplies the first signal included in the memory sequence to the input pin of the main memory 60. . Further, data control section 302 may receive a data signal output from main memory 60 according to a memory sequence.

Next, the memory sequence storage unit 204 determines whether to end the memory sequence (S110). The memory sequence storage unit 204 may determine that the memory sequence ends when the last signal of the plurality of signals included in the memory sequence is supplied to the main memory 60 in S108.

When terminating the memory sequence, the access command storage unit 202 receives the next access command from the test pattern output unit 85 (S106). If the memory sequence is not terminated, the command generation section 304, the address signal output section 3112, and the data control section 302 supply the next signal included in the memory sequence to the main memory 60. (S108).

In the present embodiment, the memory control unit 70 Accesses the main memory 60 according to the memory sequence stored in a rewritable manner. Therefore, according to the present embodiment, even when the type of the memory used for the main memory 60 is changed, the memory sequence stored in the memory sequence Can be accessed. Thus, the main memory 60 included in the test apparatus 100 can be easily changed to a memory having a different interface specification.

Although the embodiments of the present invention have been described above, the technical scope of the present invention according to the present application is not limited to the above embodiments. The invention described in the claims can be implemented by adding various changes to the above embodiment. It is also apparent from the claims that such an invention belongs to the technical scope of the invention according to the present application. Industrial applicability

As is clear from the above description, according to the present invention, the memory provided in the test apparatus or the like can be easily changed to a memory having a different interface specification.

Claims

The scope of the claims

1. A pattern generator for generating a test pattern for testing an electronic device,

A main memory that stores test data corresponding to the test pattern; a memory control unit that controls the main memory;

A test pattern output unit that receives the test data from the main memory and outputs the test pattern based on the test data;

With

The memory control unit includes:

A memory sequence storage unit for rewritably storing a memory sequence indicating an order in which an input signal is to be applied to an input pin of the main memory;

A memory access unit for receiving the memory sequence from the memory sequence storage unit, applying the input signal to the input pin of the main memory according to the memory sequence, and accessing the main memory;

A pattern generator having:

2. The main memory is a dynamic random access memory, and the memory sequence storage unit stores the memory sequence corresponding to at least one of read, write, and refresh for the main memory, and the memory access unit 2. The pattern generator according to claim 1, wherein the main memory is accessed in accordance with the memory sequence stored in the memory sequence storage.

3. The test pattern output unit outputs an access command indicating access to the main memory to the memory control unit,

The memory control unit further includes an access command storage unit that sequentially stores the plurality of access commands received from the test pattern output unit and sequentially supplies the stored plurality of access commands to the memory access unit. The memory access unit receives the memory sequence for performing the access corresponding to the access command from the memory sequence storage unit in response to the access command sequentially received from the access command storage unit; 2. The pattern generator according to claim 1, wherein the main memory is accessed according to a sequence.

4. The test pattern output unit outputs the access command including an address of the main memory,

The memory access unit,

A row address generation unit that rewritably stores a correspondence between the access command and a row address of the main memory and generates the address corresponding to the access command;

A column address generation unit that rewritably stores a correspondence between the access instruction and a column address of the main memory and generates the column address corresponding to the access instruction;

An address signal output unit for applying an address signal to an address input pin of the main memory based on the row address generated by the row address generation unit and the column address generated by the column address generation unit;

4. The pattern generator according to claim 3, comprising:

5. The main memory is a dynamic random access memory, and the memory sequence storage stores the memory sequence corresponding to an initialization memory access for initializing the main memory,

2. The pattern generator according to claim 1, wherein the memory access unit initializes the main memory according to a memory sequence corresponding to the initialization memory access.

6. The memory access unit further includes a setting information storage unit for storing information to be set in a mode register for setting an operation of the main memory,

In the memory sequence corresponding to the initialization memory access, 6. The pattern generator according to claim 5, wherein the memory access unit sets the information to be set in a mode register of the main memory.

7. The pattern generator according to claim 6, wherein the memory access unit sets at least one of a burst length, a lap type, and a CAS latency in the mode register.

8. The pattern generator further includes a non-volatile memory for storing the memory sequence,

2. The pattern generator according to claim 1, wherein the memory sequence storage reads and stores the memory sequence from the non-volatile memory.

9. A memory controller for controlling a memory,

A memory sequence storage unit for rewritably storing a memory sequence indicating an order in which an input signal is to be applied to an input pin of the memory;

A memory access unit that receives the memory sequence from the memory sequence storage unit, applies the input signal to the input pin of the memory according to the memory sequence, and accesses the memory;

A memory controller comprising:

10. A test apparatus for testing an electronic device,

A main memory for storing test data corresponding to a test pattern for testing the electronic device;

A memory control unit that controls the main memory;

A waveform shaper for shaping the test pattern;

A determination unit configured to determine the acceptability of the electronic device based on an output signal output by the electronic device based on the test pattern; and

With

The memory control unit includes: A memory sequence storage unit for rewritably storing a memory sequence indicating an order in which an input signal is to be applied to an input pin of the main memory;

A test device having: