WO2004025733A1 - Non-planar nitride-based semiconductor structure and metehod for fabricating the same - Google Patents

Non-planar nitride-based semiconductor structure and metehod for fabricating the same Download PDF

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Publication number
WO2004025733A1
WO2004025733A1 PCT/US2003/029373 US0329373W WO2004025733A1 WO 2004025733 A1 WO2004025733 A1 WO 2004025733A1 US 0329373 W US0329373 W US 0329373W WO 2004025733 A1 WO2004025733 A1 WO 2004025733A1
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layer
ain
semiconductor structure
gan
metal contacts
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PCT/US2003/029373
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French (fr)
Inventor
Jeong Sun Moon
Paul Hashimoto
Wah S. Wong
David E. Grider
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Hrl Laboratories, Llc
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Priority claimed from US10/386,960 external-priority patent/US6830945B2/en
Application filed by Hrl Laboratories, Llc filed Critical Hrl Laboratories, Llc
Priority to AU2003270755A priority Critical patent/AU2003270755A1/en
Publication of WO2004025733A1 publication Critical patent/WO2004025733A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a method for fabricating a semiconductor structure useful for fabricating a non-planar heterostructure field effect transistor. More specifically, the present invention relates to a method for fabricating a semiconductor structure useful for fabricating a non-planar nitride-based heterostructure field effect transistor, wherein the non-planar region is fabricated in the group Ill-nitride material aluminum nitride (AIN) and the semiconductor structure is not damaged by dry etching or wet etching.
  • AIN group Ill-nitride material aluminum nitride
  • the present disclosure describes a method for fabricating a non-planar nitride- based heterostructure field effect transistor.
  • a non-planar heterostructure field effect transistor is a field effect transistor comprising several different semiconductor layers of semiconductor material, wherein the top layer has a non-planar region. Typically a gate is then formed in the non-planar region. By forming the gate in the non-planar region, the parasitic resistance of the heterostructure field effect transistor is lowered. Furthermore, a higher breakdown voltage and transconductance, as discussed below, can be achieved. However, fabricating a non-planar heterostructure field effect transistor using group Hi-nitride substrates can be troublesome.
  • Transconductance is a measure of how the output current of the device changes with the applied voltage at the input of the device.
  • the breakdown voltage is a threshold voltage, which, when exceeded, causes current in the gate to flow uncontrollably. This ultimately leads to the destruction of the device.
  • the breakdown voltage is directly related to the bandgap as described above. Another benefit of having a higher breakdown voltage is improved gate modulation of the channel under a strong RF input drive, which improves power performance of the transistor.
  • group Ill-nitride substrates to fabricate a non-planar region in the top layer is popular because group ffl-nitride substrates have much higher bandgaps than more traditional substrates such as silicon.
  • the bandgap of a substrate refers to the degree to which it can support an applied electric field before breaking down. Thus, the applied voltage that a substrate can maintain is directly proportional to the bandgap of the substrate.
  • Dry etching processes have also been used in an attempt to create a non-planar region in a GaN substrate.
  • dry etching introduces unrecoverable damage to the surface of the GaN substrate. Similar damage is also present when using an AlGaN substrate. The surface damage can be repaired by a post-annealing process, but removing all the surface damage is not possible.
  • Another problem with dry-etching in GaN and AlGaN is the difficulty in controlling the etch depth. Techniques attempting to fabricate recessed gates using GaN are discussed in J.W. Burm et al., "Recessed gate GaN MODFETS," Solid-State Electronics vol 41, pp. 247-250 (1997), and T.
  • the present invention provides a transistor having a device structure that allows for the use of dry-etching and wet-etching to create a non-planar region without damaging the transistor.
  • the present invention makes use of the group Ill-nitride material AIN for creating a non-planar region.
  • AIN has not been used for this application because of the focus on GaN. Because GaN has one of the highest bandgaps of any group Ill-nitride material, it has been more desirable to find a compatible wet etching process that will work with GaN, than it is to attempt the process with a different group ffl-nitride material.
  • AIN along with the device structure of the transistor disclosed herein, is processed in conjunction with the wet-etching and dry-etching process disclosed herein, a non-planar region can be fabricated consistently and repeatedly without inducing damage to the rest of the transistor.
  • Such results have not been attainable using GaN or other group Ill-nitride materials to fabricate non-planar regions in heterostructure field effect transistors.
  • the present invention provides a substrate, whereon at least one layer of semiconductor material is deposited.
  • a layer of AIN is deposited on the at least one layer.
  • An active channel is created at the interface of the AIN layer and the at least one layer. Charges are induced in the channel by both spontaneous polarization and piezoelectric strain at the interface.
  • the at least one layer may further consist of a plurality of layers of different semiconductor material. The interface created by the plurality of layers of semiconductor material serves as the channel of the transistor.
  • a capping layer is preferably deposited on the AIN layer.
  • the capping layer helps prevents oxidation from forming on the AIN layer.
  • Ohmic metal contacts are deposited on the capping layer by metal evaporation. The ohmic metal contacts are then annealed so that they diffuse into the transistor, where they contact the channel. The ohmic metal contacts may then be used as a source and drain for the transistor.
  • a portion of the capping layer is removed using a reactive ion etch (a dry etch) to expose a portion of the AIN layer.
  • a reactive ion etch a dry etch
  • the exposed portion of the AIN layer is not removed by the dry-etch, thereby acting as an etch stop and preventing damage to the layers of semiconductor material beneath the AIN layer caused by the dry- etch.
  • a portion of the AIN layer is removed with a solvent to create a non-planar region.
  • the solvent can remove the desired portion of the AIN layer with predictable and repeatable results without reducing the performance of the transistor caused by damage to the AIN layer.
  • the solvent to etch the AIN layer helps remove any surface damage on the AIN layer induced by the reaction ion etch. Also, the layers of semiconductor material beneath the AIN layer are insoluble in the solvent. As a result, the layers of semiconductor material work as a controllable etch stop for etching AIN, thereby preventing damage to the semiconductor layers beneath the AIN layer.
  • Fig. la shows the substrate according to a first embodiment
  • Fig. lb shows the first layer deposited on the substrate
  • Fig. lc shows the AIN layer deposited on the first layer and the interface
  • Fig. Id shows the capping layer and photoresist deposited on the AIN layer;
  • Fig. le shows a portion of the photoresist layer removed;
  • Fig. If shows the ohmic metal contacts deposited on the capping layer
  • Fig. Ig shows the ohmic contact regions
  • Fig. Ih shows the second window to expose a portion of the capping layer
  • Fig. li shows the removal of a portion of the capping layer
  • Fig. Ij shows the non-planar gate region
  • Fig. Ik shows the gate deposited in the non-planar gate region.
  • Fig. 2a shows a substrate of the second embodiment
  • Fig. 2b shows a first layer deposited on the substrate
  • Fig. 2c shows a second layer deposited on the first layer, and the interface
  • Fig. 2d shows the third layer deposited on the second layer
  • Fig. 2e shows the AIN layer deposited on the third layer
  • Fig. 2f shows the capping layer and photoresist layer deposited on the AIN layer
  • Fig. 2g shows the removal of a portion of the photoresist layer
  • Fig. 2h shows the ohmic metal contacts deposited on the capping layer
  • Fig. 2i shows the ohmic metal regions in the capping layer, AIN layer, second layer, and third layer;
  • Fig. 2j shows a portion of the photoresist layer removed
  • Fig. 2k shows a portion of the capping layer removed
  • Fig. 21 shows the non-planar gate region
  • Fig. 2m shows the gate deposited in the non-planar gate region.
  • Fig. 3a shows the substrate; Fig. 3b shows the first layer deposited on the substrate; Fig. 3c shows the second layer deposited on the first layer; Fig. 3d shows the AIN layer deposited on the second layer Fig. 3e shows the capping layer and photoresist layer deposited on the AIN layer; Fig. 3f shows a portion of the photoresist removed; Fig. 3g shows ohmic metal contacts deposited on the capping layer;
  • Fig. 3h shows the ohmic metal regions in the capping layer, AIN layer, and second layer; Fig. 3i shows a portion of the photoresist layer on the capping layer removed; Fig. 3j shows a portion of the capping layer removed Fig. 3k shows the non-planar gate region; and Fig. 31 shows the gate deposited in the non-planar gate region.
  • a substrate 102 is provided as shown in Fig. la.
  • the substrate 102 preferably comprises sapphire, silicon carbide, or GaN.
  • a first layer 104 is provided as shown in Fig. lb.
  • the first layer 104 is deposited, preferably epitaxially, on the substrate 102.
  • the first layer 104 preferably comprises GaN, however other materials such as InP or InGaN can be used as well.
  • an AIN layer 108 is provided as shown in Fig. lc.
  • the AIN layer 108 is preferably deposited epitaxially on the first layer 104.
  • the AIN layer 108 has a thickness of preferably not more than 10 nm.
  • an interface 106 is created as shown in Fig. lc.
  • the interface 106 serves as the channel of the transistor, which will be discussed later.
  • a capping layer 109 is preferably deposited on the AIN layer 108 as shown in Fig. Id, followed by a layer of photoresist 11 .
  • the capping layer 109 preferably comprises GaN and helps prevent oxidation from forming on the AIN layer 108 during subsequent processing steps.
  • first windows 112 which expose part of the surface of the capping layer 109 as shown in Fig. le.
  • Ohmic metal contacts 118 are deposited in the first windows 112 on the surface of the capping layer 109 using metal evaporation as shown in Fig. If.
  • the ohmic metal contacts 118 can be comprised of a combination of Ti/Al or Ta/Ti/Al, which are deposited in that order and are about 320 nm thick.
  • the ohmic metal contacts 118 are then annealed at a temperature in the range of about 600-800° C for about a minute.
  • ohmic metal contacts 118 to diffuse into the capping layer 109 and AIN layer 108, thereby creating an ohmic contact region 119 as shown in Fig. lg.
  • the ohmic metal contact region 119 can then be used as a source and a drain.
  • the remaining portion of the photoresist layer 110 on the AIN layer 108 is patterned to create a second window 122 as shown in Fig. Ih.
  • the second window 122 exposes part of the capping layer 109.
  • the exposed portion of the capping layer 109 is etched away using a reactive ion etch preferably with chlorine gas at an etch rate of about 72nm/min. Etching away a portion of the capping layer 109 exposes a portion of the surface of the AIN layer 108 as shown in Fig. li, however the reactive ion etching does not remove any significant portion of the AIN layer 108.
  • the AIN layer 108 effectively acts as an etch stop, thereby preventing the reactive ion etch from damaging the first layer 104 beneath the AIN layer 108. It is possible though, for the exposed portion of the surface of the AIN layer 108 to incur damage caused by the reactive ion etch. Also, the remaining portion of the photoresist layer 110 is removed using techniques known in the art. Next, using the remaining portion of the capping layer 109 as a mask, the exposed portion of the AIN layer 108 is etched away at room temperature with a solvent to create a non- planar gate region 124 as shown in Fig. Ij.
  • the solvent preferably comprises potassium hydroxide (KOH), water, and potassium borates, and is sold under the trade name AZ- 400 by the Clariant Corporation of Somerville, NJ.
  • Etching the AIN layer 108 helps remove any surface damage on the AIN layer 108 caused by the reactive ion etching of the capping layer 109.
  • AZ-400 has an etch rate of approximately lOOA/min.
  • a gate 126 is deposited in the non-planar gate region 124 as shown in Fig. Ik.
  • the gate 126 is preferably T-shaped to help reduce intrinsic resistance. Fabricating a T-shaped structure is a technique well known in the art.
  • the interface 106 between the AIN layer 108 and first layer 104 already contains carrier charges due to the well-known effects of spontaneous polarization. In this way, the interface 106 acts as a channel for the transistor without requiring any additional doping. However, additional doping can be provided, if desired.
  • the transistor is biased with a voltage at the gate 126, and at either of the ohmic contact regions 119, the carrier charges at the interface 106 flow between the ohmic contact regions 119 allowing operation of the non-planar heterostructure field effect transistor.
  • a substrate 202 as shown in Fig. 2a is provided.
  • the substrate 202 preferably comprises sapphire, silicon carbide, or GaN.
  • a first layer 204 is deposited, preferably epitaxially, on the substrate 202 as shown in Fig. 2b.
  • the first layer 204 preferably comprises GaN, however other materials such as InN or InGaN can be used as well.
  • a second layer 206 is deposited, preferably epitaxially, on the first layer 204.
  • the second layer 206 as shown in Fig. 2c, preferably comprises AlGaN.
  • an interface 208 is created.
  • the interface 208 is located where the first layer 204 contacts the second layer 206 and is further discussed later.
  • a third layer 210 is deposited, preferably epitaxially, on the surface of the second layer 206 as shown in Fig. 2d.
  • This third layer 210 preferably comprises GaN.
  • the purpose of the third layer 210 will be discussed later.
  • an AIN layer 212 is deposited preferably epitaxially as shown in Fig. 2e.
  • the AIN layer 212 is preferably no greater than 10 nm thick.
  • a capping layer 213 as shown in Fig. 2f is preferably deposited on the AIN layer 212, followed by a photoresist layer 214. The purpose of the capping layer 213 is to prevent oxidation from forming on the surface of the AIN layer 212 during subsequent processing steps.
  • a portion of the photoresist layer 214 is patterned, and removed using techniques known in the art to create first windows 216, which expose part of the surface of the capping layer 213 as shown in Fig. 2g.
  • ohmic metal contacts 222 are deposited in the first windows 216 as shown in Fig. 2h.
  • the ohmic metal contacts 222 can be comprised of a combination of Ti/Al or Ta/Ti/Al, which are deposited in that order and are about 320 nm thick.
  • the ohmic metal contacts 222 are annealed at a temperature in the range of about 600-800° C for about a minute. This allows the ohmic metal contacts 222 to diffuse into the capping layer 213, the AIN layer 212, the third layer 210, and the second layer 206, creating an ohmic contact region 223 as shown in Fig. 2i.
  • the ohmic contact region 223 can then be used as a source and a drain.
  • a portion of the remaining photoresist layer 214 is patterned and removed using techniques well-known in the art, creating a second window 226, as shown in Fig. 2j.
  • the second window 226 exposes part of the capping layer 213.
  • the exposed portion of the capping layer 213 is etched away using a reactive ion etch preferably with chlorine gas at an etch rate of about 72nm/min. Etching away a portion of the capping layer 213 exposes a portion of the surface of the AIN layer 212 as shown in Fig. 2k, however the reactive ion etching does not remove any significant portion of the AIN layer 212.
  • the Ain layer 212 effectively acts as an etch stop, thereby preventing the reactive ion etch from removing portions of the first, second, or third layers 204, 206, 210 beneath the AIN layer 212. It is possible though, for the exposed portion of the surface of the AIN layer 212 to incur damage caused by the reactive ion etch. Also, the remaining portion of the photoresist layer 214 is removed using techniques known in the art. Next, using the remaining portion of the capping layer 213 as a mask, a portion of the exposed surface of the AIN layer 212 is removed with a solvent to create a non-planar gate region 228 as shown Fig. 21.
  • the solvent preferably comprises potassium hydroxide (KOH), water, and potassium borates, and is sold under the trade name AZ-400 by the Clariant Corporation of Somerville, NJ.
  • Etching the AIN layer 212 helps remove any surface damage on the AIN layer 212 caused by the reactive ion etching of the capping layer 213.
  • the non-planar gate region 228 is created by completely etching away a portion of the AIN layer 212.
  • this embodiment would work if the AIN layer 212 was not completely etched away as shown in Fig. lj of the first embodiment. In the first embodiment, the AIN layer 108 was not completely etched away.
  • the third layer 210 preferably comprises GaN.
  • GaN is insoluble in AZ-400 and effectively acts as an etch stop, preventing the AZ-400 from damaging the layers located under the AIN layer 212.
  • a gate 230 is then deposited in the non-planar gate region 228 as shown in Fig. 2m.
  • the gate 230 is preferably T-shaped to help reduce intrinsic resistance and capacitance. Fabricating a T-shaped structure is a technique well-known in the art.
  • the interface 208 between the first layer 204 and the second layer 206 already contains carrier charges due to the well-known effects of spontaneous polarization. In this way, the interface 208 acts as a channel for the transistor without requiring any additional doping. However, additional doping can be provided, if desired.
  • the transistor is biased with a voltage at the gate 230 and at either of the ohmic contact regions 223, the charges at the interface 208 flow between the ohmic contact regions 223, allowing operation of the non-planar heterostructure field effect transistor.
  • a substrate 302 is provided as shown in Fig. 3a.
  • the substrate 302 preferably comprises sapphire, silicon carbide, or GaN.
  • a first layer 304 preferably comprising GaN is provided as shown in Fig. 3b, however, other materials such as InN or InGaN could work equally as well.
  • the first layer 304 is deposited, preferably epitaxially, on the substrate 302.
  • a second layer 306 is provided as shown in Fig. 3c.
  • the second layer 306 preferably comprises AlGaN and is deposited, preferably epitaxially, on the first layer 304.
  • an interface 305 is created.
  • the interface 305 is located where the first layer 304 contacts the second layer 306 and is further discussed later.
  • an AIN layer 308 is deposited, preferably epitaxially on the second layer 306 as shown in Fig. 3d.
  • the AIN layer 308 is preferably no greater than 10 nm thick.
  • a capping layer 309 preferably comprising GaN, is preferably deposited on the AIN layer 308, followed by a photoresist layer 310 as shown in Fig. 3e.
  • the purpose of the capping layer 309 is to prevent oxidation from forming on the surface of the AIN layer 308 during subsequent processing steps.
  • first windows 312 which expose part of the surface of the capping layer 309 as shown in Fig. 3f.
  • Ohmic metal contacts 318 are deposited in the first windows 312 using metal evaporation as shown in Fig. 3g.
  • the ohmic metal contacts 318 can be comprised of a combination of Ti/Al or Ta/Ti/Al, which are deposited in that order and are about 320 nm thick.
  • the ohmic metal contacts 318 are annealed at a temperature in the range of about 600-800° C for about a minute.
  • ohmic metal contacts 318 can diffuse into the capping layer 309, the AIN layer 308, and the second layer 306, creating an ohmic contact region 319 as shown in Fig. 3h.
  • the ohmic contact region 319 can then be used as a source and a drain.
  • a portion of the remaining photoresist layer 310 is patterned and removed as shown in Fig. 3i using techniques well-known in the art, to create a second window 322.
  • the second window 322 exposes part of the capping layer 309 as shown in Fig. 3i.
  • the exposed portion of the capping layer 309 is removed using a reactive ion etch preferably with chlorine gas at an etch rate of about 72nm/min. Etching away a portion of the capping layer 309 exposes a portion of the surface of the AIN layer 308 as shown in Fig. 3j, however the reactive ion etching does not remove any significant portion of the AIN layer 308.
  • the AIN layer 308 effectively acts as an etch stop to the reactive ion etching, thereby preventing the reactive ion etch from damaging the first or second layers 304, 306 beneath the AIN layer 308. It is possible though, for the exposed portion of the surface of the AIN layer 308 to incur damage caused by the reactive ion etch. Also, the remaining portion of the photoresist layer 310 is removed using techniques known in the art. Next, using the remaining portion of the capping layer 309 as a mask, a portion of the exposed AIN layer 308 is etched away with a solvent to create a non-planar gate region 324 as shown in Fig. 3k.
  • the solvent preferably comprises potassium hydroxide (KOH), water, and potassium borates, and is sold under the tradename AZ-400 by the Clariant Corporation of Somerville, NJ.
  • Etching the AIN layer 308 also helps removes any surface damage on the AIN layer 308 caused by the reactive ion etching of the capping layer 309.
  • the non-planar gate region 324 is created by completely etching a portion of the AIN layer 308 through to the second layer 306.
  • this embodiment would work if the AIN layer 308 was not completely etched away as shown in Fig. lj of the first embodiment. In the first embodiment the AIN layer 108 was not completely etched away.
  • the second layer 306 preferably comprises AlGaN.
  • AlGaN is insoluble in AZ-400 and effectively acts as an etch stop, preventing the AZ-400 from damaging the layers located under the AIN layer 308 should a portion of the AIN layer 308 be completely etched through to the second layer 306.
  • a gate 326 is deposited in the non-planar gate region 324 as shown in Fig. 31.
  • the gate 326 is preferably T-shaped in order to help reduce intrinsic resistance and capacitance. Fabricating a T-shaped structure is a technique well-known in the art. Because the first layer 304 and second layer 306 are comprised of group III-V materials, the interface 305 between the first layer 304 and second layer 306 already contains carrier charges due to the well-known effects of spontaneous polarization. In this way, the interface 305 acts as a channel for the transistor without requiring any additional doping. However, additional doping of the transistor can be provided, if desired. When the transistor is biased with a voltage at the gate 326 and at either of the ohmic contact regions 319, the charges at the interface 305 flow between the ohmic contact regions 319, allowing operation of the non-planar heterostructure field effect transistor.

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Abstract

A method for fabricating a non-planar heterostructure field effect transistor usinggroup III-nitride materials with consistent repeatable results is disclosed. The methodprovides a substrate (102) on which at least one layer of semiconductor material (104) is deposited. An AIN layer (108) is deposited on the at least one layer of semiconductor material. A portionof the AIN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AIN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at east one layerbeneath the AIN layer. Furthermore, should the AIN layer incur any surface damage as aresult of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.

Description

NON-PLANAR NITRIDE-BASED SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME
Cross-Reference to Related Applications
This application is related to and claims benefit of United States Provisional Application 60/411,076 filed on September 16, 2002, which is incorporated by reference in its entirety.
Field of the Invention
The present invention relates to a method for fabricating a semiconductor structure useful for fabricating a non-planar heterostructure field effect transistor. More specifically, the present invention relates to a method for fabricating a semiconductor structure useful for fabricating a non-planar nitride-based heterostructure field effect transistor, wherein the non-planar region is fabricated in the group Ill-nitride material aluminum nitride (AIN) and the semiconductor structure is not damaged by dry etching or wet etching. The present disclosure describes a method for fabricating a non-planar nitride- based heterostructure field effect transistor.
Background of the Invention
The use of group Ill-nitride substrates has become popular for fabricating a non- planar region in a non-planar heterostructure field effect transistor. A non-planar heterostructure field effect transistor is a field effect transistor comprising several different semiconductor layers of semiconductor material, wherein the top layer has a non-planar region. Typically a gate is then formed in the non-planar region. By forming the gate in the non-planar region, the parasitic resistance of the heterostructure field effect transistor is lowered. Furthermore, a higher breakdown voltage and transconductance, as discussed below, can be achieved. However, fabricating a non-planar heterostructure field effect transistor using group Hi-nitride substrates can be troublesome.
Transconductance is a measure of how the output current of the device changes with the applied voltage at the input of the device. The breakdown voltage is a threshold voltage, which, when exceeded, causes current in the gate to flow uncontrollably. This ultimately leads to the destruction of the device. The breakdown voltage is directly related to the bandgap as described above. Another benefit of having a higher breakdown voltage is improved gate modulation of the channel under a strong RF input drive, which improves power performance of the transistor.
The use of group Ill-nitride substrates to fabricate a non-planar region in the top layer is popular because group ffl-nitride substrates have much higher bandgaps than more traditional substrates such as silicon. The bandgap of a substrate refers to the degree to which it can support an applied electric field before breaking down. Thus, the applied voltage that a substrate can maintain is directly proportional to the bandgap of the substrate.
Previous attempts have been made to fabricate a non-planar heterostructure field effect transistor with a top layer comprising GaN, a group ffl-nitride substrate. However, using GaN has presented problems. When using a wet-etch there is no reliable or controllable method for controlling the regions in the GaN which are being etched. As a result, if the GaN layer is overetched, the layers beneath the GaN layer would be damaged by the wet etchant. There have also been attempts at fabricating a non-planar region in AlGaN where the AlGaN layer was partially wet-etched. Like GaN, using a wel-etch with AlGaN presented problems with controlling the area being etched and the depth of the etched area.
Dry etching processes have also been used in an attempt to create a non-planar region in a GaN substrate. However, dry etching introduces unrecoverable damage to the surface of the GaN substrate. Similar damage is also present when using an AlGaN substrate. The surface damage can be repaired by a post-annealing process, but removing all the surface damage is not possible. Another problem with dry-etching in GaN and AlGaN is the difficulty in controlling the etch depth. Techniques attempting to fabricate recessed gates using GaN are discussed in J.W. Burm et al., "Recessed gate GaN MODFETS," Solid-State Electronics vol 41, pp. 247-250 (1997), and T. Egawa et al., "Recessed gate AlGaN/GaN MODFET on Sapphire grown by MOCVD," IEDM tech Digest, pp.401-404 (1999). These references both use dry-etching techniques to fabricate the recessed gate.
Therefore, there is a need for a method for fabricating a non-planar heterostructure field effect transistor, wherein the non-planar region is fabricated in a group Ill-nitride material. There is also a need for a non-planar heterostructure field effect transistor in which dry-etching and wet-etching techniques can be used to create the non-planar region which does not induce damage to the transistor and allows good control of the etching depth.
Summary of the Invention
The present invention provides a transistor having a device structure that allows for the use of dry-etching and wet-etching to create a non-planar region without damaging the transistor. The present invention makes use of the group Ill-nitride material AIN for creating a non-planar region. AIN has not been used for this application because of the focus on GaN. Because GaN has one of the highest bandgaps of any group Ill-nitride material, it has been more desirable to find a compatible wet etching process that will work with GaN, than it is to attempt the process with a different group ffl-nitride material. However, when AIN along with the device structure of the transistor disclosed herein, is processed in conjunction with the wet-etching and dry-etching process disclosed herein, a non-planar region can be fabricated consistently and repeatedly without inducing damage to the rest of the transistor. Such results have not been attainable using GaN or other group Ill-nitride materials to fabricate non-planar regions in heterostructure field effect transistors.
It is an object of the present invention to provide a novel method for fabricating a non-planar nitride-based heterostructure field effect transistor. The present invention provides a substrate, whereon at least one layer of semiconductor material is deposited. A layer of AIN is deposited on the at least one layer. An active channel is created at the interface of the AIN layer and the at least one layer. Charges are induced in the channel by both spontaneous polarization and piezoelectric strain at the interface. Furthermore, the at least one layer may further consist of a plurality of layers of different semiconductor material. The interface created by the plurality of layers of semiconductor material serves as the channel of the transistor. After depositing the AIN layer, a capping layer is preferably deposited on the AIN layer. The capping layer helps prevents oxidation from forming on the AIN layer. Ohmic metal contacts are deposited on the capping layer by metal evaporation. The ohmic metal contacts are then annealed so that they diffuse into the transistor, where they contact the channel. The ohmic metal contacts may then be used as a source and drain for the transistor.
Next, a portion of the capping layer is removed using a reactive ion etch (a dry etch) to expose a portion of the AIN layer. However, the exposed portion of the AIN layer is not removed by the dry-etch, thereby acting as an etch stop and preventing damage to the layers of semiconductor material beneath the AIN layer caused by the dry- etch. Then, by using the remaining portion of the capping layer as a mask, a portion of the AIN layer is removed with a solvent to create a non-planar region. The solvent can remove the desired portion of the AIN layer with predictable and repeatable results without reducing the performance of the transistor caused by damage to the AIN layer. Using the solvent to etch the AIN layer helps remove any surface damage on the AIN layer induced by the reaction ion etch. Also, the layers of semiconductor material beneath the AIN layer are insoluble in the solvent. As a result, the layers of semiconductor material work as a controllable etch stop for etching AIN, thereby preventing damage to the semiconductor layers beneath the AIN layer.
Brief Description of the Drawings
First Embodiment
Fig. la shows the substrate according to a first embodiment;
Fig. lb shows the first layer deposited on the substrate;
Fig. lc shows the AIN layer deposited on the first layer and the interface;
Fig. Id shows the capping layer and photoresist deposited on the AIN layer; Fig. le shows a portion of the photoresist layer removed;
Fig. If shows the ohmic metal contacts deposited on the capping layer;
Fig. Ig shows the ohmic contact regions;
Fig. Ih shows the second window to expose a portion of the capping layer;
Fig. li shows the removal of a portion of the capping layer; Fig. Ij shows the non-planar gate region; and
Fig. Ik shows the gate deposited in the non-planar gate region.
Second Embodiment
Fig. 2a shows a substrate of the second embodiment; Fig. 2b shows a first layer deposited on the substrate;
Fig. 2c shows a second layer deposited on the first layer, and the interface;
Fig. 2d shows the third layer deposited on the second layer;
Fig. 2e shows the AIN layer deposited on the third layer;
Fig. 2f shows the capping layer and photoresist layer deposited on the AIN layer; Fig. 2g shows the removal of a portion of the photoresist layer;
Fig. 2h shows the ohmic metal contacts deposited on the capping layer; Fig. 2i shows the ohmic metal regions in the capping layer, AIN layer, second layer, and third layer;
Fig. 2j shows a portion of the photoresist layer removed; Fig. 2k shows a portion of the capping layer removed; Fig. 21 shows the non-planar gate region; and
Fig. 2m shows the gate deposited in the non-planar gate region.
Third Embodiment Fig. 3a shows the substrate; Fig. 3b shows the first layer deposited on the substrate; Fig. 3c shows the second layer deposited on the first layer; Fig. 3d shows the AIN layer deposited on the second layer Fig. 3e shows the capping layer and photoresist layer deposited on the AIN layer; Fig. 3f shows a portion of the photoresist removed; Fig. 3g shows ohmic metal contacts deposited on the capping layer;
Fig. 3h shows the ohmic metal regions in the capping layer, AIN layer, and second layer; Fig. 3i shows a portion of the photoresist layer on the capping layer removed; Fig. 3j shows a portion of the capping layer removed Fig. 3k shows the non-planar gate region; and Fig. 31 shows the gate deposited in the non-planar gate region.
Detailed Description of Embodiments
The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are shown. This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
First Embodiment
A method useful for fabricating a non-planar nitride-based heterostructure field effect transistor according to a first embodiment of the present invention is described with reference to Figs. la-Ik. In this first embodiment, a substrate 102 is provided as shown in Fig. la. The substrate 102 preferably comprises sapphire, silicon carbide, or GaN. Next, a first layer 104 is provided as shown in Fig. lb. The first layer 104 is deposited, preferably epitaxially, on the substrate 102. The first layer 104 preferably comprises GaN, however other materials such as InP or InGaN can be used as well. Next, an AIN layer 108 is provided as shown in Fig. lc. The AIN layer 108 is preferably deposited epitaxially on the first layer 104. The AIN layer 108 has a thickness of preferably not more than 10 nm. When the AIN layer 108 is deposited on the first layer 104, an interface 106 is created as shown in Fig. lc. The interface 106 serves as the channel of the transistor, which will be discussed later. After the AIN layer 108 is deposited, a capping layer 109 is preferably deposited on the AIN layer 108 as shown in Fig. Id, followed by a layer of photoresist 11 . The capping layer 109 preferably comprises GaN and helps prevent oxidation from forming on the AIN layer 108 during subsequent processing steps.
Next, a portion of the photoresist layer 110 is patterned and removed using techniques well-known in the art, to create first windows 112, which expose part of the surface of the capping layer 109 as shown in Fig. le. Ohmic metal contacts 118 are deposited in the first windows 112 on the surface of the capping layer 109 using metal evaporation as shown in Fig. If. The ohmic metal contacts 118 can be comprised of a combination of Ti/Al or Ta/Ti/Al, which are deposited in that order and are about 320 nm thick. The ohmic metal contacts 118 are then annealed at a temperature in the range of about 600-800° C for about a minute. This allows the ohmic metal contacts 118 to diffuse into the capping layer 109 and AIN layer 108, thereby creating an ohmic contact region 119 as shown in Fig. lg. The ohmic metal contact region 119 can then be used as a source and a drain.
Next, the remaining portion of the photoresist layer 110 on the AIN layer 108 is patterned to create a second window 122 as shown in Fig. Ih. The second window 122 exposes part of the capping layer 109. The exposed portion of the capping layer 109 is etched away using a reactive ion etch preferably with chlorine gas at an etch rate of about 72nm/min. Etching away a portion of the capping layer 109 exposes a portion of the surface of the AIN layer 108 as shown in Fig. li, however the reactive ion etching does not remove any significant portion of the AIN layer 108. The AIN layer 108 effectively acts as an etch stop, thereby preventing the reactive ion etch from damaging the first layer 104 beneath the AIN layer 108. It is possible though, for the exposed portion of the surface of the AIN layer 108 to incur damage caused by the reactive ion etch. Also, the remaining portion of the photoresist layer 110 is removed using techniques known in the art. Next, using the remaining portion of the capping layer 109 as a mask, the exposed portion of the AIN layer 108 is etched away at room temperature with a solvent to create a non- planar gate region 124 as shown in Fig. Ij. The solvent preferably comprises potassium hydroxide (KOH), water, and potassium borates, and is sold under the trade name AZ- 400 by the Clariant Corporation of Somerville, NJ. Etching the AIN layer 108 helps remove any surface damage on the AIN layer 108 caused by the reactive ion etching of the capping layer 109. AZ-400 has an etch rate of approximately lOOA/min. Finally, a gate 126 is deposited in the non-planar gate region 124 as shown in Fig. Ik. The gate 126 is preferably T-shaped to help reduce intrinsic resistance. Fabricating a T-shaped structure is a technique well known in the art.
Because the AIN layer 108 and first layer 104 are comprised of group III-V materials, the interface 106 between the AIN layer 108 and first layer 104 already contains carrier charges due to the well-known effects of spontaneous polarization. In this way, the interface 106 acts as a channel for the transistor without requiring any additional doping. However, additional doping can be provided, if desired. When the transistor is biased with a voltage at the gate 126, and at either of the ohmic contact regions 119, the carrier charges at the interface 106 flow between the ohmic contact regions 119 allowing operation of the non-planar heterostructure field effect transistor.
Second Embodiment
A method for fabricating a non-planar heterostructure field effect transistor according to a second embodiment of the present invention is described with reference to Figs. 2a-2m. In this embodiment a substrate 202 as shown in Fig. 2a is provided. The substrate 202 preferably comprises sapphire, silicon carbide, or GaN. A first layer 204 is deposited, preferably epitaxially, on the substrate 202 as shown in Fig. 2b. The first layer 204 preferably comprises GaN, however other materials such as InN or InGaN can be used as well. A second layer 206 is deposited, preferably epitaxially, on the first layer 204. The second layer 206, as shown in Fig. 2c, preferably comprises AlGaN. By depositing the second layer 206 on top of the first layer 204, an interface 208 is created. The interface 208 is located where the first layer 204 contacts the second layer 206 and is further discussed later. A third layer 210 is deposited, preferably epitaxially, on the surface of the second layer 206 as shown in Fig. 2d. This third layer 210 preferably comprises GaN. The purpose of the third layer 210 will be discussed later. After the third layer 210 is deposited, an AIN layer 212 is deposited preferably epitaxially as shown in Fig. 2e. The AIN layer 212 is preferably no greater than 10 nm thick. Finally, a capping layer 213 as shown in Fig. 2f is preferably deposited on the AIN layer 212, followed by a photoresist layer 214. The purpose of the capping layer 213 is to prevent oxidation from forming on the surface of the AIN layer 212 during subsequent processing steps.
After depositing the photoresist layer 214, a portion of the photoresist layer 214 is patterned, and removed using techniques known in the art to create first windows 216, which expose part of the surface of the capping layer 213 as shown in Fig. 2g.
Next, ohmic metal contacts 222 are deposited in the first windows 216 as shown in Fig. 2h. The ohmic metal contacts 222 can be comprised of a combination of Ti/Al or Ta/Ti/Al, which are deposited in that order and are about 320 nm thick. The ohmic metal contacts 222 are annealed at a temperature in the range of about 600-800° C for about a minute. This allows the ohmic metal contacts 222 to diffuse into the capping layer 213, the AIN layer 212, the third layer 210, and the second layer 206, creating an ohmic contact region 223 as shown in Fig. 2i. The ohmic contact region 223 can then be used as a source and a drain.
Next, a portion of the remaining photoresist layer 214 is patterned and removed using techniques well-known in the art, creating a second window 226, as shown in Fig. 2j. The second window 226 exposes part of the capping layer 213. The exposed portion of the capping layer 213 is etched away using a reactive ion etch preferably with chlorine gas at an etch rate of about 72nm/min. Etching away a portion of the capping layer 213 exposes a portion of the surface of the AIN layer 212 as shown in Fig. 2k, however the reactive ion etching does not remove any significant portion of the AIN layer 212. The Ain layer 212 effectively acts as an etch stop, thereby preventing the reactive ion etch from removing portions of the first, second, or third layers 204, 206, 210 beneath the AIN layer 212. It is possible though, for the exposed portion of the surface of the AIN layer 212 to incur damage caused by the reactive ion etch. Also, the remaining portion of the photoresist layer 214 is removed using techniques known in the art. Next, using the remaining portion of the capping layer 213 as a mask, a portion of the exposed surface of the AIN layer 212 is removed with a solvent to create a non-planar gate region 228 as shown Fig. 21. The solvent preferably comprises potassium hydroxide (KOH), water, and potassium borates, and is sold under the trade name AZ-400 by the Clariant Corporation of Somerville, NJ. Etching the AIN layer 212 helps remove any surface damage on the AIN layer 212 caused by the reactive ion etching of the capping layer 213. As shown in Fig. 21, the non-planar gate region 228 is created by completely etching away a portion of the AIN layer 212. However, this embodiment would work if the AIN layer 212 was not completely etched away as shown in Fig. lj of the first embodiment. In the first embodiment, the AIN layer 108 was not completely etched away. However, should a portion of the AIN layer 212 be completely etched through to the third layer 210 as shown in Fig. 21, the substrate layers located beneath the AIN layer 212 will not be affected by the AZ-400 solution. In this second embodiment, the third layer 210 preferably comprises GaN. GaN is insoluble in AZ-400 and effectively acts as an etch stop, preventing the AZ-400 from damaging the layers located under the AIN layer 212. A gate 230 is then deposited in the non-planar gate region 228 as shown in Fig. 2m. The gate 230 is preferably T-shaped to help reduce intrinsic resistance and capacitance. Fabricating a T-shaped structure is a technique well-known in the art.
Because the first layer 204 and the second layer 206 are comprised of group III-V materials, the interface 208 between the first layer 204 and the second layer 206 already contains carrier charges due to the well-known effects of spontaneous polarization. In this way, the interface 208 acts as a channel for the transistor without requiring any additional doping. However, additional doping can be provided, if desired. When the transistor is biased with a voltage at the gate 230 and at either of the ohmic contact regions 223, the charges at the interface 208 flow between the ohmic contact regions 223, allowing operation of the non-planar heterostructure field effect transistor.
Third Embodiment
A method for fabricating a non-planar heterostructure field effect transistor according to a third embodiment is described with reference to Figs. 3a-3J. In this embodiment, a substrate 302 is provided as shown in Fig. 3a. The substrate 302 preferably comprises sapphire, silicon carbide, or GaN. Next, a first layer 304 preferably comprising GaN is provided as shown in Fig. 3b, however, other materials such as InN or InGaN could work equally as well. The first layer 304 is deposited, preferably epitaxially, on the substrate 302. A second layer 306 is provided as shown in Fig. 3c. The second layer 306 preferably comprises AlGaN and is deposited, preferably epitaxially, on the first layer 304. By depositing the second layer 306 on the first layer 304, an interface 305 is created. The interface 305 is located where the first layer 304 contacts the second layer 306 and is further discussed later. Next, an AIN layer 308 is deposited, preferably epitaxially on the second layer 306 as shown in Fig. 3d. The AIN layer 308 is preferably no greater than 10 nm thick. Finally, a capping layer 309 preferably comprising GaN, is preferably deposited on the AIN layer 308, followed by a photoresist layer 310 as shown in Fig. 3e. The purpose of the capping layer 309 is to prevent oxidation from forming on the surface of the AIN layer 308 during subsequent processing steps.
Next, the photoresist layer 310 is patterned and removed using techniques well known in the art to create first windows 312, which expose part of the surface of the capping layer 309 as shown in Fig. 3f. Ohmic metal contacts 318 are deposited in the first windows 312 using metal evaporation as shown in Fig. 3g. The ohmic metal contacts 318 can be comprised of a combination of Ti/Al or Ta/Ti/Al, which are deposited in that order and are about 320 nm thick. The ohmic metal contacts 318 are annealed at a temperature in the range of about 600-800° C for about a minute. This allows the ohmic metal contacts 318 to diffuse into the capping layer 309, the AIN layer 308, and the second layer 306, creating an ohmic contact region 319 as shown in Fig. 3h. The ohmic contact region 319 can then be used as a source and a drain.
Next, a portion of the remaining photoresist layer 310 is patterned and removed as shown in Fig. 3i using techniques well-known in the art, to create a second window 322. The second window 322 exposes part of the capping layer 309 as shown in Fig. 3i. The exposed portion of the capping layer 309 is removed using a reactive ion etch preferably with chlorine gas at an etch rate of about 72nm/min. Etching away a portion of the capping layer 309 exposes a portion of the surface of the AIN layer 308 as shown in Fig. 3j, however the reactive ion etching does not remove any significant portion of the AIN layer 308. The AIN layer 308 effectively acts as an etch stop to the reactive ion etching, thereby preventing the reactive ion etch from damaging the first or second layers 304, 306 beneath the AIN layer 308. It is possible though, for the exposed portion of the surface of the AIN layer 308 to incur damage caused by the reactive ion etch. Also, the remaining portion of the photoresist layer 310 is removed using techniques known in the art. Next, using the remaining portion of the capping layer 309 as a mask, a portion of the exposed AIN layer 308 is etched away with a solvent to create a non-planar gate region 324 as shown in Fig. 3k. The solvent preferably comprises potassium hydroxide (KOH), water, and potassium borates, and is sold under the tradename AZ-400 by the Clariant Corporation of Somerville, NJ. Etching the AIN layer 308 also helps removes any surface damage on the AIN layer 308 caused by the reactive ion etching of the capping layer 309. As shown in Fig. 3k, the non-planar gate region 324 is created by completely etching a portion of the AIN layer 308 through to the second layer 306. However, this embodiment would work if the AIN layer 308 was not completely etched away as shown in Fig. lj of the first embodiment. In the first embodiment the AIN layer 108 was not completely etched away. However, should the AIN layer 308 be completely etched through to the second layer 306 as shown in Fig. 3k, the layers located beneath the AIN layer 308 will not be affected by the AZ-400 solution. In this third embodiment, the second layer 306 preferably comprises AlGaN. AlGaN is insoluble in AZ-400 and effectively acts as an etch stop, preventing the AZ-400 from damaging the layers located under the AIN layer 308 should a portion of the AIN layer 308 be completely etched through to the second layer 306.
A gate 326 is deposited in the non-planar gate region 324 as shown in Fig. 31. The gate 326 is preferably T-shaped in order to help reduce intrinsic resistance and capacitance. Fabricating a T-shaped structure is a technique well-known in the art. Because the first layer 304 and second layer 306 are comprised of group III-V materials, the interface 305 between the first layer 304 and second layer 306 already contains carrier charges due to the well-known effects of spontaneous polarization. In this way, the interface 305 acts as a channel for the transistor without requiring any additional doping. However, additional doping of the transistor can be provided, if desired. When the transistor is biased with a voltage at the gate 326 and at either of the ohmic contact regions 319, the charges at the interface 305 flow between the ohmic contact regions 319, allowing operation of the non-planar heterostructure field effect transistor.
Let it be understood that the foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the spirit of the invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances which fall within the scope of the appended claims.

Claims

ClaimsWhat is claimed is:
1. A method for fabricating a non-planar nitride-based semiconductor structure, the method comprising the steps of: providing a substrate; providing an AIN layer; providing at least one layer of semiconductor material, the at least one layer being disposed between the substrate and the AIN layer; and removing a portion of the AIN layer by exposing the portion of the AIN layer to a solvent, thereby creating a non-planar region in the AIN layer, wherein the at least one layer of semiconductor material is insoluble in the solvent.
2. The method of claim 1 , further comprising the steps of: depositing a capping layer comprising GaN on the AIN layer; and removing a portion of the capping layer preferably using reactive ion etching to expose the portion of the AIN layer, thereby creating a mask for the step of removing a portion of the AIN layer, wherein the reactive ion etching does not remove the portion of the AIN layer thereby protecting the at least one layer of semiconductor material, and wherein the step of removing a portion of the AIN layer removes any surface damage to the AIN layer.
3. The method of claims 1 or 2, wherein the substrate comprises a material selected from the group consisting of sapphire, silicon carbide, and GaN.
4. The method of claims 1 or 2 wherein the AIN layer is no greater than 10 nanometers thick and is deposited epitaxially.
5. The method of claims 1 or 2, further comprising the step of depositing a gate in the non- planar region.
6. The method of claims 1 or 2, wherein the solvent is a potassium hydroxide based solvent.
7. The method of claim 6, wherein the potassium hydroxide based solvent includes potassium borates and water.
8. The method of claim 2, further comprising the steps of: depositing ohmic metal contacts on the capping layer; and heating the ohmic metal contacts, thereby diffusing the ohmic metal contacts into the capping layer and the AIN layer.
9. The method of claim 8, wherein the step of providing at least one layer comprises the step of epitaxially depositing a first layer comprising GaN.
10. The method of claim 9, wherein an active channel is located at an interface of the AIN layer and the first layer.
11. The method of claim 9, wherein the step of providing at least one layer further comprises the step of forming a second layer comprising AlGaN, the second layer being disposed between the first layer and the AIN layer, the second layer being preferably formed by expitaxial deposition.
12. The method of claim 11 , wherein the step of depositing a second layer creates an active channel, the active channel being located at an interface of the first layer and the second layer.
13. The method of claim 11, wherein the step of diffusing the ohmic metal contacts into the capping layer and AIN layer further comprises the step of diffusing the ohmic metal contacts into the second layer.
14. The method of claim 11, wherein the step of providing at least one layer further comprises the step of forming a third layer comprising GaN, the third layer being disposed between the second layer and the AIN layer and preferably being formed by epitaxial deposition.
15. The method of claim 14, wherein the step of diffusing the ohmic metal contacts further comprises the step of diffusing the ohmic metal contacts into the second layer and the third layer.
16. A non-planar nitride-based semiconductor structure comprising: a substrate; a layer of AIN having a non-planar region; and at least one layer of semiconductor material, the at least one layer being located between the substrate and the AIN layer.
17. The semiconductor structure of claim 16, wherein (he substrate comprises a material selected from the group consisting of sapphire, silicon carbide, and GaN.
18. The semiconductor structure of claim 16, further comprising a capping layer comprising GaN on a portion of the AIN layer, thereby creating a mask to expose a portion of the AIN layer.
19. The semiconductor structure of claim 16, wherein the AIN layer is no greater than 10 nanometers thick, and is deposited epitaxially.
20. The semiconductor structure of claim 16, further comprising a gate in the non- planar region.
21. The semiconductor structure of claim 18, wherein the solvent is a potassium hydroxide based solvent.
22. The semiconductor structure of claim 21 , wherein the potassium hydroxide based solvent further comprises potassium borates and water.
23. The semiconductor structure of claim 21 , further comprising ohmic metal contacts diffused into the capping layer and the AIN layer.
24. The semiconductor structure of claim 23, wherein the at least one layer comprises an epitaxially deposited first layer comprising GaN.
25. The semiconductor structure of claim 24, further comprising an active channel, the active channel being located at an interface of the AIN layer and the first layer.
26. The semiconductor structure of claim 24, wherein the at least one layer further comprises an epitaxially deposited second layer comprising AlGaN, the second layer being disposed between the first layer and the AIN layer.
27. The semiconductor structure of claim 26, further comprising an active channel, the active channel being located at the interface of the first layer and the second layer.
28. The semiconductor structure of claim 26, wherein the ohmic metal contacts are diffused in the capping layer, the AIN layer, and the second layer.
29. The semiconductor structure of claim 26, wherein the at least one layer further comprises an epitaxially deposited third layer comprising GaN, the third layer being disposed between the second layer and the AIN layer.
30. The semiconductor structure of claim 29, wherein the ohmic metal contacts are diffused in the capping layer, the AIN layer, the second layer, and the third layer.
31. The semiconductor structure of claim 16, wherein the at least one layer is insoluble in a solvent used to form the non-planar region.
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