JPH0758060A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the characteristics of field effect transistors(FET) by adopting a three layer structure for dummy gates under which matching between an FET gate electrode and an ion-implanted region is carried out based on a self-alignment method. CONSTITUTION:A dummy gate, which is required to perform matching 5 between a gate electrode 13 of FET and an ion-implanted region based on a self- alignment method, is designed under three layer structure which comprises a first layer insulating film 1, a second insulating film 2 and a third layer insulating film 3. The requirements for the etch rate of the insulating films under the three layer structure are specified to satisfy the following. The first layer insulating film is < the second layer insulating film 2 while the second layer insulating film 2 is < the third layer insulating film. When etching is carried out between the second layer insulating film 2 and the third layer insulating film 3 and between the first layer insulating film 1 and the second layer insulating film 2, the first layer insulating film 1 serves as an etching stopper respectively. This construction makes it possible to enhance the characteristics of FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a Schottky junction field effect transistor.

[0002]

2. Description of the Related Art Conventionally, in order to improve the characteristics of FETs and increase the integration density of semiconductor integrated circuit devices including FETs,
Ion implantation is performed using the gate electrode as a mask, and heat treatment is performed on this to perform self-alignment (self-alignment).
ignment) method is commonly practiced.

Heat treatment after ion implantation by the self-alignment method for a GaAs Schottky gate FET requires a temperature of about 850 ° C., but molybdenum (Mo), tungsten (W), etc. are used as the gate electrode material. In such a case, in this heat treatment, these metals react with GaAs, the Schottky barrier is destroyed, and the FET cannot be realized. As a material that does not cause this reaction, there is Ti / W silicide, but this material has a high resistivity and is a serious problem for a GaAs FET that aims for high speed.

In order to solve these problems, Japanese Patent Laid-Open Publication No.
8-60574 and JP-A-60-137070.
In the publication, a self-alignment method using a dummy gate is proposed. In these methods, since the gate is formed after heat treatment, a single-layer or multi-layer gate metal having a desired resistivity can be selected regardless of heat resistance or non-heat resistance.

[0005]

However, these methods have the following problems. That is, JP-A-58-6
In Japanese Patent Publication No. 0574, as shown in FIG. 13, a resist or a metal film 2 is formed on an insulating film to be a dummy gate.
After forming 7, the unnecessary portion is etched by reactive ion etching (RIE) using them as a mask, and then the side wall of the insulating film is etched by isotropic etching to form a dummy gate 26. The amount of etching determines the distance between the gate edge and the N ⁺ edge.
The insulating film is etched up to the GaAs surface with, and isotropic etching is performed with the GaAs surface exposed.
Damage to the GaAs surface by E is a major issue. Further, by the completion of the dummy gate, film formation by CVD or the like, R
Etching by IE and isotropic etching, and 3
Need a process.

Further, in JP-A-60-137070, as shown in FIG. 14, after forming an insulating film 37 having a different etching rate on a dummy gate made of the insulating film 36, the sidewall of the dummy gate is formed. Only, the insulating film 37 is left by RIE or the like, and the thickness of this side wall is equal to that of the gate end and N.
^This is a method to determine the ⁺ edge distance, but RIE is used to
Not only when the insulating film 36 is etched to the surface,
Even when the side wall made of the insulating film 37 is left, the GaAs surface is exposed to the RIE, so that the damage of the GaAs surface due to the RIE becomes a serious problem. In addition, by the completion of the dummy gate, film formation by CVD, etching by RIE,
A side wall film formation by CVD or the like and etching by RIE or the like and four steps are also required. After that, even when the dummy gate is inverted to the resist pattern, RIE is performed.
When the dummy gate is etched by, the overetching must be performed due to the nonuniformity of etching, and the GaAs surface at the gate junction portion is damaged by RIE, which is also a problem. Therefore, the present invention
When the self-alignment method is used to align the gate electrode of the FET with the ion implantation region, the structure of the dummy gate is a three-layer insulating film structure. Among the three-layer insulating film structure, a one-layer insulating film and a two-layer insulating film, By using the etching conditions in which the upper layer has a higher etching rate than the lower layer for the two-layer insulating film and the three-layer insulating film, the GaAs surface is not damaged during the dummy gate etching process, and therefore the characteristics are improved. Another object of the present invention is to provide a method of manufacturing a semiconductor device.

[0007]

The present invention comprises the following steps. 1. a step of forming a first layer insulating film, a second layer insulating film and a third layer insulating film having the following etching conditions on the compound semiconductor substrate, and an etching rate of the first layer insulating film < Second layer insulating film etching rate,
Etching rate of second layer insulating film <Etching rate of third layer insulating film 2, Etching second layer insulating film other than dummy gate and third layer insulating film using second layer insulating film as an etching stopper A step of forming a gate, 3, a step of ion-implanting an N-type impurity into a compound semiconductor substrate using the dummy gate as a mask, and 4, a step of using the injected N-type impurity as a first-layer insulating film as a protective film A heat treatment and activation to form an N-type layer; a step of forming a resist around the dummy gate; and a step of etching a third layer insulating film of the dummy gate. , 7, a step of removing the etching residue of the third-layer insulating film by lift-off when etching the second-layer insulating film of the dummy gate, and 8, the bottom layer of the dummy gate. And a step of forming a gate opening by removing the single-layer insulating film by etching so as not to damage the surface of the compound semiconductor substrate; and a step of forming a gate electrode in the gate opening. A method for manufacturing a featured semiconductor device.

[0008]

The dummy gate has a three-layer structure including the first-layer insulating film, the second-layer insulating film, and the third-layer insulating film, and the first-layer insulating film is provided between the insulating films having the three-layer structure as an etching rate condition. Insulating film <second layer insulating film, second layer insulating film <third layer insulating film,
Therefore, the second layer insulating film is used when etching the second layer insulating film and the third layer insulating film, and the first layer insulating film is used when etching the first layer insulating film and the second layer insulating film. But,
Each will act as an etching stopper. Further, when the dummy gate is inverted into the resist pattern, the etching residue of the third-layer insulating film can be removed by lift-off during the etching of the second-layer insulating film.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. As shown in FIG. 1, on a semi-insulating GaAs substrate 10, a resist mask 4 is provided, for example, the Si at ^{150keV, 5 × 10 1 2 cm} - 2 degree injection to form an injection layer 5.

After removing the resist mask 4, FIG.
As shown in FIG. 1, a first layer silicon nitride (SiNx) film 1 for protecting the GaAs substrate 10 is formed to a thickness of 100 by a CVD method or the like.
It is formed to have a thickness of about nm. Then, the second layer silicon oxide (SiO ₂ ) film 2 is formed to a thickness of about 50 nm by the CVD method or the like. Next, the third layer silicon nitride (SiN
x) The film 3 is formed to have a thickness of about 500 nm. These first-layer insulating film, second-layer insulating film, and third-layer insulating film have etching rates of first-layer insulating film <second-layer insulating film, and second-layer insulating film <third-layer insulating film, It is made of a material having the following etching conditions.

As shown in FIG. 3, a pattern 6 made of a resist or a metal film is formed on the insulating film to be the dummy gate.
Are formed by an ordinary lithography method.

At this time, as shown in FIG. 4, the third layer Si
When the RIE conditions are set so that the etching rate of the Nx film 3 is several times as high as the etching rate of the second layer SiO ₂ film 2, the interface between the second layer and the third layer is perpendicular to the substrate 10. In this direction, the second layer SiO ₂ film 2 serves as an etching stopper and the etching does not proceed so much.
The etching of the third-layer SiNx film 3 progresses in the direction parallel to. The gate length is controlled by the etching amount in the parallel direction. After that, the exposed portion of the second layer SiO ₂ film 2 is wet-etched with a mixed solution of hydrogen fluoride (HF) and ammonium fluoride (NH ₄ F) or dry-etched by RIE or the like.

As shown in FIG. 5, ion implantation is performed to form the source region 7 and the drain region 8. That is, after providing the resist mask 9, the second layer SiO ₂ film 2 and the third layer 3
Using the dummy gate formed of the layer SiNx film 3 and the resist mask 9 as a mask, 1 × 10 at about 300 keV
^{1 4} cm ^{- two} approximately infusion.

As shown in FIG. 6, after the pattern 6 and the mask 9 are removed, heat treatment is performed using the first-layer SiNx film 1 as a protective film.

Next, as shown in FIG. 7, patterning is performed by a conventional lithography method to form a source electrode 7a and a drain electrode 8a.

Next, as shown in FIG. 8, the resist on the dummy gate is removed by an etch back method, and a resist 9 is formed around the dummy gate.

Thereafter, as shown in FIG. 9, the third-layer SiNx film 3, the second-layer SiO ₂ film 2 and the first-layer SiNx film 1 immediately below the third-layer SiNx film 3 forming the dummy gate are removed. In this etching of the dummy gate, the third layer SiNx film 3
Etching is performed under the etching conditions in which the etching rate is about several times the etching rate of the second layer SiO ₂ film 2. The etching of the third-layer SiNx film 3 is performed by using RIE in consideration of controllability. Depending on the RIE conditions, the residue 3a of the third-layer SiNx film 3 may remain.

Next, as shown in FIG. 10, the second layer SiO 2
₂ Etching is performed under the etching condition that the etching rate of the film 2 is about several times the etching rate of the first-layer SiNx film 1. The etching of the second layer SiO ₂ film 2 is performed by using hydrogen fluoride (HF) and ammonium fluoride (NH).
₄ F) and mixed solution. Then, the second layer Si
Along with the O ₂ film 2, the residue 3a of the third layer is lifted off.
Are also peeled off together, and the surface of the first layer SiNx film 1 appears.
Then, the first layer SiNx film 1 is etched under the condition that the GaAs surface is not damaged. The etching of the first layer SiNx film 1 may be wet etching using a mixed solution of hydrogen fluoride (HF) and ammonium fluoride (NH ₄ F), but in consideration of controllability of the gate length, dry etching by RIE or the like is performed. Etching is preferred.

Next, as shown in FIG. 11, after patterning the resist 11 by a conventional lithography method,
The conductor layer 12 forming the gate electrode is formed by vapor deposition, sputtering or the like. This conductor layer 12 is made of gold (A
u), a single layer structure of aluminum (Al), or gold-germanium / nickel / gold (Au-Ge / Ni / Au)
It is possible to select a multilayer structure such as.

After that, as shown in FIG. 12, a gate electrode 13 is obtained by a normal lift-off method.

As described above, in the present invention,
A dummy gate is formed of an insulator having a different etching rate, the second layer insulating film serves as an etching stopper in the vertical direction of the substrate, and the third layer insulating film is etched only in the parallel direction of the substrate to obtain the gate length and the gate edge. And the distance between the N ⁺ region edges can be determined. Also, the dummy gate is C
The process is completed in two steps: film formation by VD or the like and etching by RIE or the like. By combining dry etching and wet etching when reversing the dummy gate into a resist pattern, damage to the GaAs surface is reduced.

In the above embodiment, GaAs is used.
Although the MESFET is shown, the present invention can be applied to HEMT or other compound semiconductor device.

In the above embodiment, the SiNx / SiO ₂ / SiNx structure is used as the three-layer insulating film, but the first layer can be used as a protective film for heat treatment and the second layer can be used. Any combination may be used as long as it has a three-layer structure in which the etching rate of the third layer is several times or more than the etching rate of.

[0024]

The present invention has the following effects. By using the second layer film as an etching stopper when dry etching the first and third layer films, it is possible to improve the uniformity of the dummy gate formation etching process within the wafer.

2. Since the etching in the vertical direction does not proceed and the etching in the lateral direction proceeds, side etching of the dummy gate can be simultaneously performed by one dry etching, and the etching process can be simplified.

3. The gate length can be determined only by the amount of etching in the lateral direction.

4. Since the first layer film and the second layer film protect the substrate when the dummy gate is formed by dry etching, damage to the substrate due to dry etching can be prevented.

5. After ion implantation through the first layer film,
Activation annealing can be performed without newly forming a protection film for annealing.

6. In the step of reversing the dummy gate into the resist pattern, the third layer film portion is removed by dry etching until the second layer film portion appears, and the second layer film portion is removed by wet etching. The remaining portions of the third layer film portion can be removed together by lift-off, and the controllability of the dummy gate etching can be improved.

7. Since the second layer film portion and the third layer film portion of the dummy gate can be removed with good controllability, the amount of over-etching of the first layer film portion can be reduced and damage to the substrate due to etching can be reduced. You can

[Brief description of drawings]

FIG. 1 Process diagram for implanting Si into a GaAs substrate

FIG. 2 is a first-layer SiNx film serving as a dummy gate, a second layer
Process diagram for forming a three-layer structure including a three-layer SiO ₂ film and a third-layer SiNx film

FIG. 3 is a process drawing of forming a pattern on an insulating film to be a dummy gate

FIG. 4 is a process diagram of etching away parts other than the second-layer SiO ₂ film and the third-layer SiNx film, which will be dummy gates.

FIG. 5 is a process diagram of ion implantation for forming a source region and a drain region.

FIG. 6 is a process diagram of heat treatment using the first-layer SiNx film as a protective film.

FIG. 7 is a process drawing of forming a source electrode and a drain electrode.

FIG. 8 is a process diagram of forming a resist for reversing a dummy gate.

FIG. 9 is a process diagram of etching and removing the dummy gate

FIG. 10 is the bottom layer of the dummy gate, the first layer SiN.
Process drawing for removing x film

FIG. 11 is a process drawing of forming a conductor layer to be a gate electrode.

FIG. 12 is a process diagram of forming a gate electrode by lifting off a resist.

FIG. 13 is a process chart of a conventional example

FIG. 14 is a process diagram of another conventional example

[Explanation of symbols]

1 1st layer SiNx film 2 2nd layer SiO ₂ film 3 3rd layer SiNx film 4 resist mask 5 injection layer 6 pattern 7 source region 8 drain region 9, 11 resist 10 GaAs substrate 12 conductive layer 13 gate electrode

Claims (1)

[Claims] 1. A step of forming a first-layer insulating film, a second-layer insulating film and a third-layer insulating film having the following etching conditions with respect to an etching rate on a compound semiconductor substrate, and a first-layer insulating film. Film etching rate <second layer insulating film etching rate, second layer insulating film etching rate <third layer insulating film etching rate 2, second layer other than dummy gate using second layer insulating film as an etching stopper Etching the insulating film and the third-layer insulating film to form a dummy gate; 3, implanting N-type impurities into the compound semiconductor substrate using the dummy gate as a mask, 4, implanting A step of heat-treating and activating the N-type impurity using the first-layer insulating film as a protective film to form an N-type layer; and a step of forming a resist around the dummy gate. 6, a step of etching the third layer insulating film of the dummy gate, and 7, when etching the second layer insulating film of the dummy gate, removing etching residues of the third layer insulating film by lift-off. And a step of forming a lowermost first layer insulating film of the dummy gate,
A semiconductor device comprising: a step of etching and removing a gate opening so as not to damage the surface of the compound semiconductor substrate; and a step of forming a gate electrode in the gate opening. Manufacturing method.