WO2004017288A2

WO2004017288A2 - Multi-panel liquid crystal display systems

Info

Publication number: WO2004017288A2
Application number: PCT/US2003/025604
Authority: WO
Inventors: Howard V. Goetz; Philip Odom; Steven H. Linn; David L. Keith
Original assignee: Iljin Diamond Co., Ltd.
Priority date: 2002-08-16
Filing date: 2003-08-15
Publication date: 2004-02-26
Also published as: AU2003262710A1; TW200426768A; AU2003262710A8; WO2004017288A3

Abstract

Display controllers for multi-panel LCDs (202, 204, 206) include row scanners (208) associated with red, green, and blue image color components. The row scanners are configured to scan a row, a set of rows, or all rows of a panel associated with a selected color component, and then scan corresponding rows, sets of rows, or all rows of panels associated with additional color components. The display controller can be configured to store and retrieve color component data using a row buffer or a frame buffer. Column drivers can be configured to drive a set of column scanners (210) associated with display rows for all color components, or to drive separate sets of column scanners (210).

Description

MULTI-PANEL LIQUID CRYSTAL DISPLAY SYSTEMS

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application 60/403,974, filed August 16, 2002, and which is incorporated herein by reference.

TECHNICAL FIELD

The disclosure pertains to liquid crystal displays.

BACKGROUND

Transmission-mode active-matrix polysilicon LCD modules for projection applications have traditionally been designed using one of two different electronics architectures. The first architecture involves driving the columns of the display directly with an external integrated circuit. The other architecture is referred to as "Line Scan Sample and Hold" (LSSH). This is an indirect drive method in which one row of data at a time is written to and buffered in the display, and during the next row time the buffered data is used to update a row of display pixels.

Both systems have advantages and disadvantages. The first architecture is simpler, and generally requires somewhat simpler external drive electronics. However, such displays exhibit image quality limitations, and the speed at which data can be written to the columns and pixels is limited. To overcome this speed limitation, several parallel data lines are used so that several pixels of the display can be written at once. For example, an SVGA (800 x 600) display typically uses six data channels driven with a single custom integrated circuit. Even with six parallel data channels, such displays are operating at their speed limit. These displays cannot be operated at higher frame rates, such as 75 Hz, even though such frame rates may be desirable. Higher resolution displays require still more parallel data channels, and require additional IC drivers. In particular, an XGA (1024 x 768) display requires two ICs per display. A 3-color system using these displays requires six IC driver chips. These IC drivers cost several dollars each, and the total cost of six of them is considerable in cost sensitive applications.

LSSH-based displays generally require drive electronics that are slightly more complicated because both Ramp and DataRamp signals must be supplied in addition to normal control signals. FIG. 13 is a schematic view of a portion of an LSSH display. Such displays are capable of high data rates due to the internal row buffer in the display that permits an entire row time to be used to charge a row of pixels to intended voltages. While LSSH drive electronics can be based on one or more data channels, some LSSH systems have been built based on eight parallel data channels. Systems using eight data channels generally have wide timing margins, and are capable of high speed operation. For example, such LSSH systems can operate at 75 Hz or 85 Hz frame rates. Drive chips are available that can drive XGA as well as SVGA displays, based on eight parallel data channels.

However, systems using more than one display (such as 3-color projectors) typically require one such drive chip per display. These multiple chips increase the cost of the display. Therefore, improved display methods and apparatus are needed.

SUMMARY

Display controllers comprise an input configured to receive an image signal that includes image data associated with at least a first color component and a second color component. A processor is configured to store at least one row of image data in a memory. A display driver is configured to direct the image data associated with the first color component to a first image data output and image data associated with the second color component to a second image data output. In additional examples, a data ramp generator is configured to produce a first dataramp associated with the first color component and a second dataramp associated with the second color component. In further representative examples, the data ramp generator is configured to deliver the first data ramp to a first output associated with the first color component and the second data ramp to a second output associated with the second color component. In other examples, the data ramp generator is configured to deliver the first data ramp and the second data ramp to a common output. In additional representative examples, the at least one row of image data stored by the processor includes image data for a plurality of rows. In other examples, the at least one row of image data stored by the processor includes a frame of image data.

Display systems comprise a display panel that includes pixel arrays associated with a red color component, a green color component, and a blue color component, and a row scanner configured to scan the red, green, and blue pixel arrays. In representative examples, the row scanner is configured to sequentially scan the row lines of the pixel arrays. In additional examples, the row scanner includes scanner sections associated with the red color component, the green color component, and the blue color component, and the scanner sections include a scan enable input configured to initiate row scanning. In further representative examples, a display driver is configured to receive a video signal and distribute color image data for the red color component, the green color component, and the blue color component to the respective pixel arrays. In other examples, a memory is configured to store image values for a row of each of the pixel arrays. In illustrative examples, the memory is configured to store image values for a plurality of rows of each of the pixel arrays. In further examples, the display driver is configured to receive and store image data for a row of pixels in a row time, and distribute stored images values for a row of at least one of the color components in about one-third of the row time. In other representative examples, the memory is configured to store image values for at least two rows of each of the pixel arrays.

Display systems comprise display panels associated with a red color component, a green color component, and a blue color component. Each of the display panels includes a row scanner. A display controller is configured to deliver red, green, and blue color component image data, and red, green, and blue scan enable signals to the respective display panels. In additional examples, the display controller is configured to provide red, green, and blue data ramp signals to the respective display panels, wherein at least one of the red, green, and blue dataramp signals is unique. Display methods comprise receiving a video signal and storing image data associated with at least one row of image data for a red color component, a green color component, and a blue color component. The stored image data is retrieved, and the stored image data is delivered to first, second, and third displays so that the red color component image data is delivered to a first display, the green color component data is delivered to a second display, and the blue color component data is delivered to a third display. The first, second, and third displays include rows of pixels, and the red, green, and blue color component data are scanned into rows of the respective displays. In representative examples, the sequential scanning is based on scanning all the rows associated with a selected color component prior to scanning the rows associated with the unselected color components. In additional representative examples, the row of image data is received in a row time, and the image data associated with at least one of the color components is delivered to an associated display in about one-third of the row time. In additional examples, data ramp signals are supplied to the displays based on the associated color component. These and other features and advantages are described below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of a single panel, full color liquid crystal light valve (LCLV). FIG. IB is a schematic diagram illustrating an arrangement of row and column conductors for the LCLV of FIG. 1 A.

FIG. 2 is a schematic diagram of a single panel, multiple subpanel, full color display. FIG. 3 is a block diagram of a display driver for the display of FIG. 2.

FIG. 4 illustrates signal timings for various signals associated with writing image data to the display of FIG. 2.

FIG. 5 is a schematic diagram of a single panel, multiple subpanel, full color display configured for segmented row scanning. FIG. 6 is a block diagram of a display driver for the display of FIG. 5.

FIG. 7 is a schematic diagram of a display system that includes three separate, vertically-stacked panels associated with red, green, and blue image signal components.

FIG. 8 illustrates signal timings for various signals associated with the display system of FIG. 7. FIG. 9 is a schematic diagram of a single panel display configured to receive a scan enable signal.

FIG. 10 is a block diagram of a display driver for the display of FIG. 9.

FIG. 11 is a schematic diagram of a single panel display configured to scan image data associated with a selected color component while additional panels scan image data associated with other color components.

FIG. 12 is a block diagram of a display driver for the display of FIG. 11.

FIG. 13 illustrates a portion of a line scan, sample and hold (LSSH) display.

DETAILED DESCRIPTION Combinations of three separate LCDs ("panels") or a single LCD on which sub- regions ("subpanels" or "sub-arrays") associated with red, green, and blue color components are defined can be used to form full color display systems. Various optical systems can be used to recombine color components after modulation of color component illumination beams by the separate LCDs or the subpanels to form full color images. These combinations of panels or subpanels can be driven as a single display unit with a single set of control lines and data channels, using a single integrated circuit driver. Additional control signals can be generated to control data flow to the panels or subpanels, and typically panels and subpanels in such systems receive image data at higher data rates than if operated separately. So-called line scan, sample and hold ("LSSH") LCDs can generally be operated at such data rates with some manipulation and/or buffering of incoming image data. Several example drive methods and apparatus for 3-panel and 3-subpanel displays are described below. These examples can be adapted to groups of other than three panels/subpanels, and to groups of displays of differing sizes, orientations, and alignments.

Example 1. 3-Subpanel LCD

With reference to FIG. 1 A, a full-color, single-panel liquid crystal light valve (LCLV) 101 includes red, green, and blue pixel arrays 102, 104, 106 defined on a substrate 107. This ordering of red, green, and blue pixel arrays is shown for purposes of illustration, and other orders can be used. The association of the pixel arrays of FIG. 1 A with particular color components is arbitrary, as color components are typically configured based on an optical system that is not shown in FIG. 1 A. However, for convenience, the pixel arrays are referred to based on color components.

As shown in FIG. 1A, the pixel arrays include 480 rows and 864 columns of pixels. Pixel pitches of the arrays can vary, or a common pixel pitch can be used. The pixel arrays are separated by intermediate regions 112 that typically include metallization for conductors used in writing images to the LCLV 101. For example, column conductors can extend through the intermediate regions 112. The single-panel LCLV 101 can be referred to as a display panel, and the pixel arrays can be referred to as subpanels. In one example, the substrate 107 is about 20 mm by 32 mm and each of the subpanels is about 15.55 mm by 8.64 mm (17.8 mm diagonal). The pixel arrays 102, 104, 106 are typically formed based on a high temperature polysilicon process.

The LCLV 101 includes a row scan region 108 that is typically used to provide row select signals so that pixels of a selected row can be written with appropriate image values. A single backplane conductor 110 is provided, but separate backplane conductors can be provided for each of the pixel arrays 102, 104, 106. In an example, the LCLV 101 is based on a so-called line scan sample and hold (LSSH) design in which image values for all pixels in a row are established based on sampled input image values that are delivered to respective column comparators that control application of a data ramp signal to the pixels using column FETs. Such systems are described in, for example, U.S. Patent Application Publication 2002/0149557, U.S. Patent Application Publication 2002/0196264, and a portion of such a system is illustrated in FIG. 13.

With reference to FIG. IB, the subpanels 102, 104, 106 are configured to be addressed using a set 120 of column conductors or column lines. Respective sets 122, 124, 126 of row conductors (row lines) are provided for the subpanels 102, 104, 106. For convenience, only a few such conductors are shown in FIG. IB. As is apparent, the set 120 of column conductors (column lines) is configured to address all three subpanels, but separate sets of row conductors (row lines) are provided. In other arrangements, a common set of row conductors and separate sets of column conductors can be provided.

As shown in FIG. 1 A, column lines extend continuously from the top of the red subpanel 102 through the green subpanel 104 to the bottom of the blue subpanel 106. Each can be driven by one of two banks of LSSH circuitry. Several exemplary drive methods and apparatus, and row scanner configurations are described below.

The subpanels can be configured in other arrangements. For example, red, green, and blue subpanels can be stacked vertically as in FIG. 1 A, horizontally, or in a triangular or other arrangement. Two panes can be arranged horizontally and a third vertically. The subpanels can have differing sizes and shapes. In such arrangements, some or all column conductors or row conductors are configured to be shared by two or more of the subpanels so that, for example, column one of all subpanels can be addressed using a common column line. Specific details associated with driving such configurations, e.g., timing, line buffering, data rates, can vary, but one or more of the representative methods described herein permits all three subpanels to be driven with a common drive circuit.

Method 1; 3-Subpanel LCD with Sequential Scanning

With reference to FIG. 2, a display panel 200 includes subpanels 202, 204, 206 associated with red (R), green (G,) and blue (B) color components, respectively. A row scanner 208 is configured to select pixel rows, typically by controlling pixel transistors associated with each pixel. A column scanner 210 is configured to deliver image signals to the column lines, typically by controlling application of a data ramp signal to each column line. The display system 200 includes 1440 rows, and 864 columns of pixels (3 sets of 480 rows by 864 columns) such as a representative pixel 212 that includes a pixel transistor 213 and pixel electrode 214. Image signals are delivered to the pixel 212 using a column line 230 and a row line 232. For simplicity, only a few pixels, row lines, and column lines are shown in FIG. 2, and pixel capacitors and other details are omitted. The row scanner 208 includes red, green, and blue subregions 240, 242, 244, and gaps 216, 218 correspond to gaps between the subpanels 202, 204, 206. Scanner interconnects 250, 252 connect the row scanner subregions 240, 242 and 242, 244, respectively, so that the row scanner 208 is electrically continuous. A data ramp input 224 is used to deliver a data ramp waveform to the pixels. Each color component can be associated with a color-component specific data ramp waveform delivered to the data ramp input 224. A set 260 of eight data lines is used to deliver image data to respective sets of column conductors. More or fewer data lines can be used. In addition, four DCLCK signals (DCLK1-4) are provided.

Image data is transferred to the pixels from the column lines as controlled by the row scanner 208. The row scanner 208 scans the rows of the R-subpanel from top to bottom. After a last (bottom-most) row 220 of the R-subpanel 202 is scanned, the row scanner 208 scans rows of the G-subpanel 204 from top to bottom, starting at a first row 222. When scanning of the G-subpanel 204 is complete, the row scanner 208 scans rows of the B-subpanel 206. Such row scanning is thus similar to scanning of a single 864-column by 1440-row display. Such scanning can be referred to as sequential. However, rows need not be scanned in order from top to bottom. Scanning of the subpanels can be from bottom to top, and subpanels can be selected for scanning in orders other than red, green, blue. In other systems, column lines can be used to scan the columns, and scanning can proceed from left to right, right to left, or in other orders. Such scanning systems typically scan all pixels associated with a selected color component before scanning pixels associated with other color components.

Row scanners and column scanners for such displays must be configured to receive re-ordered image data. Additional, external drive electronics are used to generate control signals, data clocks, etc. at three times an incoming line rate since three display lines (R, G, B) are written for every line of incoming data. Image data is typically re-ordered using, for example, a full frame-buffer. Incoming data is typically presented as 24-bit RGB pixels, and is re-ordered so that, for example, red image data is written to a red component subpanel, after which green image data is written to a green component subpanel, and finally blue image data is written to a blue component subpanel, completing the writing process for an image frame. Thus, while data for a selected image color is written to a subpanel, data for other color components is stored in the frame buffer for subsequent scanning to the display.

FIG. 3 is a block diagram of a display system 300 that includes a 3-subpanel LCD 302 configured for sequential row scanning. A display controller 304, typically implemented in a gate array, is configured to receive a video signal at a video input 316, typically as an LVDS signal. RGB data, clock (CLK), horizontal synch (HS), and vertical synch (VS) inputs are provided. The controller 304 provides 8-bit timing data (Timing/8) to the display 302 and 16-bit video (Video/16) to a video processor 305 that provides image data to the display 302. Non-volatile memory (NVRAM) 310 is also provided as well as an EC control input 311. A frame buffer 320 is also provided. The display controller 304 re-orders incoming data into separate red, green, and blue component data for storage in the frame buffer 320. The display controller 304 also includes logic configured to retrieve stored data and deliver the data to the video processor 305 in, for example, two 16-bit words corresponding to adjacent pixels. Every 4 clock cycles, the video processor 305 updates internal A-D converters, and 8 new analog values appear at outputs 340. These values are latched into a column scanner by a next incoming DCLK rising edge. A clock signal, shift enables, and update enables delivered to the video processor 305 are included in signals denoted "Control 17" in FIG. 3. The control signals are managed by the display controller 304 based on the horizontal synch (HS) and the vertical synch (VS) signals associated with incoming video. Ramp and DataRamp signals are also synthesized in the display controller 304. A Ramp section of the video processor 305 converts the Ramp and DataRamp signals to analog values, and delivers these signals to a buffer 324 for delivery to the LCD 302. The video processor 305 also produces a backplane voltage V_common, but this is not shown in FIG. 3. Using standard 480 line timing for an 864 x 480 display, incoming row times are

31.78 μs. During an incoming row time, 3 rows of pixels are written to the display 302. In a representative example, image values are written to the columns eight at a time. Therefore, (3 x 864) / 8 = 324 video processor update cycles are needed. If each update cycle takes 4 clocks cycles, 1296 clock cycles are needed for each row. For 1296 clock cycles in a 31.78 μs row time, a minimum clock rate to the video processor 305 is about 24.5 ns, or about 41 MHz. An associated DCLK edge rate is about 10 MHz, well within a typical LCD data path capability. A phase-locked loop (PLL) is used to generate a 41 MHz clock from an incoming 30.5 MHz input. A duration of the DataRamp waveform is equal to the display row time (less comparator autozero time), so a maximum DataRamp duration is (31.78 μs/ 3) -4μs, or about 6. 6 μs.

Method 2: 3-Subpanel Display with Segmented Scanning

Row scanners can also be configured to operate as three semi-independent 480-row scanners. With reference to FIG. A, row scan enable signals RSEN, GSEN, and BSEN associated with red, green, and blue color components are shown within a single 31.78 μs row time. A clock signal SCLK and a digital data in signal DD1N are also shown. In this representative row time, a rising edge of the clock SCLK is associated with RSEN becoming positive and enabling a red component row scanner (a scanner "section"). The remaining scan enable signals GSEN, BSEN are low, and the associated scanners are not enabled. With RSEN high, red component image data is scanned to a row of the R- subpanel. RSEN then becomes low, GSEN becomes high, and green image component data is scanned to a row of the G-subpanel. GSEN and RSEN then are both low, and BSEN becomes high so that blue image component data is scanned to the B-subpanel. In this example, external scan control signals (RSEN, GSEN, BSEN) control respective row scanner sections so that a single row each color component is scanned before scanning of a next row begins. After a first row of each subpanel is scanned, respective row pointers are incremented, and this cycle repeats. Row scanners for such displays require control lines to receive signals such as RSEN, GSEN, and BSEN. A full frame buffer in external circuitry is not required because a full row of data can be read into a row buffer in a gate array or an FPGA, so that data is available for writing three rows of the display in R, G, B order as described. A full frame buffer of high-speed memory can be expensive, so that this method can be more cost-effective.

A controller for such a display system typically generates control signals, data clocks, etc. that operate at three times an incoming data rate, because three lines of the physical display (one line per subpanel) are written for every line of incoming data.

FIG. 5 is a schematic block diagram of a portion of such a display. Pixel capacitors and other details are omitted. A row scanner 502 includes scanner sections 540, 542, 544 that are associated with red, green, and blue color components and have associated control inputs 502, 504, 506 (RSEN, GSEN, BSEN, respectively). A single DataRamp input 524 is provided and DataRamp waveforms can be applied that are associated with each color component. For example, red component image data can be scanned using an R-DataRamp waveform. Green and blue image data can be scanned using a G-DataRamp waveform and a B-DataRamp waveform, respectively. Additional control signals are associated with the RSEN, GSEN, BSEN inputs that determine which of the three subpanels is to receive data at any given time. Typically only one of the row scanner sections is enabled at any one at a time.

FIG. 6 is a schematic block diagram of display system 600 configured for single- row segmented scan as described above. A display controller 604 (implemented as, for example, a gate array) is configured to re-order each row of incoming data into separate red, green, and blue line buffers in an internal memory. Logic in the display controller 604 reads out stored data and delivers the data to a video processor 605 in 16-bit words corresponding to two adjacent pixels. Every four clock cycles, the processor 604 updates internal A-D converters. Eight updated analog values are delivered to outputs 340 and are latched into a column scanner at a next incoming DCLK rising edge. The control signals to the LCD are managed by the display controller 604 based on the horizontal synch (HS) and the vertical synch (VS) signals associated with the incoming video signal. Ramp and DataRamp signals are also synthesized in the display controller 604, converted to analog signals by a RAMP section of the video processor 605, and delivered to a buffer 624 before delivery to a display 602. DataRamp and Ramp signals (noted as "12" signals) can be associated with each color component. The video processor 605 also produces a backplane voltage V_common, but this is not shown in FIG. 6.

In some implementations, two line buffers are preferred, so that one line buffer can be written by incoming video while the other line buffer is being read-out to the display. This avoids potential artifacts caused by writing to the memory as it is being read. Total memory for a 2-line buffer for 864 lines and three colors is 864 x 2 x 3 = 5184 bytes.

Example 2. 3-Panel Displays: FIG. 7 is a block diagram of display system 700 that includes a red panel 702, a green panel 704, and a blue panel 706 fixed to a circuit board 701 or other substrate. In an example, each panel includes an array of 864 (H) by 480 (V) pixels, and LSSH column drivers and row scanners. In the example of FIG. 7, the panels 702, 704, 706 are fixed to a common transparent substrate 708 to provide stable alignment. The substrate 708 is fixed to the circuit board 101 and the displays 702, 704, 706 are electrically connected with wire bonds or otherwise electrically connected at respective connection areas 710, 712, 714. An aperture 720 permits light transmission. As noted previously, such panels can be arranged vertically, horizontally, or in other arrangements, and the system 700 is only a representative example.

Method 3. 3-Panel LCDs with Segmented Scanning The individual panels 702, 704, 706 include column and row scanners. In order to drive all three as if they formed a single, larger array, additional decoding video decoding is performed. This decoding typically consists of providing a column scan enable signal and a row scan enable signal to each display. Data is first scanned into a first row of the Red panel 702, with row scanners for the Green and Blue panels 704, 706 disabled. Then, the next row of data is scanned into the first row of the Green panel, with the row scanners for the Red and Blue panels disabled. Next, a row of data is scanned into the first row of the Blue panel with the row scanners for the Red and Green panels disabled. At this point the three row-pointers₍ are incremented, and the cycle repeats for the second row of each panel, and so on. Column scanner disables are used so that each of the three displays can be sequentially loaded with data, and retain the data unchanged, until a next incoming row time during which the DataRamp transfers the data to the panel pixels. Thus, a substantial portion of a row time is available and longer duration DataRamps can be used. Longer DataRamp durations tend to be associated with superior displayed images. During one incoming row time (31.78 μs), the DataRamp is configured to transfer voltages from column lines to pixels simultaneously in all three panels. At the same time, data is scanned into the three panels, one panel at a time. Separate DataRamps generators are used for each of the three displays, since the DataRamps are used simultaneously. A representative display driver can include four 10-bit output channels, so that three channels can be used for

DataRamps and a fourth channel used to produce a Ramp signal. Alternatively, the Ramp signal can be generated with a simple op-amp integrator circuit and the fourth channel used to produce V_common. This latter approach is probably more attractive, since it tends to cancel any common-mode signals on the 10-bit outputs. With reference to FIG. 8, row scan enable signals VENR, VENG, and VENB associated with red, green, and blue color components, respectively, and associated separate display panels are shown within a single 31.78 μs row time. A clock signal SCLK and a digital data in signal DDIN are also shown. In this representative row time, a rising edge of the clock SCLK is associated with RSEN becoming positive and enabling a red component row scanner. The remaining scan enable signals GSEN, BSEN are low, and the associated scanners are not enabled. With RSEN high, red component image data is scanned to a row of the R-panel. RSEN then becomes low, GSEN becomes high, and green image component data is scanned to a row of the G-panel. GSEN and RSEN then are both low, and BSEN becomes high so that blue image component data is scanned to the B-panel. In this example, external scan control signals (RSEN, GSEN, BSEN) control the row scanner so that a single row of R, G, and B is scanned before scanning of a next row begins. After a first row of each subpanel is scanned, respective row pointers are incremented, and this cycle until a frame is complete. A row buffer can be used to store incoming data, and a frame buffer is unnecessary. Data scanning is sequential within a row time so that no more than 1/3 of the row time is available. Transfer of scanned in data to display pixels is in parallel in the three panels, so that most of the row time is available.

In this example, external logic generates at least some control signals, data clocks, etc., at rates that are three time the incoming line rate; since three lines of the physical display are written for every line of incoming data. Lines associated with the column scanner fall into this category: DDIN, DCLKl - DCLK4. Other signals associated with the DataRamp-to-Pixel transfer process, and the row scanner, can run at the incoming line rate. These signals include SDIN, SCLK, ZEROA, ZEROB, RESET, COMP, U/LB, and scan enables.

FIG. 9 is a schematic diagram of a portion of a single panel configured to receive image data for a selected color component at a data rate of three times an incoming data rate. FIG. 10 is a schematic block diagram of a drive system for use in a 3-panel LCD display based on panels as shown in FIG. 9. Three DataRamp inputs can be used. The panels include inputs for a vertical scan enable (VSEN) signal and a horizontal scan enable (HSEN) signal. A controller 1004 re-orders each row of incoming data into separate red, green, and blue line buffers in internal memory and sends the data to a video processor 1005 (an SA300) in 16-bit words corresponding to two adjacent pixels. Every four clock cycles, internal A-D converters in the video processor 1005 are updated, and eight updated analog values appear at the outputs of the video processor. These values are latched into the column scanner by the next incoming DCLK rising edge. LCD control signals are managed by the controller 1004 based on the HS and VS signals associated with the incoming video. Three DataRamp signals and a V_common potential can also be synthesized in the display controller 1004, converted to analog values in the video processor 1005, and delivered to a buffer 1010 before delivery to a display panel. (These signals are noted as "/A" in FIG. 10). The Ramp signal can be generated by an op-amp integrator, with reset levels and slopes controlled by PWM signals from the display controller 1004. In this example, Ramp duration and DataRamp duration are a full row time (not 1/3 of a row time).

Method 4: 3-Panel Display with Simultaneous Segmented Scanning

In this method, each individual display panel has an independent, fully functional column and row scanner. Image signals can be decoded by dividing the eight available data lines into three pairs of two channels each (two remain unused), and sending data to the three display panels in parallel. Individual display panels are configured to use two data channels instead of eight. Because the display panels are driven simultaneously, column and row scanners can operate simultaneously and no vertical or horizontal scan enable signals are needed. In addition, a frame buffer is unnecessary. While a row buffer can also be eliminated, operation without a row buffer results in a significantly higher data rate to the display because the row buffer allows data transfer to a row to use an entire row time. Thus, eliminating the row buffer restricts the data transfer to only the active (non-blanking) portion of the row. Two data lines can be routed to each display panel instead of eight. Long DataRamp times (most of the incoming row time) are available. However, this method uses the 8-channel drivers inefficiently so that an increased DCLK edge rate is necessary. A driver that includes 9 or 12 data channels would be more efficient. FIG 11 is a schematic diagram of one panel of such a 3-panel full color display system. FIG. 12 is a block diagram of the 3-panel display system. This system uses two data inputs per panel such as, for example, Dl, D2 or D3, D4, or D5, D6 as shown in FIG. 12. No scanner shift enable signals are needed.

If a line buffer is available, red, green, and blue image data can be merged in a data stream to a video processor 1205. For example, on one clock to the video processor 1205, data for two adjacent Red pixels are shifted into its 16-bit inputs. On a next clock, data for two adjacent Green pixels are shifted in. On a third clock, data for two adjacent Blue pixels are shifted in. The next clock updates all of the video processor analog outputs from the shifted-in data, while shifting in new values for the next two adjacent Red pixels. Therefore, after every 3 clocks to the video processor, six new analog values appear at outputs 1240 and are latched (two channels each) into display column scanners. (Two channels remain unused.) The clocks can be derived from a PLL 1210 since it is necessary to write to the video processor 1204 faster than the incoming data stream. To calculate the frequency, note that 31.78 μs is available to write 864 bytes to the display. Since this is done two data channels per display per video processor update cycle, 432 update cycles are needed. Since each takes 3 clocks, 1296 clocks are needed in 31.78 μs, for a clock frequency of ~41 MHz. However DCLK edges need to come faster than in some other configurations, every 3 clocks for an edge rate of 13.6 MHz. Thus, data to the display changes every 73.6 ns.

If no line buffer is available, the display can be written at a rate locked to the active (non-blanked) incoming video, since there is no line buffer for rate conversion. Since three data output clocks for every two incoming data clocks are used, the display clock needs to be 3/2 the rate or the input data clock, or about 49 MHz. Two incoming clock periods provide data for two pixels of each color, and this data is subsequently transferred to three panels. An output data path is 16 bits, while the input data path is 24 bits. This clock rate corresponds to a DCLK edge rate of 16.38 MHz, and the data to the display changes every 61 ns.

The examples use four DCLK signals: DCLKl, DCLK2, DCLK3, DCLK4. This is not necessary, and use of two DCLK signals is probably preferable. This number of DCLK signals typically depends on how fast a column scanner shift register can operate. Regardless of the number of DCLKS used, the DCLK (rising) edge rates must be at least as fast as those calculated above. The examples described above are representative, and many other examples are possible. Displays can have different numbers of pixels such as, for example, arrays of 864 by 600, 800 by 600, 1024 by 768, etc. One, two, three, or four separate display panels can be used, or a single display panel can be divided into one, two, three, or four sub-arrays. One or more display controller integrated circuits can be used with displays having larger pixel counts. For example, a three color WXGA (1366 by 768 pixels) can be built. Different numbers of ramp and data channels can also be used, and a backplane voltage V_common can be generated by sources other than a display processor such as, for example, with a DAC or a voltage divider. In other examples, 1, 2, 3, 5, 6, 8, or more DCLK signals are used. Display subpanels or panels in a display system can have different sizes and/or resolutions. For example, Blue. and/or Red pixel arrays can have lower resolutions than a Green pixel array, and thus require lower data rates. Various drive chips can be used instead of a SARIF SA300 such as, for example, ANALOG DEVICES AD8380 devices. An output clock can be derived from sources other than PLL multiplication of the input clock. Panels/subpanels can be arranged vertically, horizontally, or in non-linear patterns such as triangles. Different panels/subpanels can be operated at different pixel, row, and/or frame rates from each other. Full frames, sets of rows, or individual rows associated with each color component can be scanned simultaneously or sequentially. These methods can also be used in non-video applications such as, for example, digital photography exposure systems. In other examples, columns of panels and subpanels are scanned as described above with respect to rows. In other examples, scan enable signals can be omitted and digital data in (DDIN) signals associated with each color component can be associated with row scanning, and different clock rates can be used.

It will be apparent that the examples described above can be modified in arrangement and detail without departing from the scope of the disclosure. We claim all that is encompassed by the appended claims.

Claims

We claim:

1. A display controller, comprising: an input configured to receive an image signal that includes image data associated with at least a first and a second color component; a memory; a processor configured to store at least one row of image data associated with the color components in the memory; and a display driver configured to direct the image data associated with the first color component to a first image data output and image data associated with the second color component to a second image data output.

2. The display controller of claim 1, further comprising a data ramp generator configured to produce a first dataramp associated with the first color component and a second dataramp associated with the second color component.

3. The display controller of claim 2, wherein the data ramp generator is configured to deliver the first data ramp to a first output associated with the first color component and the second data ramp to a second output associated with the second color component.

4. The display controller of claim 2, wherein the data ramp generator is configured to deliver the first data ramp and the second data ramp to a common output.

5. The display driver of claim 1, wherein the at least one row of image data stored by the processor includes image data for a plurality of rows of image data.

6. The display driver of claim 1, wherein the at least one row of image data stored by the processor includes a frame of image data.

7. The display driver of claim 1, wherein the first image data output and the second image data output are the same.

8. A display system, comprising: a display panel that includes pixel arrays associated with a red color component, a green color component, and a blue color component; and a row scanner configured to scan at least one row line of the red, green, and blue pixel arrays.

9. The display system of claim 8, wherein the row scanner is configured to sequentially scan the row lines of the pixel arrays.

10. The display system of claim 8, wherein the row scanner includes scanner sections associated with the red color component, the green color component, and the blue color component, wherein the scanner sections include a scan enable input configured to initiate row scanning.

11. The display system of claim 8, further comprising a display driver configured to receive a video signal and distribute color image data for the red color component, the green color component, and the blue color component to the respective pixel arrays.

12. The display system of claim 11, further comprising a memory configured to store image values for a row of each of the pixel arrays.

13. The display system of claim 12, wherein the memory is configured to store image values for a plurality of rows of each of the pixel arrays.

14. The display system of claim 12, wherein the display driver is configured to receive and store image data for a row of pixels in a row time, and distribute stored images values for at least a row of one of the color components in about one-third of the row time.

15. The display system of claim 12, wherein the memory is configured to store image values for at least two rows of each of the pixel arrays.

16. The display system of claim 12, further comprising a data ramp generator configured to produce at least a red data ramp signal, a green data ramp signal, and a blue data ramp signal and deliver the data ramp signals to the respective pixel arrays.

17. The displays system of claim 16, wherein the red, green, and blue data ramp signals are different.

18. A display system, comprising: display panels associated with a red color component, a green color component, and a blue color component, each of the display panels including a row scanner; and a display controller configured to deliver red, green, and blue color component image data and red, green, and blue scan enable signals to the respective display panels.

19. The display system of claim 18, wherein the display controller is configured to provide red, green, and blue data ramp signals to the respective display panels, wherein at least one of the red, green, and blue dataramp signal is unique.

20. A display method, comprising: receiving a video signal; storing image data associated with at least one row of image data for a red color component, a green color component, and a blue color component based on the received video signal; retrieving the stored image data; delivering red color component image data to a first display, green color component data to a second display, and blue color component data to a second display, wherein the first, second, and third displays include rows of pixels; and sequentially scanning the red, green, and blue color component data into the respective displays.

21. The method of claim 20, wherein the sequential scanning is based on scanning all the rows associated with a selected color component prior to scanning the rows associated with the unselected color components.

22. The method of claim 20, further comprising receiving the row of image data in a row time, and delivering the image data associated with the color components sequentially to the displays in about a row time.

23. The method of claim 20, further comprising supplying data ramp signals to the displays based on the associated color component.

24. The method of claim 20, wherein segments of red, green, and blue image data are sequentially scanned into the displays.

25. The method of claim 20, wherein the segments are associated with a plurality of lines.