WO2004015869A1

WO2004015869A1 - Phase-locked-loop circuit and method

Info

Publication number: WO2004015869A1
Application number: PCT/IB2003/002918
Authority: WO
Inventors: Hayden C. Cranford Jr.; Vernon R. Norman; Martin Schmatz
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2002-07-31
Filing date: 2003-06-27
Publication date: 2004-02-19
Anticipated expiration: 2005-01-31
Also published as: WO2004015869A8; AU2003244959A1

Abstract

A phase locked loop circuit for generating a frequency-controlled output signal and a method for providing a frequency controlled output signal in a phase locked loop circuit are introduced. A controllable oscillator unit (260, 460) of said phase locked loop is operated for generating the output signal (261, 461). A frequency of said output signal (261, 461) is evoked by providing the oscillator unit (260, 460) with a first control signal (281, 381, 481) and with a second control signal (241, 341, 441). The first control signal (281, 381, 481) and the second control signal (241, 341, 441) are adapted automatically such that a given reference frequency is achieved in the output signal (261, 461).

Description

PHASE-LOCKED-CIRCUIT AND METHOD

Field of the invention

This invention generally relates to electronic circuits and specifically to the group of control circuits known as phase locked loop circuits also termed PLL circuits herein for brevity.

Background of the invention

PLL circuits are well known in the art and are used in such typical areas as communications, wireless systems and signal processing. In essence, a PLL circuit is a feedback system that operates on the excess phase of nominally periodic signals. The loop is considered "locked" if the phase difference is constant with time or, in other words, if input and output frequencies are equal.

Typical specific problems solved by means of PLL circuits are those connected with reduction of what is termed "timing jitter", a phenomenon that may be observed on signals as they travel through a communication channel, or as they are retrieved from a storage medium. Other fields of use of PLL circuits include skew suppression, frequency synthesis and/or multiplication, e.g. when an on-chip clock frequency within a digital system needs to be much higher than that of the system clock. In fact, frequency multiplication is one of the outstanding fields of use of PLL circuits. Further uses of PLL circuits include those where there is a need to recover a timing information from received data. There, PLL circuits can be used together with an edge detector to perform clock recovery (CRC).

It is well known in the art to use PLL circuits for frequency and/or phase synchronization and for phase stable frequency multiplication. Typically, a conventional PLL circuit comprises a phase detector, a charge pump and a voltage controlled oscillator - that means frequency-controlled by a voltage. Circuit 1 shown diagrammatically in Fig. 1 represents such a known, conventional PLL circuit. A reference frequency signal 110 is fed via a connection 111 into a phase/frequency detector 120 which receives a further input signal 161 via a prescaler 150 from an oscillator 160 with a frequency control input. The detector 120 produces either an up-signal 121 or a down-signal 122 fed to a charge pump 130 producing an output signal fed via a loop filter 140 to the oscillator 160. The up- or down-signal is used for adjusting the oscillation frequency of the controllable oscillator 160, in case the detector 120 has detected any difference in frequency between the reference frequency input 110 and the oscillator's current output signal 161 - or a derivative thereof. Accordingly, the output frequency is tuned so as to achieve a frequency that is comparable to that of the reference input.

In other words and more specifically, a conventional PLL circuit works by comparing the reference frequency from a reference frequency input with a processed output frequency, and the phase difference yields either the "up signal" or the "down signal" for shifting the output frequency towards the reference frequency. The resulting signal is fed to a charge pump where the signal is converted into a current which is filtered by the loop filter. Then, the output of the loop filter is fed to the oscillator with a controllable frequency, such as the voltage controlled oscillator. The voltage input of the voltage controlled oscillator determines its frequency at an output which yields the total output frequency.

A very popular version of a voltage controlled oscillator in CMOS applications is its implementation as a ring oscillator. Oscillators on high density CMOS chips with a priority on digital functions are basically restricted to implementations in the form of ring oscillators with several drawbacks considering jitter and/or phase noise. First, they do not have a high factor Q of quality and - as a consequence - have a lower phase noise performance compared with a resonator (e.g. LC-) type oscillator. Second, prior art circuits of this type have critical production and temperature tolerances with regard to the output frequency. This has to be accounted for by a large tuning range, and this, in turn, makes PLL circuits sensitive to injected noise.

Starting from another point, some PLL applications like high speed interconnections require a large tuning range since those PLL circuits might be applied to many different customer networks thus requiring adaptation to many different frequencies, since data rates in these networks are not known a priori. The larger the tuning range has to be, the lower the factor Q is. The lower the factor Q is, the more noise sensitivity a PLL circuit shows.

With regard to components of a PLL circuit, the voltage controlled oscillator and the phase/frequency detector are critical parts. In order to achieve a large tuning range - also called tuning sensitivity, the oscillator has to offer a large control- voltage-to-frequency-offset ratio; the latter is only achieved by simultaneously accepting a low factor of merit Q. Result is jitter, which can be considered as a noise phenomenon of the oscillator, since due to low factor Q, signal energy compared to noise energy is low. hi addition, the phase/frequency detector requires a layout that is very tuning sensitive. This, in effect, leads to limited stability of the loop, such that the output of the loop filter may have large rectangular excursions or "ripples" in each cycle of operation, and such ripples may become so large as to overload the voltage controlled oscillator.

Generally, prior art PLL circuits work under a limited stability which, in turn, tends to decrease when the sensitivity of the voltage controlled oscillator is increased. Instability may become critical upon occurrence of noise.

A known modification of conventional PLL circuits is what is called a "fine/coarse PLL circuit." Herein, the voltage controlled oscillator provides two inputs, a coarse input and a fine input. The fine input has a lower sensitivity since its range of tunable frequencies is limited. However, the coarse input has a high sensitivity. The coarse input of a PLL circuit is provided with a predetermined and fixed signal value. This fixed value causes a certain frequency in the output signal that can be tuned up or down within a small range by adjusting the fine input.

However, this amended PLL circuit still shows insufficient noise characteristics when applied to large frequency range applications since the fine tuning channel still has to serve a wide range of frequencies and thus still shows high tuning sensitivity. Consequently, noise is still a major problem.

Accordingly, it is desirable to achieve an improved circuit architecture and an operating method of a PLL circuit that further reduce noise impact while at the same time offer a large tuning range.

Summary of the invention

According to a first aspect of the present invention, there is provided a phase locked loop circuit for generating a frequency-controlled output signal, comprising a first frequency control loop for providing a first control signal and a second frequency control loop for providing a second control signal. The first control signal and the second control signal are automatically adjusted in an operating mode of the phase-locked loop circuit. A controllable oscillator unit provides the output signal. A frequency of the output signal is determined by the first control signal and the second control signal.

hi the following, the first frequency control loop is also called coarse frequency control loop, the second frequency control loop is also called fine frequency control loop, the first control signal is also called coarse control signal, and the second control signal is also called fine control signal, for demonstrating more explicitly which frequency control loop and which control signal is responsible for causing rather a major portion of a frequency change in the output signal and thus being responsible for sort of a coarse tuning, and which frequency control loop and which control signal is responsible for causing rather a minor portion of a frequency change in the output signal and thus being responsible for sort of a fine tuning.

In connection with such a dual loop style PLL circuit a very narrow frequency range can be used for fine tuning so as to provide an excellent performance with regard to phase noise and jitter. This is achieved by auto-tracking also the coarse control signal in an operating mode. Since the coarse control signal basically can vary and is adapted automatically in a control loop style, the fine control signal now preferably serves for a very narrow frequency band and thus is responsible only for causing a small frequency portion and change of the entire output signal frequency. This leads to a higher factor Q in the fine tuning oscillator path and thus causes less noise and jitter. The operating mode characterizes a mode of the PLL circuit when the frequency of the output signal is controlled and adjusted if necessary. Now, an excellent signal-to-noise ratio, a high Q factor and a large tuning sensitivity is achieved in the overall phase locked loop circuit. This allows applying the PLL circuit to applications that cover wide frequency ranges like high speed communication systems. At the same time, temperature and/or production tolerance can be eliminated.

The output frequency preferably comprises a base frequency that is a constant frequency. A change in this output signal's base frequency is evoked by the first and the second control signal, wherein the first control signal is preferably responsible for evoking a frequency change in the output signal that is equal or greater than a frequency change that is evoked by the second control signal.

Preferably, the first control signal is responsible for evoking a frequency change in the output signal that is between ten and hundred times greater than a frequency change that is evoked by the second control signal.

These preferred embodiments serve for achieving even less noise and jitter in the phase locked loop. With regard to the scope of the invention, the proposed limits shall permit tolerances of ten percent.

Li a preferred embodiment, the first frequency control loop provides an input for the second control signal for determining the first control signal in dependence on the second control signal. So the fine control signal is used to adjust the coarse control signal.

In another preferred embodiment, the first frequency control loop comprises an increasing unit receiving the second control signal for causing an amplitude increasing effect on the first control signal when the second control signal is above a threshold. This embodiment helps increasing the coarse control signal when the fine control signal is on a high level, and in particular when the fine control signal is on a high level for a longer period. This indicates the need to adjust the coarse control signal to a higher level, respectively a higher amplitude value.

In another preferred embodiment, the first frequency control loop comprises a decreasing unit for causing an amplitude decreasing effect on the first control signal. This embodiment is advantageous to install a reverse effect to the above mentioned increasing effect on the coarse control signal. Since there is only provided an increasing effect based on the fine control signal, it is advantageous to introduce decreasing means in order to stop increasing effect on the coarse control signal or lower an increased coarse control signal again where appropriate. This digital leakage counter is working only into one frequency direction. With such an approach, the loop gain in one direction is essentially zero. This will break the loop and maintain stability.

In another preferred embodiment, the first frequency control loop comprises a filter unit for flattening increasing and decreasing effects on the first control signal. Having quickly reacting coarse control signal increasing and decreasing means, oscillation in the coarse control signal with a high frequency may appear, which is not appreciated from a loop stability's point of view. This filter unit helps averaging such oscillation.

Tn another preferred embodiment, the increasing unit comprises a comparator for comparing the second control signal with the threshold, and a post-connected latch for forming a pulse when the second control signal exceeded the threshold. The latch is preferably clocked, such that when the threshold is exceeded by the fine control signal with every clock cycle, a pulse is generated. The longer time the amplitude of the fine control signal is above the threshold, the more pulses are created as a measure for indicating a coarse control adjustment need, since whenever the fine control signal is reaching the limits of its range the coarse control signal is preferably adjusted.

Preferably, the decreasing unit provides a time constant decreasing effect on the first control signal. Preferably this is achieved by means of a leakage counter for providing overflow pulses.

In another preferred embodiment, a counter is provided for counting up pulses received from the latch and for counting down overflow pulses received from the leakage counter. Then, the coarse control signal can be adjusted proportionally to the counter reading and such being adjusted taking increasing effects derived from the fine control signal and simultaneously taking decreasing effects from the leakage counter into consideration. Accordingly, the counter is used as a digital integrator and realizes a low pass function with beneficial effects for switching noise.

Preferably, the filter unit comprises a digital/analog converter for receiving a counter reading from the counter and for converting only most significant bits of the counter reading into an analog signal. This digital/analog converter realizes two functions: its intrinsic converting function and an additional filtering function by converting only most significant bits of the counter reading, for example taking only five most significant bits.

In particular, the first control signal is derived from a converted signal delivered by the digital/analog converter.

Since the first frequency control loop is digitally implemented, a work clock for the latch, the leakage counter, the counter and the digital/analog converter is preferred to be provided. This clock is preferentially derived from a reference frequency input, that is simultaneously used as nominal signal for the adjusting output signal to.

In another preferred embodiment, the first frequency control loop is designed as a digitally operating circuit and the second frequency control loop is designed as an analog operating circuit. Consequently, the phase locked loop is including an analog and digital dual loop circuit and can be produced by standard fabrication methods.

Preferably, the second frequency control loop, that is the fine control loop, comprises elements of a standard phase locked loop, such as a a frequency detector for comparing phase or frequency of a reference frequency input signal with phase or frequency of the output signal or a derivative thereof, and for providing a signal indicating a difference in phase or frequency, wherein the second frequency control signal, that is the fine control signal, is dependent from the difference indicating signal. Further, a charge pump is provided as well as a low pass filter in series with the frequency detector for converting the difference indicating signal into the second frequency control signal. The phase locked loop according to the invention is preferably applied to reference frequency input signals with a frequency greater than 1 GHz.

According to another aspect of the present invention, there is provided a method for providing a frequency controlled output signal in a phase locked loop circuit, comprising operating a controllable oscillator unit of the phase locked loop for generating the output signal, evoking a frequency change in the output signal by providing the oscillator unit with a first control signal and with a second control signal, and adapting automatically the first control signal and the second control signal such that a given reference frequency is achieved in the output signal.

Preferred method embodiments according to claims 19 to 27 and their advantages correspond with preferred embodiments of the inventive PLL circuit and respective advantages.

Brief summary of the drawings

Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a conventional PLL circuit;

FIG. 2 is a diagram of an embodiment of a PLL circuit in accordance with the present invention;

FIG. 3 is a diagram of an embodiment of a coarse frequency control loop in accordance with the present invention; and

FIG. 4 is a more detailed diagram of an embodiment of a PLL circuit in accordance with the present invention. Detailed description of the drawings

Fig. 2 is a diagrammatic illustration of a PLL circuit 2 according to the invention comprising a fine frequency control loop 21 and a coarse frequency control loop 280. A reference frequency signal 210 is fed to a phase/frequency detector 220 which produces an up-signal 221 or a down-signal 222 to a charge pump 230. The charge pump 230 is connected to a loop filter 240. The reference frequency signal 210 is also provided to the coarse frequency control loop 280 which further receives a threshold signal 282. The loop filter 240 provides a fine control signal 241 to the coarse frequency control loop 280 and to an oscillator unit 260. The coarse frequency control loop 280 generates a coarse control signal 281 which is fed to the oscillator unit 260, which provides an output signal 261 that is determined by the fine control signal 241 and the coarse control signal 281. Output signal 261 is determined in a way that a given base frequency of the output signal 261 can be changed according to the coarse and the fine control signal 281 and 241.

The oscillator unit 260 is preferably able to process two input signals - the coarse control signal 281 and the fine control signal 241 - and can be embodied as a single component. Signals 241 and 281 control the frequency of said output signal 261 by changing the given base frequency of the oscillator unit 160.

The coarse control signal 281 is responsible for evoking a frequency change in the output signal 261 that is between ten and hundred times greater than a frequency change that is evoked by the fine control signal 241.

The oscillator unit 260 can also comprise two oscillator components, one oscillator for receiving the coarse control signal 281, the other oscillator for receiving the fine control signal 241. The fine tuning path of the oscillator unit 260 is covering only a small range of output frequencies around the frequency that is tuned by the coarse control signal. Factor Q of this path is high.

The oscillator unit 260 is preferably comprising a voltage controlled oscillator, that is controlled by coarse and fine control signal voltages 281 and 241. The coarse frequency control loop 280 of Fig. 2 is illustrated more detailed in FIG. 3, referenced there by number 3. Both the fine control signal 341 and the threshold 382 are fed into a digitally operating comparator 383 to produce an output signal 393 fed to a latch 384 which, in turn, is receives the reference frequency signal 310 for clock purposes, which is also connected with a leakage counter 390 showing a specified number q of bits. An overflow signal 389 from the leakage counter 390 is fed - as a down counting signal - to a counter 385 which receives any up counting signal 398 from the latch 384. The counter 385 offers a predetermined number of bits, for example m bits. The counter 385 is also connected to the reference frequency signal 310 and produces an output 395 which is a MSB-signal fed to a digital/analog converter 386 for m - n bits to produce an output 396 that is preferably passed through a low pass filter 387, and ends as the coarse control signal 381.

Fig. 4 is a detailed illustration of a PLL circuit according to the invention, basically showing the PLL circuit of FIG. 2 and having replaced the coarse frequency control loop block 280 with the detailed coarse frequency control loop 3 of FIG. 3, and referencing now this detailed coarse frequency control circuit by number 480 whereas the entire PLL circuit is referenced by 4. The PLL circuit according to FIG. 4 comprises a fine frequency control loop 41 and a coarse frequency control loop 480. FIG. 4 shows: phase/frequency detector 420, a charge pump 430 and a low pass filter as a loop filter 440 to deliver a fine control signal 441 to an oscillator unit 460 (VCO) with fine and coarse frequency control inputs. The coarse control signal 481 is produced by the digitally implemented coarse control loop 480, comprising a leakage counter 490, a comparator 483, a latch 484, a counter 485, a digital/ analog converter 486, and a low pass filter 487 in the manner explained in connection with Fig. 3 above.

More specifically, the oscillator unit 460 has two inputs, i.e. a coarse and a fine control input. The latter is at the same time the output of the loop filter 440 and is fed into the coarse frequency control loop 480 while the coarse input 481 is fed directly by the coarse frequency control loop 480. The reference frequency signal 410 and the external threshold signal 482 are two other inputs for the coarse frequency control loop 480.

Accordingly, in the PLL circuit depicted in FIG. 4 the output of loop filter 440 which carries the fine tuning voltage 441 is compared with a threshold 482. The comparator 483 generates an output signal 493 corresponding to those peaks of fine tuning voltage 441 that exceed the reference level 482. This is digitized in the latch 484 and then fed to the counter 485. As a consequence, the counter 485 counts the number of times that the fine control voltage 441 exceeds the reference level 482. Now, some MSBs of that counter 485 are fed to the digital/analog converter 486 which creates an analog signal 496 from the MSB input 495.

A higher number of peaks will produce a correspondingly higher output voltage of the digital/analog converter 486. This voltage is low-pass filtered in the filter 487 and fed as the coarse control signal 481 to the oscillator unit 460. This control, however, works but for upper peaks of the fine tuning voltage 441. Once the coarse control signal 481 has shifted the output signal 461 such that the fine control signal 441 no longer exceeds the threshold 482, no counter-control is present. Accordingly, the leakage counter 490 triggered by the reference frequency signal 410 - which serves as clock - counts the time and, in case of overflow corresponding to a predetermined time, will trigger down the input 489 of the counter 485. The effect is a time-controlled down-counting. Now, even if there are no fine control signal peaks at all, the clocked down-steps will cause no harm because as soon as up-steps occur this will cause a counter-effect.

It is to be noted that the frequency figures in Fig. 4 and the bit figures are given merely for purposes of illustration and understanding and that no limitation is to be construed from such illustration.

Claims

1. A phase locked loop circuit for generating a frequency-controlled output signal, comprising

• a first frequency control loop (280, 3, 480) for providing a first control signal (281, 381, 481) and a second frequency control loop (21, 41) for providing a second control signal (241, 341, 441), said first control signal (281, 381, 481) and said second control signal (241, 341, 441) being automatically adapted in an operating mode of said phase-locked loop circuit,

• a controllable oscillator unit (260, 460) providing said output signal (261, 461), a frequency of said output signal (261, 461) being determined by said first control signal (281, 381, 481) and said second control signal (241, 341, 441).

2. The phase-locked loop circuit according to claim 1, wherein said first frequency control loop (280, 3, 480) provides an input for said second control signal (241, 341, 441) for determining said first control signal (281, 381, 481) in dependence on said second control signal (241, 341, 441).

3. The phase-locked loop circuit according to claim 2, wherein said first frequency control loop (280, 3, 480) comprises an increasing unit receiving said second control signal (241, 341, 441) for causing an amplitude increasing effect on said first control signal (281, 381, 481) when said second control signal (241, 341, 441) is above a threshold (282, 382, 482).

4. The phase-locked loop circuit according to one of the preceding claims, wherein said first frequency control loop (280, 3, 480) comprises a decreasing unit for causing an amplitude decreasing effect on said first control signal (281, 381, 481).

5. The phase locked loop circuit according to one of the preceding claims, wherein said first frequency control loop (280, 3, 480) comprises a filter unit for flattening increasing and decreasing effects on said first control signal (281, 381, 481).

6. The phase locked loop circuit according to claim 3, wherein said increasing unit comprises a comparator (383, 483) for comparing said second control signal (241, 341, 441) with said threshold (282, 382, 482), and a post-connected latch

(384. 484) for forming a pulse (398, 488) when said second control signal (241, 341, 441) exceeded said threshold (282, 382, 482).

7. The phase locked loop circuit according to claim 4, wherein said decreasing unit provides a time constant decreasing effect on said first control signal (281, 381, 481).

8. The phase locked loop circuit according to claim 4 or claim 7, wherein said decreasing unit comprises a leakage counter (390, 490) for providing overflow pulses (389, 489).

9. The phase locked loop circuit according to claim 6 in connection with claim 8, wherein said first frequency control loop (280, 3, 480) comprises a counter (385, 485) for counting up pulses (398, 488) received from the latch (384, 484) and for counting down overflow pulses (389, 489) received from said leakage counter (390, 490).

10. The phase locked loop circuit according to claim 5, wherein said filter unit comprises a digital/analog converter (386, 486) for receiving a counter reading from said counter and for converting only most significant bits of said counter reading.

11. The phase locked loop circuit according to claim 10, wherein said first control signal (281, 381, 481) is derived from a converted signal (396, 496) delivered by said digital/analog converter (386, 486).

12. The phase locked loop circuit according to one of the preceding claims, wherein a work clock of said latch (384, 484), said leakage counter (390, 490), said counter

(385. 485) and said digital/analog converter (386, 486) is derived from a reference frequency signal (210, 310, 410).

13. The phase locked loop circuit according to one of the preceding claims,

• wherein said first frequency control loop (280, 3, 480) is designed as a digitally operating circuit, and

• wherein said second frequency control loop (21, 41) is designed as an analog operating circuit.

14. The phase locked loop circuit according to one of the preceding claims,

• wherein said second frequency control loop (21, 41) comprises a frequency detector (220, 420) for comparing phase or frequency of a reference frequency signal (210, 310, 410) with phase or frequency of said output signal (261, 461) or a derivative thereof, and for providing a signal indicating a difference in phase or frequency, and

• wherein said second control signal (241, 341, 441) is dependent from said difference indicating signal.

15. The phase locked loop circuit according to claim 14, wherein a charge pump (230, 430) and a low pass filter (240, 440) are connected in series with said frequency detector (220, 420) for converting said difference indicating signal into said second control signal (241, 341, 441).

16. The phase-locked loop circuit according to one of the preceding claims, wherein said first control signal (281, 381, 481) is responsible for evoking a frequency change in said output signal (261, 461) that is equal or greater than a frequency change that is evoked by said second control signal (241, 341, 441).

17. The phase-locked loop circuit according to claim 16, wherein said first control signal (281, 381, 481) is responsible for evoking a frequency change in said output signal (261, 461) that is between ten and hundred times greater than a frequency change that is evoked by said second control signal (241, 341, 441).

18. A method for providing a frequency controlled output signal in a phase locked loop circuit, comprising

• operating a controllable oscillator unit (260, 460) of said phase locked loop for generating said output signal (261, 461),

• evoking a frequency of said output signal (261, 461) by providing said oscillator unit (260, 460) with a first control signal (281, 381, 481) and with a second control signal (241, 341, 441), and

• adapting automatically said first control signal (281, 381, 481) and said second control signal (241, 341, 441) such that a given reference frequency is achieved in said output signal (261, 461).

19. Method according to claim 18, wherein said first control signal (281, 381, 481) is determined by said second control signal (241, 341, 441),.

20. Method according to claim 19,

• wherein said second control signal (241, 341, 441) is compared with a threshold (282, 382, 482), and

• wherein an amplitude increasing effect on said first control signal (281, 381, 481) is caused when said second control signal (241, 341, 441) is above a threshold (282, 382, 482).

21. Method according to claim 20, wherein a decreasing effect on said first control signal (281, 381, 481) is achieved over time.

22. Method according to claim 20 in combination with claim 21, wherein increasing and decreasing effects on said first control signal (281, 381, 481) are flattened.

23. Method according to one of the preceding claims 18 to 22,

• wherein pulses (398, 488) that are generated when the second control signal (241, 341, 441) exceeds said threshold (282, 382, 482) are counted up and overflow pulses (389, 489) of a leakage counter (390, 490) are counted down, and

• wherein a counter reading resulting from counting up and counting down is determining said first control signal (281, 381, 481).

24. Method according to claim 23, wherein only the most significant bits of said counter reading are converted into an analog signal.

25. Method according to one of the preceding claims 18 to 24,

• wherein a frequency detector (220, 420) is comparing phase or frequency of a reference frequency signal (210, 310, 410) with said phase or frequency of said output signal (261, 461) or a derivative thereof, and

• wherein said second control signal (241, 341, 441) is determined by said comparison.

26. Method according to one of the preceding claims 18 to 25, wherein said first control signal (281, 381, 481) is responsible for evoking a frequency in said output signal (261, 461) that is equal or greater than a frequency that is evoked by said second control signal (241, 341, 441).

27. Method according to claim 26, wherein said first control signal (281, 381, 481) is responsible for evoking a frequency in said output signal (261, 461) that is between ten and hundred times greater than a frequency that is evoked by said second control signal (241, 341, 441).