WO2004015715A1

WO2004015715A1 - Shift register circuit arrangement with improved compatibility and method of operating it

Info

Publication number: WO2004015715A1
Application number: PCT/IB2003/003134
Authority: WO
Inventors: Matthias Locher; Martin Schellenberg
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2002-08-08
Filing date: 2003-08-04
Publication date: 2004-02-19
Also published as: CN1675719A; JP2005535991A; EP1529292A1; DE10236328A1; AU2003249502A1

Abstract

The shift register circuit arrangement (1), or a finite-impulse-response-digital-digital-to-analog converter for audio technology respectively, comprises a plurality of sequentially cascaded flip-flops (3.1,..., 3.n) connected together in pairs by a data line (2), which elements can be clocked by a clock signal over a clock signal line (7). The flip-flops (3.1,..., 3.n) are then connected together in pairs in series by the clock signal line (7). The connection of the flip-flops (3.1,..., 3n) by the clock signal line (7) is such that a signal on the data line (2) and the clock signal propagate in opposite directions to adhere to the necessary setup and hold times. Due to the delay, which occurs in each flip-flop (3.1,..., 3n), the flip-flops (3.1,..., 3n) are not clocked simultaneously, so that only slight power impulses are developed on the supply lines. Therefore, the circuit arrangement (1) has improved electromagnetic compatibility without separate delay circuits being necessary.

Description

Shift register circuit arrangement with improved compatibility and method of operating it

The present invention is in the field of shift register circuit arrangements and pertains to such a circuit arrangement with improved electromagnetic compatibility and a method of operation it. An illustrative embodiment of the invention from audio technology is a finite impulse response signal analog converter (FIRDAC) with reduced current impulses in the power supply.

Shift register circuit arrangements typically include a large number of logic elements, which are clocked simultaneously. For example, an audio FIRDAC includes a number of flip-flops that are in the order of magnitude of 100. Due to the limited power of the clock generator the lead of the clock signal reaching the flip-flop levels off. In each clock cycle this causes strong current impulses on the supply lines. This leads to a broad spectrum of harmonics and to voltage breakdowns on the supply lines. Signals in other circuit blocks, more particularly high-frequency circuits, oscillators, phase-locked loop (PLL) circuits or analog-to-digital (AD) converters of the microphones are distorted. The interference voltages are also propagated over the chip by the substrate and again picked up (body effect) by sensitive (usually analog) circuit portions. Furthermore, high-frequency harmonics in the supply lines radiate electromagnetic waves into the environment.

Fig. 1 diagrammatically shows a block diagram of a FIR filter circuit arrangement 101 as it is known from the state of the art. Such a circuit arrangement 101 is in essence a shift register comprising a multitude of cascaded D-flip-flops 103,1, ..., 103.n. An input signal to be filtered is conveyed over a data line 102 to the D-input of the first flip-flop 103.1. The input signal in this example is a 1 bit with oversampling. The input signal and the respective output signals of the flip-flop 103.1, ..., 103.n are branched off from the data line 102 and multiplied in multiplier stages 104.0, 104.1, ..., 104.n by respective filter coefficients, while the filter coefficients determine the impulse response of the FIR filter 101. The multiplied intermediate signals are added together in an addition stage 105 of which the result is an output signal on an output line 106. Thus the output signal is a weighted sum of the intermediate signals.

In the illustrative embodiment of a finite impulse response digital-to-analog converter (FIRDAC) from audio technology, which is designed for limited-bandwidth speech signals, the input signal is a digital 1-bit signal. Typically, between n = 50 and n = 150, preferably about n = 110 flip-flops 103.1, ..., 103.n, are used. The filter coefficients of the multiplier stages 104.0, 104.1 , ... , 104.n are implemented by differently scaled current sources (not shown). With 1-bit signals that are either zero or one, there is talk of a selection of the filter coefficients. The output signal is an analog current signal. The input signal is low-pass filtered simultaneously with the digital to analog conversion.

The flip-flops 103.1, ..., 103.n are clocked in parallel by a clock signal on a clock signal line 107. A respective clock generator (not shown) is typically an oscillator within or without the chip, whose clock is buffered in order to drive the large parallel (capacitive) load of all the flip-flops 103.1, ... , 103.n, for which purpose usually a series of inverters is used with rising transistor magnitude. The last stage of the clock generator output buffer may comprise for example a p-type MOS transistor having an 11 μm channel width and a .25μm channel length as well as an n-type MOS transistor having a 5μm channel width and a .25 μm channel length. A typical clock frequency is for example 1MHz. As described above a parallel clocking causes strong power impulses on the supply lines with undesired effects such as voltage breakdowns, signal distortions or antenna-like radiation of electromagnetic waves which take place in every clock cycle. Such current impulses in a state-of-the-art FIRDAC 101 are well visible in Fig. 6 in which the supply current in milliamperes is plotted against time in microseconds. Fig. 6(a) shows many power impulses in a relatively long time interval of about 140μs; Fig. 6(b) shows an about 4ns-long section of this. The power impulse shown in Fig. 6(b) has an amplitude of about -45mA and a half- power width of about 0.24ns. One would like to avoid such undesired effects or at any rate diminish them.

A method and a device for reducing supply current losses is described in US patent No. 6,100,752 (Lee et al.). This patent relates to a pump circuit for generating voltages that are considerably higher than the available supply voltage. This is achieved by cyclic charge transfers between capacitors. The circuit disclosed in said US patent includes two pump lines which can each be subdivided into a plurality of pump stages, and a clock signal line for supplying the pump stages with a clock signal. The clock signal line is then provided with a multiplicity of identical delay circuits which cause the clock signal to reach the respective subsequent pump stage with a delay. These delays reduce and divide the supply current impulses. This circuit, however, requires a large number of delay circuits, so that it becomes complex and expensive and requires a large surface. The delay circuits also have large power consumption. Furthermore, it may be considered that US patent No. 6,100,752 relates to a totally different type of circuits than the present invention as a result of which its teaching cannot be applied to shift registers. When delay circuits are installed in the clock signal line 107 of Fig. 1, there could be the danger of the data propagating over the data line 102 faster than the clock signal on the clock signal line 107; this could lead to a harming of the time- dependent signal sequence up to a taking over of the wrong data. Therefore, the delay circuits should be designed and manufactured extremely accurately then, which is well nigh impossible. In the pump circuit, however, there are no such problems with the time- dependent signal sequence. Therefore, it is an object of the invention to provide a shift register circuit arrangement with improved electromagnetic compatibility and a method of operating it, which do not have the disadvantages mentioned above. The circuit arrangement and the method should particularly be less complex and more cost effective than the solutions known from the state of the art, and nevertheless guarantee the desired time-dependent signal sequence.

These and other objects are achieved by the method and the circuit arrangement as they are defined in the independent patent claims. Advantageous embodiments are defined in the dependent claims.

The invention is based on the idea to pass the clock signal through the logic elements in series and to briefly buffer it in each individual logic element in lieu of driving all logic elements with it at the same time, that is to say in parallel. This provides a desired delay in each logic element. The buffers, which are required for this purpose, may be provided, for example, as two cascaded inverters and comprising very small transistors (that is, small width-to-length ratio W/L). Normally, such a buffer is already available in a flip- flop anyway, because of which they need not be rendered available especially for this purpose. Thanks to the solution according to the invention it is therefore not necessary to provide separate delay circuits.

The shift register circuit arrangement according to the invention comprises a plurality of cascaded logic elements connected together in pairs by a data line, which elements can be clocked by a clock signal over a clock signal line. The logic elements are then connected in pairs to each other in series by the clock signal line. The connection of the logic elements by the clock signal line is preferably such that a signal on the data line and the clock signal are propagated in opposite directions to adhere to the necessary setup and hold times. In the invented method of operating a shift register circuit arrangement with a plurality of sequentially cascaded logic elements connected together in pairs by a data line, a clock signal is passed through the logic elements in series for clocking the logic elements. The clock signal is preferably passed through the logic elements so that it propagates in opposite direction to a signal on the data line. The clock signal is preferably delayed in each logic element.

Preferred embodiments of the invention and the state of the art will be explained in more detail hereafter with reference to the drawings. A finite impulse response (FIR) filter will then be used as a concrete example; obviously, however, the invention is not restricted to FIR filters, but can be used in any shift register circuit arrangement, in which: Fig. 1 shows a circuit arrangement according to the state of the art; Fig. 2 shows a first embodiment of the circuit arrangement according to the invention;

Fig. 3 shows a second, preferred embodiment of the circuit arrangement according to the invention;

Fig. 4 shows a detailed view of the circuit arrangement shown in Fig. 3; Fig. 5 shows a simulation of the propagation of the clock signal in the circuit arrangement shown in Fig. 4;

Fig. 6 shows supply current impulses with a FIR according to the state of the art; and

Fig. 7 shows a simulation of the supply current in the circuit arrangement shown in Fig. 4.

A first, simple embodiment of the circuit arrangement 1 according to the invention is shown in Fig. 2. The most important elements of this circuit have already been explained with reference to Fig. 1 known from the state of the art and are referred to in Fig. 2 by analogous reference characters. In the circuit 1 according to the invention shown in Fig. 2 the clock signal is passed through the flip-flops 3.1, ..., 3.n in series in lieu of in parallel as shown in Fig. 1. The clock signal is thus buffered in each flip-flop 3.1, ... , 3.n and then undergoes a brief delay (see Fig. 5). The expensive delay circuits 108.1, ..., 108. (n-1) of Fig. 1 are not needed in the circuit arrangement according to the invention.

However, the embodiment of Fig. 2 does have a disadvantage. Since the data propagate on the data line 2 in the same direction and about equally fast as the clock signal on the clock signal line 7, it is possible that the setup and hold times are not adhered to. This may cause the circuit 1 to end up in undefined state. As is known, the setup time is the time preceding the active clock signal edge, during which a signal at the input of the flip-flop must not change, and the hold time the time during which the signal at the input of the flip-flop need not remain constant after the active clock signal edge. The disadvantage of the embodiment shown in Fig. 2 is eliminated in the preferred embodiment of Fig. 3. This embodiment too is based on the basic idea to pass the clock signal through the flip-flops 3.1, ... , 3.n in series. Contrary to Fig. 2, however, the propagation directions of the data signal and of the clock signal are each other's opposites, i.e. the clock signal is first fed to the backmost flip-flop 3.n, then to the backmost-but-one flip-flop 3. (n-1) etc. whereas the data signal from the foremost flip-flop 3.1 is led to the backmost flip-flop 3.n. This guarantees that the setup and hold times are adhered to.

Fig. 4 shows a detailed diagram of the circuit arrangement of Fig. 3 and also utilizes like reference characters for like elements. The multiplier stages 4.0, ..., 4.n occur twice in this example to be able to form difference signals for which the noise is reduced. PCEL1, ..., PCELOn are the instance names of the multiplier stages 4.0, ..., 4.n. The differential outputs of the multiplier stages 4.0, ..., 4.n are referred to as outn and outp. Differential output lines are referred to as 61 and 62. In the representation of Fig. 4 the data signal propagates on a data line 2 from left to right; the data input and data output of a flip- flop 3.1, ..., 3.n is referred to as d and q, respectively. The clock signal, on the other hand, propagates from right to left on a clock signal line 7; the clock signal input and clock signal output of a flip-flop 3.1, ..., 3.n is referred to as elk and clk_o, respectively. Two supply lines 91, 92 supply a fundamental voltage vss and ON or an operating voltage vdd, 2.5V, respectively, to the flip-flops 3.1, ..., 3.n.

Fig. 5 shows a simulation of the propagation of the clock signal in the circuit arrangement of Fig. 4 in a representation in which the clock signal voltage in volts is plotted against the time in microseconds. The leading edge 70.0 corresponds to the ingoing clock signal. The second edge 70.1 corresponds to the clock signal to the first flip-flop 3.1, the third edge 70.2 corresponds to the clock signal to the second flip-flop 3.2 and the last edge 70.n corresponds to the clock signal to the last flip-flop 3.n. This simulation provides a propagation time of the clock signal of 9.43ns between the n = 110 flip-flops of the circuit arrangement 1, which corresponds to a clock signal delay of .086ns per flip-flop.

Fig. 7 shows a simulation of the supply current in the supply line 92 of the circuit arrangement of Fig. 4 in which the current in milliamperes is plotted against time in microseconds. A comparison of Fig. 7 with Fig. 6 shows the advantages of the invention over the state of the art. In the circuit arrangement 1 according to the invention there is a power impulse about every 600μs having an amplitude of about -2mA, as may be seen from Fig. 7(a); this amplitude is smaller than in the state of the art (Fig. 6) by a factor of about 20. Further consideration of such a power impulse, as effected in Fig. 7(b), shows that the power impulse is composed of high-frequency oscillations all right, but whose amplitude is only about .7 mA, thus almost two orders of magnitude smaller than in the state of the art.

The invention thus causes a reduction to occur of the power impulses by at least a factor of 20 in that the currents are distributed in a time-dependent manner by clocking the logic elements in series. This extends the duration of the power impulses and thus considerably reduces the cause of the undesired noise. This is an important step in the development of integrated circuits, for example for audio technology or mobile telephony. Here the electromagnetic compatibility and the signal quality play an important role, as is known. The reduction of the power impulses may also be accompanied with power saving and an extension of the useful life of a battery, but at most as a secondary effect.

Claims

CLAIMS:

1. A shift register circuit arrangement comprising a plurality of sequentially cascaded logic elements connected to each other in pairs by a data line, which elements can be clocked by a clock signal over a clock signal line, in which the logic elements are connected together in pairs in series by the clock signal line.

2. A circuit arrangement as claimed in claim 1, in which the logic elements are connected together by the clock signal line such that a signal on the data line and the clock signal are propagated in opposite directions.

3. A circuit arrangement as claimed in one of the preceding claims, in which the logic elements are flip-flops and preferably D-flip-flops.

4. A circuit arrangement as claimed in one of the preceding claims, in which the circuit arrangement comprises a finite impulse response filter and preferably a finite impulse response digital-to-analog converter.

5. A circuit arrangement as claimed in claim 4, in which the circuit arrangement comprises a multiplicity of multiplier stages for multiplying intermediate signals branched off from the sequentially cascaded logic elements by filter coefficients as well as an adder stage for adding together the multiplied intermediate signals.

6. A circuit arrangement as claimed in one of the preceding claims, in which the circuit arrangement comprises between 50 and 150, preferably 1 10, logic elements.

7. A circuit arrangement as claimed in one of the preceding claims, in which each logic element comprises a buffer element for buffering the clock signal, preferably two cascaded inverters.

8. A method of operating a shift register circuit arrangement comprising a plurality of sequentially cascaded logic elements connected to each other in pairs by a data line, in which a clock signal is passed though the logic elements in series to clock the logic elements.

9. A method as claimed in claim 8, in which the clock signal is passed through the logic elements such that it is propagated in opposite direction to a signal on the data line.

10. A method as claimed in claim 8 or 9, in which the clock signal is delayed in each logic element.