JP5037800B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device equipped with a digital circuit having one or more circuit blocks, and in particular, reduces power consumption in distributing clocks and data to these circuit blocks and reduces noise generated by the circuit itself. The present invention relates to a semiconductor device suitable for reducing the skew between the clock and data.

In recent years, with the miniaturization of semiconductor devices, the circuit scale mounted on one chip of an LSI has increased, and distribution of clocks and data has become increasingly difficult.
For clock and data distribution, it is desirable that the propagation delay time is small, the skew between the clock and data is small, the power consumption is small, and the noise generated by the distribution circuit itself is small. Off and clock and data distribution are realized.

Here, generally used clock distribution methods are shown in FIGS.
FIG. 8 is a general circuit image of the clock distribution method, and FIG. 9 is an example of a general layout of the clock distribution method in the semiconductor device.
The clock distribution system shown in FIGS. 8 and 9 is a clock distribution structure called an H-Tree structure. This is a method of increasing the distribution to the reverse tournament type, with the same fan delay and wiring load at the distribution destination, and the same wiring delay and load capacity, so that the difference in delay time of the distribution path can be reduced. They are the same (for example, refer to Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 10-275862 JP 2005-123347 A

However, the above-described H-Tree structure has the following problems.
For example, since a long-wiring or large fan-out circuit is driven using a buffer with high driving capability, the current consumption is concentrated in time as shown in FIG. 10, and the frequency band that cannot be compensated by the bypass capacitor is large. It was generating noise.

  In addition, when the clock distribution range is wide, the number of buffer stages increases, and the distribution circuit alone may have a propagation delay time of several ns. In particular, in CMOS circuits, delay time fluctuations of 0.07% to 0.10% occurred with respect to voltage fluctuations of 1 mV.

In addition, when data is distributed in conjunction with clock distribution, the fanout of data is often smaller than that of the clock, but the number of signals to be distributed is large. Therefore, in order to reduce SKEW, It is difficult to make them the same.
This is a cause of narrowing the eye opening (eye opening) because the ratio of the fluctuation of the delay time to the voltage fluctuation described above also changes when the circuit is different.
Here, the eye opening refers to an opening portion (a central opening portion shaped like an eye) formed at the center of the waveform among the waveforms formed by superimposing clock waveforms for each period.

  The present invention has been made to solve the above-described problems. In the distribution of clocks and data, data can be transmitted and distributed without narrowing the eye opening, and operation-dependent power consumption (AC component) is achieved. An object of the present invention is to provide a semiconductor device that can realize a clock distribution technique that can reduce the noise generated by the mounted circuit itself and reduce the noise generated by the mounted circuit itself.

  In order to achieve this object, the semiconductor device of the present invention includes one or more circuit blocks, a clock wiring for distributing a clock to each of these circuit blocks, and each of one or more circuit blocks. The clock wiring has a clock buffer for giving a predetermined delay amount to the clock, and the data wiring has a data delay for giving the data a predetermined delay amount. The semiconductor device has a buffer, and includes a control signal wiring for sending a delay time control signal for giving the same propagation delay time to each stage of the clock buffer and each stage of the data buffer. .

When the semiconductor device has such a configuration, the propagation delay time of each stage of the clock buffer and each stage of the data buffer is controlled to be the same. The stage power consumption is equal. For this reason, the power consumption is distributed in the time direction to form a rectangular wave, and noise can be reduced or the frequency component of noise can be reduced.
Then, due to the noise reduction or the like, the fluctuation (variation) in the time direction of the data waveform is reduced, so that data can be propagated and distributed while securing the eye opening.

  In the semiconductor device of the present invention, the clock wiring connects the clock main path for transmitting the clock and the clock main path for each circuit block, and sends the clock from the clock main path to the circuit block. The clock main path has a clock branch point where the clock branch path branches, the clock buffer is connected between each of the clock branch points in the clock main path, and the data wiring is data for transmitting data A data branch path that connects the main path and the data main path for each circuit block and sends data from the data main path to the circuit block is provided, and the data main path is a data branch point where the data branch path branches And the data buffer is connected between the data branch points in the data main path.

  If the semiconductor device has such a configuration, the power consumption of each stage of the clock buffer and data buffer becomes equal, and the power consumption is distributed in the time direction to form a rectangular wave, which is generated in the distribution circuit. The frequency component of noise can be reduced, and the noise peak can be reduced. Then, by reducing the noise, variation in the time direction of the data waveform is suppressed, so that data can be distributed while securing the eye opening.

  In the semiconductor device of the present invention, the clock branch path includes a clock branch path buffer, the data branch path includes a data branch path buffer, and the control signal wiring propagates a clock propagated by the clock branch path. The delay time control signal is applied to the clock branch path buffer and the data branch path buffer so that the delay time and the propagation delay time of the data propagated by the data branch path are the same.

  When the semiconductor device has such a configuration, a buffer for compensating the skew between the clock and the data is inserted in the clock branch or the data branch, so that the skew between the clock and the data distributed over the entire chip is suppressed. it can.

  In the semiconductor device of the present invention, the clock wiring includes a clock return path for returning the clock propagated through the clock main path, and the semiconductor device is output from the clock input to the clock main path and the clock return path. A delay lock loop circuit is provided that inputs a clock, generates a delay time control signal, and sends it to the control signal wiring.

When the semiconductor device has such a configuration, the delay time control signal (BIAS) used for the clock buffer and the data buffer can be generated by the delay lock loop circuit. The delay lock loop circuit can control the delay time of the distribution circuit to be an integral multiple of the clock cycle.
In addition, the power consumption of each stage of the clock buffer and the data buffer is made equal, and the delay time of the distribution circuit is controlled to be an integral multiple of the clock cycle. It becomes flat in the direction, and noise can be reduced.
Furthermore, since the delay lock loop circuit controls, the delay time of the distribution circuit can be kept constant because it follows even when an external power supply voltage fluctuation or temperature fluctuation occurs.

  In the semiconductor device of the present invention, the clock return path includes a return path buffer, and the control signal wiring includes a clock propagation delay time propagated by the clock main path and a clock propagation delay propagated by the clock return path. The delay time control signal is provided to the clock buffer and the return path buffer so that the time is the same.

  When the semiconductor device has such a configuration, the power consumption of each stage of the clock buffer and the data buffer is equalized, and the delay time of the distribution circuit is controlled to be an integral multiple of the clock cycle. The power consumption is distributed in the time direction to form a rectangular wave, the frequency component of noise generated in the distribution circuit can be lowered, and the noise peak can be reduced.

As described above, according to the present invention, the buffer is connected to the data wiring as well as the clock wiring, and the propagation delay time of each stage of the clock buffer and the data buffer is made the same, so that Therefore, the power consumption can be distributed in the time direction. As a result, the waveform of the power consumption becomes a rectangular wave, the frequency component of the noise generated in the distribution circuit can be lowered, and the noise peak can be reduced.
In addition, since the delay time control signal is applied so that the propagation delay time of the clock and the data is the same, the influence of the variation in the data waveform is reduced, so that data can be distributed while securing the eye opening. it can.

Furthermore, the generation of noise can be suppressed by controlling the propagation delay time of the clock distribution circuit to be an integral multiple of the clock period by generating the bias used for the buffer by the delay lock loop circuit. In addition, since the delay time control signal is generated by the delay lock loop circuit, the delay time of the distribution circuit can be kept constant because it follows even when an external power supply voltage fluctuation or temperature fluctuation occurs.
Further, by connecting a buffer for compensating the skew between the clock and the data to the clock branch or the data branch, the skew between the clock distributed to the entire chip and the data can be suppressed.

  Hereinafter, a preferred embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

[First embodiment]
First, a first embodiment of a semiconductor device of the present invention will be described with reference to FIG.
FIG. 2 is a circuit diagram showing a configuration of a digital circuit mounted on the semiconductor device of the present embodiment.
As shown in the figure, the digital circuit 1a mounted on the semiconductor device of the present embodiment includes circuit blocks 10-1 to 10-n, a clock wiring 20, a data wiring 30, a bias wiring 40, and data holding. A circuit 50 is provided.

One or two or more circuit blocks 10-1 to 10-n are provided in the digital circuit 1a. The first holding circuits 11-1 to 11-n, the logic circuits 12-1 to 12-n, And two holding circuits 13-1 to 13-n.
The first holding circuits 11-1 to 11-n receive data from the data wiring 30. Then, a clock is input from the clock wiring 20, and data is output based on the input timing of this clock. The output data is sent to the logic circuits 12-1 to 12-n. Note that the first holding circuits 11-1 to 11-n can be configured by, for example, flip-flops or latch circuits.

The logic circuits 12-1 to 12-n receive data output from the first holding circuits 11-1 to 11-n and output a predetermined signal (in this embodiment, output data). This output data is sent to the second holding circuits 13-1 to 13-n. The configuration of the logic circuits 12-1 to 12-n is arbitrary and is not limited to a specific circuit.
The second holding circuits 13-1 to 13-n receive signals (output data) output from the logic circuits 12-1 to 12-n. Then, a clock is input from the clock wiring 20, and a signal (output data) is output based on the input timing of this clock. Note that the second holding circuits 13-1 to 13-n can be configured by, for example, flip-flops or latch circuits.

The clock wiring 20 is a wiring for distributing a clock to each of the circuit blocks 10-1 to 10-n, and has a clock main path 21 and a clock branch path 22.
The clock main path 21 is a path for transmitting a clock input from the clock input terminal 23.
The clock branch path 22 is a path that connects the clock main path 21 to each of the circuit blocks 10-1 to 10-n, and is clocked from the clock main path 21 to the circuit blocks 10-1 to 10-n. Is to send.

The clock main path 21 has a clock branch point 24 that is a point where the clock branch path 22 branches, that is, a point where the clock main path 21 and the clock branch path 22 are connected.
A clock buffer 25 is connected (inserted) between each of a plurality of clock branch points 24 in the clock main path 21.

The clock buffer 25 is a buffer for giving a predetermined delay amount to the clock.
The clock buffer 25 is also connected between the clock input terminal 23 and the clock branch point 24 closest to the clock input terminal 23.
The configuration of the clock buffer 25 will be described later in “About Configuration of Clock Buffer and Data Buffer”.

The data line 30 is a line for distributing data to each of the circuit blocks 10-1 to 10-n, and includes a data main path 31 and a data branch path 32.
The data main path 31 is a path for transmitting data input from the data input terminal 33.
The data branch path 32 is a path that connects the data main path 31 to each circuit block 10-1 to 10-n, and data is transferred from the data main path 31 to each circuit block 10-1 to 10-n. Is to send.

The data main path 31 has a data branch point 34 that is a point where the data branch path 32 branches, that is, a point where the data main path 31 and the data branch path 32 are connected.
A data buffer 35 is connected (inserted) between each of a plurality of data branch points 34 in the data main path 31.

The data buffer 35 is a buffer for giving a predetermined delay amount to the data.
The data buffer 35 is also connected between the data input terminal 33 and the data branch point 34 closest to the data input terminal 33.
The configuration of the data buffer 35 will be described later in “Configuration of Clock Buffer and Data Buffer”.

The bias wiring (control signal wiring) 40 is a path for supplying a delay time control signal (BIAS) to each stage of the clock buffer 25 and the data buffer 35.
By giving the delay time control signal, the propagation delay time of each stage of the clock buffer 24 and the data buffer 34 is made the same. Thereby, the difference (variation) in the time direction of the data waveform input to each of the circuit blocks 10-1 to 10-n is reduced, and the data can be propagated and distributed while the eye opening is secured.
The configuration of the circuit that provides the delay time control signal will be described in the following “Configuration of Clock Buffer and Data Buffer”.

  The data holding circuit 50 inputs data and outputs the data at the timing when the clock is input.

Next, the configuration of the clock buffer and the data buffer will be described with reference to FIG.
FIG. 2 is a circuit diagram showing a configuration example of a buffer (including both a clock buffer and a data buffer). FIG. 1A is a single simplified delay circuit, and FIG. 1 shows a single delay circuit, and FIG. 3C shows a differential delay circuit. Note that the buffer can be configured by any one of (a), (b), and (c) in FIG.

The single simplified delay circuit has a P-channel MOSFET and an N-channel MOSFET as shown in FIG.
The drain of the N channel MOSFET and the source of the P channel MOSFET are connected, the source of the N channel MOSFET is grounded, and a predetermined voltage is applied to the drain of the P channel MOSFET. Further, BIASP is input to the gate of the P-channel MOSFET, and a signal (clock in the clock path and data in the data path) is input to the gate of the N-channel MOSFET (In). A signal delayed based on BIASP (clock in the clock path and data in the data path) is output from the connection point between the drain of the N-channel MOSFET and the source of the P-channel MOSFET (Out).

The single delay circuit has two P-channel MOSFETs and two N-channel MOSFETs as shown in FIG.
The source of the first P-channel MOSFET and the drain of the second P-channel MOSFET are connected, the source of the second P-channel MOSFET and the drain of the first N-channel MOSFET are connected, and the first N-channel MOSFET The source and the drain of the second N-channel MOSFET are connected. The source of the second N-channel MOSFET is grounded, and a predetermined voltage is applied to the drain of the first P-channel MOSFET. Furthermore, BIASPx is input to the gate of the first P-channel MOSFET, BIASNx is input to the gate of the second N-channel MOSFET, and a signal (clock) is input to the gate of the second P-channel MOSFET and the gate of the first N-channel MOSFET. The clock is input to the path and the data is input to the data path (In). A signal delayed based on BIASPx and BIASNx (clock in the clock path and data in the data path) is output from the connection point between the source of the second P-channel MOSFET and the drain of the first N-channel MOSFET (Out ).
That is, the single delay circuit has a CMOS inverter in the middle and a current source on both sides thereof.

As shown in FIG. 2C, the differential delay circuit combines two single simplified delay circuits to connect the sources of each N-channel MOSFET, and a predetermined voltage is applied to the drain of each P-channel MOSFET. Each is applied. Further, the drain of the third N-channel MOSFET is connected to the point where the sources of the N-channel MOSFETs are connected to each other, and the source of the third N-channel MOSFET is grounded.
Further, a signal (one is INP and the other is INN) is input to the gates of the N-channel MOSFETs of the two single simplified delay circuits, and a signal (BIASPx or Vss) is input to the gate of each P-channel MOSFET of the single simplified delay circuit. Is entered.
Then, the signal Q is output from one of the two single simplified delay circuits, and the signal XQ is output from the other.

Here, the operation of the single delay circuit will be further described.
When the inverter in the middle of the single type delay circuit transitions to Hi, a current flows from the Hi-side current source (first P-channel MOSFET) to the load (Out), and the load capacitance is charged. On the other hand, when the transition is made to the Low side, this time, the transition is made from the load side to the power source side by releasing current. MOSFETs connected to both sides of the single-type delay circuit are used as current sources for these flowing currents, and they are intended to be controlled so as to flow currents when charged and discharged.
A bias source of a certain kind is connected to the current source, and the current source is connected to the transistor at the final stage of the bias source. Since the current mirror is connected, the current flowing in one bias generator is mirrored, mirrored, and limited by the current close to the bias current in all transistors. This means that the charging current is controlled with respect to the load capacity.

Next, the operation result of the semiconductor device of this embodiment will be described with reference to FIG.
The figure shows the clock input ((a) Clock in), output ((b) Clock Out (circuit Block In)), and power consumption (when the digital circuit mounted on the semiconductor device of this embodiment is operated. (C) Clock distribution current consumption).

In the digital circuit 1a mounted on the semiconductor device of this embodiment, the power consumption in the buffers (the clock buffer 25 and the data buffer 35) is equal at each stage. For this reason, as shown in FIG. 3, the power consumption is distributed in the time direction and becomes a rectangular wave shape. Thereby, since the frequency component of the noise generated in the distribution circuit is lowered, the peak of the noise can be reduced as can be seen by comparing FIG. 10 and FIG.
Since noise can be suppressed in this way, the influence of fluctuation (variation) in the time direction of the data waveform as shown in FIG. 4 can be reduced. For this reason, it is possible to propagate and distribute data while ensuring the eye opening.

[Second Embodiment]
Next, a second embodiment of the semiconductor device of the present invention will be described with reference to FIG.
FIG. 2 is a circuit diagram showing a configuration of a digital circuit mounted on the semiconductor device of the present embodiment.
This embodiment is different from the first embodiment in that a clock return path for returning a clock and a delay lock loop circuit (DLL) that outputs a delay time control signal are newly provided. Other components are the same as those in the first embodiment.
Therefore, in FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 5, the digital circuit 1b mounted on the semiconductor device of this embodiment includes a plurality of circuit blocks 10-1 to 10-n, a clock wiring 20, a data wiring 30, a device path 40, A data holding circuit 50 and a DLL 60 are provided.
Here, the clock wiring 20 has a clock main path 21, a clock branch path 22, a clock input terminal 23, a clock branch point 24, a clock buffer 25, and a clock return path 26.
The clock return path 26 is a path for returning the clock propagated to the end of the clock main path 21 to the vicinity of the clock input terminal 23. The starting point of the clock return path 26 may be on the clock main path 21 or on the clock branch path 24.

On the clock return path 26, a clock buffer (return path buffer) 27 is connected.
The return path buffer 27 is connected to each stage of the clock buffer 24 connected to the clock main path 21. That is, the clock buffer 24 and the return path buffer 27 have the same number of stages.
The clock buffer 24 and the return path buffer 27 have the same number of stages, and the propagation delay time of the clock is the same in each stage by the delay time control signal (BIAS). Therefore, the power consumption in each stage of the clock buffer 24 and the return path buffer 27 is equal.

As shown in FIG. 5, the DLL (Delay Lock Loop) 60 includes a phase comparator (PD) 61, a counter (CTR) 62, and a DA converter (DAC) 63.
The phase comparator 61 inputs the clock (transmission clock) input to the clock main path 21 and the clock (return clock) returned by the clock return path 26, detects the phase between these signals, The detection result is output as a phase signal.
The counter 62 receives the phase signal from the phase comparator 61 and generates and outputs a control signal based on the phase signal.

The DA converter 63 performs digital-analog conversion on the control signal from the counter 62 and outputs it as a delay time control signal (BIAS signal). The BIAS signal is propagated through the bias path 40 and is supplied to the clock buffer 25, the data buffer 35, and the return path buffer 27.
With this configuration, the DLL 60 controls the BIAS signal so that the propagation delay time in the clock wiring 20 is an integral multiple of the clock period.

By applying the delay time control signal (BIAS signal) generated by the DLL 60 to each stage of the clock buffer 25, the data buffer 35, and the return path buffer 27, the power consumption of these stages can be made equal. it can. Further, since the propagation delay time in the clock wiring 20 is controlled to be an integral multiple of the clock cycle, the waveform of the current consumption becomes flat as shown in FIG. For this reason, generation | occurrence | production of the noise in a clock wiring can be suppressed.
In the DLL 60, a transmission clock and a return clock are input. The return clock is normally input to the DLL 60 with a delay of exactly one cycle from the transmission clock. The phase comparator 61 compares the phases of the transmission clock and the return clock to determine whether the return clock is ahead or behind one cycle of the transmission clock, and sends a signal indicating the result to the counter 62. send. The counter 62 counts up or down based on the signal. The DAC 63 outputs a delay or advance signal (BIAS signal) based on the count value of the counter 62. As a result, the return clock is adjusted to be input to the DLL 60 with a delay of exactly one cycle of the transmission clock. That is, the DLL 60 controls the BIAS signal so that the propagation delay time in the clock wiring 20 is an integral multiple of the clock period.

6 shows the clock ((a) Clock In) input to the clock main path 21, the clock ((b) Clock Out (circuit Block In)) output from the clock main path 21, and the consumption in the clock wiring 20. It is a wave form diagram which shows each waveform of an electric current ((c) Clock distribution consumption current), respectively.
In the figure, for example, the first clock is delayed by a predetermined time by the clock buffer 25 from being inputted to the clock main path 12 until being outputted (FIGS. 4A and 4B). In the meantime, it can be understood from (c) that the current consumption is suppressed in the clock main path 21.

  Furthermore, since the delay time of the buffer is controlled by the DLL, the delay time in the clock wiring can be kept constant because it follows even if an external power supply voltage fluctuation or temperature fluctuation occurs.

[Third embodiment]
Next, a third embodiment of the semiconductor device of the present invention will be described with reference to FIG.
FIG. 2 is a block diagram showing a configuration of a digital circuit mounted on the semiconductor device of this embodiment.
Compared with the first embodiment, the present embodiment is newly provided with a clock return path for returning a clock and a DLL for sending a delay time control signal. The difference is that a buffer is connected to. Other components are the same as those in the first embodiment.
Therefore, in FIG. 7, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 7, the digital circuit 1c mounted on the semiconductor device of the present embodiment includes a plurality of circuit blocks 10-1 to 10-n, a clock wiring 20, a data wiring 30, a bias wiring 40, The data holding circuit 50 and the DLL 60 are provided.
Buffers 28-1 to 28-n are connected to the clock branch path 22 of the clock wiring 20, respectively. In addition, buffers 38-1 to 38-n are connected to the data branch path 32 of the data wiring 30. The buffers 28-1 to 28-n and the buffers 38-1 to 38-n are connected to compensate for the skew between the circuit blocks 10-1, 10-2,.

The number of buffers 28-1 to 28-n connected to each clock branch path 22 is different. Similarly, the number of buffers 38-1 to 38-n connected to each data branch path 32 is different.
For example, when there are n clock buffers 25 (data buffers 35) connected to the clock main path 21 (data main path 31), the clock branch point 24 (closest to the clock input terminal 23 (data input terminal 33)) N-1 buffers 28-1 (buffer 38-1) are connected to the clock branch path 22 (data branch path 32) connected to the data branch point 34).

Subsequently, n-2 buffers 28-2 (buffers 38-2) are connected to the clock branch path 22 (data branch path 32) connected to the next closest clock branch point 24 (data branch point 34). Is done.
Thereafter, as the distance from the clock input terminal 23 (data input terminal 33) increases, the number of buffers 28 (buffers 38) included in each clock branch path 22 (data branch path 32) decreases by one.

Then, zero buffer 28 (buffer 38) is connected to the clock branch path 22 (data branch path 32) connected to the farthest clock branch point 24 (data branch point 34). That is, the buffer 28 (buffer 38) is not connected to the clock branch path 22 (data branch path 32).
In FIG. 7, for convenience of description, the symbol of the buffer 28-n (buffer 38-n) is shown, and “× 0” indicating that the buffer 28-n (buffer 38-n) is zero. Is described.

  The configuration and functions of the clock return path 26, return path buffer 27, and DLL 60 in the present embodiment are the same as the configuration and functions of the clock return path 26, return path buffer 27, and DLL 60 in the second embodiment.

  According to the semiconductor device of the present embodiment having the above-described configuration, since the buffer for compensating the skew between the clock and the data is inserted in the clock branch and the data branch, the clock distributed to the entire chip and SKEW between data can be suppressed.

The preferred embodiments of the semiconductor device of the present invention have been described above. However, the semiconductor device according to the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention. Needless to say.
For example, in the above-described embodiment, the clock main path or the data main path is shown as a straight line. However, on the semiconductor device, the clock main path or the data main path is not limited to being arranged in a straight line, but at a right angle or the like. It can also contain bent parts.

  The semiconductor device of the present invention may be an arbitrary combination of the semiconductor devices in each of the first embodiment, the second embodiment, and the third embodiment.

  Since the present invention relates to a digital circuit mounted on a semiconductor device, it can be used in the technical field related to a digital circuit or a semiconductor device.

It is a circuit diagram which shows the structure of the digital circuit mounted in the semiconductor device concerning 1st embodiment of this invention. FIG. 2 is a circuit diagram illustrating a configuration example of a buffer, in which (a) is a circuit diagram of a single simplified delay circuit, (b) is a circuit diagram of a single delay circuit, and (c) is a circuit diagram of a differential delay circuit. Respectively. FIG. 2 is a waveform diagram showing waveforms of clock input and output in the digital circuit shown in FIG. 1 and current consumption in clock wiring. FIG. 2 is a waveform diagram showing waveforms of clock and data input and clock and data output in the digital circuit shown in FIG. 1. It is a circuit diagram which shows the structure of the digital circuit mounted in the semiconductor device concerning 2nd embodiment of this invention. 6 is a waveform diagram showing waveforms of clock input and output in the digital circuit shown in FIG. 5 and current consumption in the clock wiring. FIG. It is a circuit diagram which shows the structure of the digital circuit mounted in the semiconductor device concerning 3rd embodiment of this invention. It is a circuit diagram which shows the general circuit image of the conventional clock distribution system. It is a circuit diagram which shows the example of the general layout of the clock distribution system in the conventional semiconductor device. FIG. 10 is a waveform diagram illustrating waveforms of clock input, output, and current consumption in clock wiring in the clock distribution method illustrated in FIG. 9.

Explanation of symbols

1a, 1b, 1c Digital circuit (semiconductor device)
10-1 to 10-n Circuit block 20 Clock wiring 21 Clock main path 22 Clock branch path 23 Clock input terminal 24 Clock branch point 25 Clock buffer 26 Clock return path 27 Return path buffer 28 Branch path buffer 30 Data line 31 Data main path 32 Data branch path 33 Data input terminal 34 Data branch point 35 Data buffer 36 Data return path 37 Return path buffer 38 Branch path buffer 40 Bias wiring (control signal wiring)
50 data holding circuit 60 DLL (delay lock loop circuit)

Claims (3)

A semiconductor device comprising one or more circuit blocks, a clock wiring that distributes a clock to each of these circuit blocks, and a data wiring that distributes data to each of the one or more circuit blocks Because
The clock wiring connects a clock buffer that gives a predetermined delay amount to the clock, a clock main path that transmits the clock, and the clock main path for each of the circuit blocks. A clock branch for sending the clock from the path to the circuit block;
The clock main path has a clock branch point where the clock branch path branches,
The clock buffer is connected between each of the clock branch points in the clock main path,
The clock branch path includes a clock branch path buffer;
The data line connects a data buffer that gives a predetermined delay amount to the data, a data main path that transmits the data, and the data main path for each circuit block, and the data main line A data branch path for sending the data from the path to the circuit block;
The data main path has a data branch point where the data branch path branches,
The data buffer is connected between each of the data branch points in the data main path,
The data branch path includes a data branch path buffer;
The semiconductor device is:
A control signal wiring for supplying a predetermined bias signal serving as a delay time control signal is provided to each stage of the clock buffer and each stage of the data buffer, and the clock signal is provided by applying the bias signal. The buffer for each stage for data and data is controlled so that the propagation delay time is the same,
The control signal wiring includes the clock branch path buffer and the data branch so that the propagation delay time of the clock propagated by the clock branch path is the same as the propagation delay time of the data propagated by the data branch path. A semiconductor device characterized in that a delay time control signal is given to a road buffer . The clock wiring includes a clock return path for returning a clock propagated through the clock main path,
The semiconductor device includes a delay lock loop circuit that inputs a clock input to the clock main path and a clock output from the clock return path, generates the delay time control signal, and transmits the delay time control signal to the control signal wiring. The semiconductor device according to claim 1 . The clock return path includes a return path buffer;
The control signal wiring includes the clock buffer and the return path buffer so that the propagation delay time of the clock propagated through the clock main path and the propagation delay time of the clock propagated through the clock return path are the same. The semiconductor device according to claim 2 , wherein a delay time control signal is applied to.

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