WO2004012487A1 - Method of manufacturing printed wiring boards and substrate used for the method - Google Patents

Method of manufacturing printed wiring boards and substrate used for the method Download PDF

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Publication number
WO2004012487A1
WO2004012487A1 PCT/JP2002/007684 JP0207684W WO2004012487A1 WO 2004012487 A1 WO2004012487 A1 WO 2004012487A1 JP 0207684 W JP0207684 W JP 0207684W WO 2004012487 A1 WO2004012487 A1 WO 2004012487A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
thin
walled portion
conductive layer
circuit patterns
Prior art date
Application number
PCT/JP2002/007684
Other languages
French (fr)
Inventor
Nobuhiro Yoshioka
Toshiyuki Suzuki
Original Assignee
Matsushita Electric Works, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works, Ltd. filed Critical Matsushita Electric Works, Ltd.
Priority to PCT/JP2002/007684 priority Critical patent/WO2004012487A1/en
Priority to AU2002319914A priority patent/AU2002319914A1/en
Publication of WO2004012487A1 publication Critical patent/WO2004012487A1/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/241Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0293Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0284Details of three-dimensional rigid printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0191Dielectric layers wherein the thickness of the dielectric plays an important role
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09036Recesses or grooves in insulating substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09045Locally raised area or protrusion of insulating substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09118Moulded substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09127PCB or component having an integral separable or breakable part
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0736Methods for applying liquids, e.g. spraying
    • H05K2203/0746Local treatment using a fluid jet, e.g. for removing or cleaning material; Providing mechanical pressure using a fluid jet
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17Post-manufacturing processes
    • H05K2203/175Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0029Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/005Punching of holes

Definitions

  • the present invention relates to a method of efficiently manufacturing printed wiring boards having a plurality of circuit patterns electrically isolated from each other, and a substrate used for the method.
  • a metal thin film is first formed on a substrate, and required regions of the metal thin film are removed to obtain a pattern of the metal thin film on the substrate. Then, electroplating is performed to form an additional metal film on the pattern of the metal thin film, so that circuit patterns having a desired thickness is obtained on the substrate.
  • the electroplating step becomes very complicated.
  • a circuit pattern 20S is electrically insulated from the circuit pattern 22S on an insulating substrate 1S, as shown in FIG. 18, it is required to individually perform electroplating with respect to each of these circuit patterns to form the addition metal film.
  • an increase in manufacturing cost is caused by an extension of time required for the electroplating step.
  • a quality of the plating solution must be very often checked.
  • US Patent No. 5,494, 781 discloses an improved method of manufacturing a printed wiring board. According to this method, it is possible to simultaneously form the additional metal film on the isolated circuit patterns by electroplating without supplying electric current to the isolated circuit patterns through the feeder circuits. That is, as shown in FIG. 19A, by pattering a metal thin film formed on a substrate (not shown), circuit patterns (30P, 32P) isolated from each other and a conductive layer 40P extending therebetween are provided on the substrate.
  • electroplating is performed by the passage of electric current through the isolated circuit patterns (30P, 32P) connected by the conductive layer 40P to simultaneously form an additional metal film 50P on these circuit patterns, as shown in FIG. 19B.
  • the additional film 50P is not formed on the conductive layer.
  • the resist film 90P is removed to expose the conductive layer 40P, and then the conductive layer 40P is removed by soft etching to make electrical insulation between the isolated circuit patterns (30P, 32P), as shown in FIG. 19C.
  • the step of forming the resist film 90P on the conductive layer 40P since the step of forming the resist film 90P on the conductive layer 40P is needed, it consequently leads to an (increase in production cost. In particular, when forming a three-dimensional circuit pattern on a substrate for MID (molded interconnect device), or manufacturing a high-density printed wiring board, the difficulty of forming the resist film on the conductive layer comes into a problem. In addition, when the removal of the conductive layer 40P after the electroplating is not enough, there is a fear that insulation failure occurs.
  • Japanese Patent Early Publication [kokai] No. 10-93225 discloses a method of manufacturing a printed wiring board, which includes the capability of efficiently forming a conductive pattern by electroplating at a relatively low cost.
  • this method as shown in FIG. 20A, an adhesive layer 10R for electroless plating and a plating resist layer 20R are formed on a substrate 1R. Then, required portions of the plating resist layer 20R is removed to expose the adhesive layer 10R. On this exposed adhesive layer 10R, conductive patterns 8R, pad 7R and lead 9R for electroplating performed later are formed by electroless plating (FIG. 20B).
  • FIG. 20A an adhesive layer 10R for electroless plating and a plating resist layer 20R are formed on a substrate 1R. Then, required portions of the plating resist layer 20R is removed to expose the adhesive layer 10R. On this exposed adhesive layer 10R, conductive patterns 8R, pad 7R and lead 9R for electroplating performed later are formed by electroless plating (FIG. 20B
  • electroplating is performed by the passage of electric current through the lead 9R to form a thick metal film 50R on the conductive patterns 8R, the pad 7R and the lead 9R.
  • electrical insulation between the conductive patterns 8R and the lead 9R is obtained by punching or etching the pad 7R with the thick metal film 50.
  • the numeral 40R designates a through hole formed in the substrate 1R by the punching step.
  • a resist material is applied on an insulating substrate to expose required regions of the insulating substrate, and then a catalyst treatment for electroless plating is performed. After the resist is removed, a metal thin film is formed on the required regions by electroless plating to obtain electric pathway portions and electric-pathway connecting portions on the insulating substrate. Subsequently, electroplating is performed by the passage of electric current through the metal thin film to form an additional metal film on the electric pathway portions and the electric- pathway connecting portions.
  • the electric- pathway connecting portions with the additional metal film are removed by means of die-cutting or drilling, to thereby obtain a plurality of circuit patterns, i.e., the electric pathway portions with the additional metal film, that are electrically isolated from each other.
  • a concern of the present invention is to provide a method of manufacturing a printed wiring board having a plurality of circuit patterns electrically insulated from each other, which includes the capability of improving manufacturing yield and efficiently forming a metal film by electroplating.
  • the method of the present invention is characterized by comprising the steps of: providing a substrate with a thin-walled portion; forming a first circuit pattern on the substrate; forming a second circuit pattern isolated from the first circuit pattern on the substrate; forming a conductive layer on the thin-walled portion to make a temporary electrical connection between the first and second circuit patterns; performing electroplating by the passage of electric current through the first and second circuit patterns connected by the conductive layer to simultaneously form a metal film on the first and second circuit patterns; and after the electroplating, removing the thin-walled portion with the conductive layer to provide an electrical insulation between the first and second circuit patterns.
  • the conductive layer is formed on the thin-walled portion, it is possible to readily and efficiently remove the thin-walled portion with the conductive layer by means of punching, drilling and so on after the electroplating.
  • mechanical damages and shocks given to the substrate at the time of removing the thin-walled portion decrease, it is possible to prevent the propagation of cracks or the occurrence of fractures in the substrate, and improve the manufacturing yield.
  • the thin-walled portion is defined between a flat top of the substrate, on which the conductive layer is formed, and a bottom of a concave formed in a bottom surface of the substrate.
  • the thin-walled portion is defined between a flat bottom of the substrate, and a bottom of a concave formed in a top surface of the substrate, on which the conductive layer is formed.
  • thin-walled portion may be defined between a bottom of a first concave formed in a top surface of the substrate and a bottom of a second concave formed in a bottom surface of the substrate.
  • the conductive layer is formed on the bottom of at least one of the first and second concaves.
  • the thin-walled portion is provided by a projection integrally molded with the substrate such that an outer surface of the projection is used to form the conductive layer, and the projection has a cavity therein.
  • the thin-walled portion has at least one through hole around the conductive layer formed thereon, or a pair of notches in the vicinity of opposite ends of the thin-walled portion in an extending direction of the conductive layer.
  • the first circuit pattern, the second circuit pattern and the conductive layer are formed at a time by patterning a metal thin film provided on the substrate.
  • a further concern of the present invention is to provide a method of more efficiently manufacturing a printed circuit board. That is, the method is characterized by comprising the steps of: forming a metal thin film on a substrate having a thin-walled portion; providing an initial circuit pattern on the substrate by patterning the metal thin film, the initial circuit pattern comprising first and second circuit patterns isolated from each other and a conductive layer formed on the thin-walled portion to make a temporary electrical connection between the first and second circuit patterns; performing electroplating by the passage of electric current through the initial circuit pattern to form an additional metal film on the initial circuit pattern; and after the electroplating, removing the thin-walled portion with the conductive layer to provide an electrical insulation between the first and second circuit patterns.
  • Another concern of the present invention is to provide a substrate used in the above-described method of the present invention, and having a thin-walled portion, which is adapted to form a conductive layer for making a temporary electrical connection between circuit patterns isolated from each other on the substrate.
  • FIG. 1 A is a schematic perspective view showing a first step of a method of manufacturing a printed wiring board according to a first embodiment of the present invention and FIG. 1B is a cross-sectional view taken along the line M-M of FIG. 1A;
  • FIG. 2A is a schematic perspective view showing a second step of the method of the first embodiment and FIG. 2B is a cross -sectional view taken along the line M-M of FIG. 2A;
  • FIG. 3A is a schematic perspective view showing a third step of the method of the first embodiment and FIG. 3B is a cross-sectional view taken along the line M-M of FIG. 3A;
  • FIG. 4A is a schematic perspective view showing a fourth step of the method of the first embodiment and FIG. 4B is a cross-sectional view taken along the line M-M of FIG. 4A;
  • FIG. 5A is an enlarged plan view of a conductive layer on a thin-walled portion of the present invention and FIG. 5B is a cross-sectional view taken along the line M-M of FIG. 5A;
  • FIG. 6A is an enlarged plan view of conductive layers on a single thin- walled portion of the present invention and FIG. 6B is a cross-sectional view taken along the line M-M of FIG. 6A;
  • FIG. 7A is an enlarged plan view of a thin-walled portion with a V-shaped groove of the present invention and
  • FIG. 7B is a cross-sectional view taken along the line M-M of FIG. 7A;
  • FIG. 8A is an enlarged plan view of a thin-walled portion with a pair of apertures of the present invention and FIG. 8B is a cross-sectional view taken along the line M-M of FIG. 8A;
  • FIG. 9A is an enlarged plan view of a thin-walled portion with a plurality of holes of the present invention and FIG. 9B is a cross-sectional view taken along the line M-M of FIG. 9A;
  • FIG. 10 is a schematic cross-sectional view showing the step of removing the thin-wailed portion by use of an ultrasonic-applied punch
  • FIG. 11 is a schematic cross-sectional view showing the step of removing the thin-walled portion by use of a laser beam
  • FIG. 12 is a schematic cross-sectional view showing the step of removing the thin-walled portion by use of a fluid jet
  • FIG. 13 is a schematic cross-sectional view showing a modification of the substrate used for the method of the present invention
  • FIG. 14 is a schematic cross-sectional view showing a further modification of the substrate used for the method of the present invention.
  • FIGS. 15A and 15B are schematic cross-sectional views showing another modification of the substrate used for the method of the present invention.
  • FIGS. 16A and 16B are schematic cross-sectional views showing a method of manufacturing a printed wiring board according to a second embodiment of the present invention.
  • FIGS. 17A to 17E are schematic cross-sectional views showing a method of manufacturing a printed wiring board according to a third embodiment of the present invention.
  • FIG. 18 is a perspective view of a printed wiring board with circuit patterns electrically isolated from each other;
  • FIGS. 19A to 19C are schematic perspective views showing a method of manufacturing a printed wiring board disclosed in US Patent No. 5,494,781;
  • FIGS. 20A to 20D are schematic perspective views showing a method of manufacturing a printed wiring board disclosed in Japanese Patent Early Publication [kokai] No. 10-93225.
  • FIGS. 1 A and 1 B A substrate used in the first embodiment is shown in FIGS. 1 A and 1 B.
  • the substrate 1 has a thin-walled portion 10 defined between a flat top 12 of the substrate and a bottom 13 of a concave 14 formed in a bottom surface of the substrate. It is preferred that the thin-walled portion 10 is integrally formed with the substrate 1 by injection molding or transfer molding.
  • the substrate 1 can be made from a ceramic material or an electrically-insulating resin material.
  • the ceramic material comprises alumina, silicon nitride, silicon carbide, zirconia and so on
  • the resin material comprises liquid polymer, poly phthal amide, poly phthal sulfone, poly buthylene terephthalete (PBT), syndiotactic polystyrene (SPS), epoxy resin and so on.
  • the substrate with the thin- walled portion may be formed by injection-molding a mixture of a resin binder and a ceramic powder to form a molded body having a required shape, and then degreasing and sintering the molded body.
  • the thin- walled portion 10 may be formed in the substrate 1 by mechanical machining.
  • first and second circuit patterns (20, 22) isolated from each other are formed on the flat top 12 of the substrate 1.
  • a conductive layer 40 is formed on the thin-walled portion 10 to make a temporary electrical connection between the first and second circuit patterns (20, 22).
  • the conductive layer 40 is used only in a step of electroplating performed later.
  • electroplating such as copper electroplating is performed by the passage of electric current through the first and second circuit patterns (20, 22) connected by the conductive layer 40 to simultaneously form an additional metal (copper) film 50 having a desired thickness on these circuit patterns. For example, when electric current is supplied to the first circuit pattern 20, it flows to the second circuit pattern 22 through the conductive layer 40 on the thin-walled portion 10.
  • the thin-walled portion 10 having the conductive layer 40 and the additional metal film 50 are removed to provide electrical insulation between the first and second circuit patterns (20, 22), as shown in FIGS. 4A and 4B. It is preferred that the thin-walled portion 10 is removed together with the conductive layer 40 and the additional metal film 50 from the substrate 1 by punching.
  • the numeral 15 designates a through hole formed in the substrate 1 by punching the thin-walled portion 10.
  • a thickness (T) of the thin-walled portion 10 is 2 mm or less.
  • the thickness (T) of the thin-walled portion 10 is 1 mm or less.
  • a ratio of the thickness (T) of the thin-walled portion 10 to a punching diameter (D) that is substantially equal to the diameter of the through hole 15 formed in the substrate 1 by punching the thin-walled portion 10 is 2 or less (T/D ⁇ 2).
  • T/D ⁇ 2 the thickness of the thin-walled portion 10
  • the metal thin film can be formed by means of vacuum deposition, DC sputtering, or RF sputtering. It is preferred that a thickness of the metal thin film is less than 1 ⁇ m. As an example, the thickness is about 0.3 ⁇ m.
  • an initial circuit pattern is formed on the substrate 1 by patterning the metal thin film.
  • the patterning method it is preferred to use a laser patterning, in which the laser beam is irradiated to the metal thin film along a desired pattern by use of a galvanometer mirror. According to this method, it is possible to efficiently form a high-density pattern of the metal thin film with accuracy.
  • a second or third harmonic YAG laser is preferably used in the laser patterning.
  • the laser beam has a wavelength, at which a laser- absorption rate in the substrate 1 is much different from laser-absorption rate in the metal thin film.
  • the initial circuit pattern comprises the first and second circuit patterns (20, 22) isolated from each other, the conductive layer 40 formed on the thin-walled portion 10 to make the temporary electrical connection between these circuit patterns.
  • electroplating such as copper electroplating is performed by the passage of electric current through the initial circuit pattern to form an additional metal film 50 on the initial circuit pattern.
  • electroplating the thin-walled portion 10 with the conductive layers 40 and the additional metal film 50 is removed, so that electrical insulation between the first and second circuit patterns (20, 22) is made by the formation of the through-hole 15.
  • Nickel plating, silver plating and/or gold plating may be performed on the additional metal film 50 prior to the step of removing the thin-walled portion 10, if necessary.
  • the additional metal film 50 is not formed on the useless region of the metal thin film at the step of electroplating. This useless region of the metal thin film can be readily removed by soft etching.
  • the first and second circuit patterns (20, 22) are formed on the substrate 1.
  • a plurality of additional circuit patterns may be formed on the substrate.
  • a conductive layer 40 can be formed on the thin-walled portion 10, as shown in FIGS. 5A and 5B, to thereby make a temporary electrical connection among the first and second circuit patterns and the additional circuit patterns.
  • the electroplating step by removing the thin-walled portion 10 with the additional metal film 50 and the conductive layer 40 formed in the pattern shown in FIG. 5A, the first and second circuit patterns and the additional circuit patterns can be readily isolated from each other.
  • a plurality of conductive layers (40, 41, 42) may be formed on a single thin-walled portion 10.
  • a pair of notches 16 in the vicinity of opposite ends of the thin-walled portion in an extending direction of the conductive layer 40.
  • a V- shaped groove 16 may be formed in the thin-walled portion 10 to extend in a loop. Since the thin-walled portion 10 is removed at the V-shaped groove 16 from the substrate 1 , it is possible to provide the electrical insulation between the circuit patterns with a high degree of reliability, while reducing the occurrence of burrs and chipping of the substrate material. In addition, there is an advantage of simplifying a subsequent cleaning step.
  • At least one through hole adjacent to the conductive layer 40 in the thin-walled portion 10 it is preferred to form at least one through hole adjacent to the conductive layer 40 in the thin-walled portion 10.
  • a pair of half-moon-shaped apertures 17 may be formed at opposite sides of the conductive layer 40 extending on the thin-walled portion 10.
  • a plurality of through-holes 18 having a small diameter may be formed at the margins of the thin-walled portion 10. In these cases, it is possible to further improve the easiness of removing the thin-walled portion 10.
  • the means of removing the thin-walled portion 10 from the substrate 1 it is possible to give shocks or vibrations to the thin-walled portion, or blast a fluid such as water or air to the thin-walled portion under high speed and high pressure.
  • the thin-walled portion 10 can be removed by use of a punch 60, to which ultrasonic vibrations are applied, as shown in FIG. 10.
  • the numerals 80 and 82 designate a hone and an ultrasonic vibrator, respectively. In this case, there is an advantage of effectively preventing the occurrence of burrs at the through-hole 15 formed by punching the thin-walled portion 10.
  • the thin-walled portion 10 may be removed by use of a laser beam 84 such as YAG laser or C0 2 laser, as shown in FIG. 11.
  • a laser beam 84 such as YAG laser or C0 2 laser
  • the thin-walled portion 10 can be removed with accuracy, it is particularly useful to form high-density circuit patterns isolated from each other on the substrate 1.
  • the substrate 1 is made from a resin material, it is possible to reduce deformation or warping of the substrate as compared with the case of mechanically removing the thin- walled portion 10 by punching or drilling.
  • the thin-walled portion 10 may be removed by use of a fluid jet 86 selected from a liquid such as water, a powder such as ceramic powder and a mixture thereof, as shown in FIG. 12.
  • FIGS. 1A and 1B it is possible to use a substrate 1 having a thin-walled portion 10, as shown in FIG. 13, which is defined between a flat bottom 11 of the substrate, and a bottom 13 of a concave 14 formed in a top surface of the substrate, on which the conductive layer 40 extends.
  • the thin-walled portion 10 is removed together with the conductive layer and the additional metal film 50 on the bottom 13 of the concave 14 by use of a punch 60, to thereby make the electrical insulation between the circuit patterns (20, 22).
  • a substrate 1 having a thin-walled portion 10 which is defined between a bottom of a first concave 14a formed in a top surface of the substrate, and a bottom of a second concave 14b formed in a bottom surface of the substrate.
  • the conductive layer 40 is formed on the bottom of the first concave 14a.
  • the conductive layer 40 may be formed on the bottom of the second concave 14b, or both of the bottoms of the first and second concaves (14a, 14b).
  • the manufacturing efficiency is further improved.
  • notches (16) described above is formed in a surface of the thin-walled portion 10, from which the punch 60 comes out.
  • FIGS. 15A and 15B may be used.
  • the projection 19 is removed together with the conductive layer 40 and the additional metal film 50 by punching, drilling, cutting, grinding or end milling in order to provide the electrical insulation between the circuit patterns (20, 22) with a high degree of reliability.
  • the projection 19 is removed by performing the end milling 88 from an adequate direction, it is possible to effectively reduce the occurrence of burrs or peeling of the circuit patterns around the through-hole 15 formed in the thin-walled portion 10 by the end milling.
  • the substrate is made from an electrically-insulating resin material
  • the substrate becomes soft by heating, it is possible to easily and efficiently remove the thin-walled portion 10 by punching.
  • an auxiliary substrate 70 having at least one projection 72 is placed under the substrate, i.e., at a side opposed to the top surface having the conductive layer 40 of the substrate 1.
  • the auxiliary substrate 70 is preferably made from a metal material such as silver, aluminum and copper.
  • the auxiliary substrate 70 is moved toward the substrate 1, as shown by the arrows in FIG. 16A, so that the thin-walled portion 10 with the conductive layer 40 and the additional metal film 50 is punched by use of the projections 72.
  • the auxiliary substrate 70 is bonded to the substrate 1 under the condition that the projections 72 pass through the substrate 1 , as shown in FIG. 16B.
  • an adhesive is used to bond the auxiliary substrate 70 to the substrate 1 , it is preferred to use an epoxy resin or an acrylic resin as the adhesive.
  • the auxiliary substrate 70 is made from a resin material having excellent thermal conductivity and electrical insulating property, the auxiliary substrate may be bonded to the substrate by pressing the projections 72 into the substrate 1 without using the adhesive.
  • the projection 72 When the auxiliary substrate 70 is made from the metal material, it is preferred that the projection 72 has a recess 76 in its side surface. When the projection 72 passes through the thin-walled portion 10, a clearance D is provided between the side surface of the projection 72 and the circuit patterns (20, 22, 50) on the substrate 1 , as shown in FIG. 16B. This clearance D presents the electrical insulation therebetween.
  • the auxiliary substrate 70 of the metal material also functions as a heat sink.
  • the auxiliary substrate 70 may be made from a ceramic material or a resin material.
  • a dent for mounting an electronic part such as LED may be formed in a top of the projection.
  • an electrical connection between the electronic part and a required circuit pattern on the substrate can be made by wire bonding.
  • a substrate 1 having thin-walled portions 10, which are defined between a flat top 12 and concaves 14 formed in its bottom surface, is used, as shown in FIG. 17A.
  • a first, second and third circuit patterns (20, 22, 24) electrically isolated from each other are formed on the flat top 12 of the substrate 1 (FIG. 17B).
  • conductive layers 40 are formed on the thin-walled portions 10 to make a temporary electrical connection between these circuit patterns.
  • the formation of the first, second and third circuit patterns (20, 22, 24) and the formation of the conductive layers 40 are performed at a time by laser-patterning a metal thin film on the substrate 1.
  • electroplating is performed by the passage of electric current through those circuit patterns (20, 22, 24) connected by the conductive layers 40 to simultaneously form an additional metal film 50 on those circuit patterns.
  • an auxiliary substrate 70 having projections 72 is bonded to the substrate 1 such that each of projections fits into the corresponding concave 14 of the substrate.
  • Each of the projections 72 has a through hole 74.
  • the thin-walled portions 10 are punched from the above of the flat top of the substrate 1 by use of punches 60, so that the punches proceed into the through holes 74 of the projections 72.
  • the auxiliary substrate 70 works as a punch receiving die, it is possible to accurately punch the thin-walled portions 10, as shown in FIG. 17E.
  • the thin-walled portions 10 can be removed without using a dedicated die for holding the substrate 1 , it is useful to save the manufacturing cost.
  • the auxiliary substrate 70 is made from a metal material, it also works as a heat sink.
  • the auxiliary substrate may be used for the substrate 1 shown in FIG. 14. In this case, the thin-walled portions 10 are punched from the above of the additional metal film 50 formed on the substrate 1 by use of the punches 60.
  • the conductive layer for making a temporary electrical connection between circuit patterns isolated from each other is formed on the thin-walled portion of the substrate, and then electroplating is performed by the passage of electric current through the circuit patterns connected by the conductive layer, so that a metal film can be formed on those circuit patterns at a time by electroplating.
  • electroplating is performed by the passage of electric current through the circuit patterns connected by the conductive layer, so that a metal film can be formed on those circuit patterns at a time by electroplating.
  • the electrical insulation between the circuit patterns can be readily obtained with reliability by removing the thin-walled portion with the conductive layer from the substrate by, for example, punching or the use of a laser beam.
  • the present invention is particularly useful to efficiently manufacture high-density printed wiring boards.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

A method of manufacturing a printed wiring board is provided, which includes the capability of improving manufacturing yield and efficiently forming a metal film by electroplating. In this method, a metal thin film is formed on a substrate (1) having a thin-walled portion (10). Then, an initial circuit pattern is formed on the substrate by patterning the metal thin film. The initial circuit pattern comprises first and second circuit patterns (20, 22) isolated from each other and a conductive layer (40) formed on the thin-walled portion (10) to make a temporary electrical connection between these circuit patterns (20, 22). Electroplating is carried out by the passage of electric current through the initial circuit pattern to form an additional metal film (50) on the initial circuit pattern. After the electroplating, electrical insulation between the first and second circuit patterns (20, 22) is obtained by punching the thin-walled portion (10) with the conductive layer (40).

Description

DESCRIPTION METHOD OF MANUFACTURING PRINTED WIRING BOARDS AND SUBSTRATE USED FOR THE METHOD
TECHNICAL FIELD
The present invention relates to a method of efficiently manufacturing printed wiring boards having a plurality of circuit patterns electrically isolated from each other, and a substrate used for the method.
BACKGROUND ART
In a conventional method of manufacturing printed wiring boards, a metal thin film is first formed on a substrate, and required regions of the metal thin film are removed to obtain a pattern of the metal thin film on the substrate. Then, electroplating is performed to form an additional metal film on the pattern of the metal thin film, so that circuit patterns having a desired thickness is obtained on the substrate.
However, when patterns of the metal thin film on the substrate are electrically isolated from each other, the electroplating step becomes very complicated. For example, when a circuit pattern 20S is electrically insulated from the circuit pattern 22S on an insulating substrate 1S, as shown in FIG. 18, it is required to individually perform electroplating with respect to each of these circuit patterns to form the addition metal film. As a result, an increase in manufacturing cost is caused by an extension of time required for the electroplating step. In addition, to stably maintain the manufacturing yield of the printed wiring boards, there is a problem that a quality of the plating solution must be very often checked.
On the other hand, by providing a feeder circuit for electroplating to each of the isolated circuit patterns, it is possible to form the additional metal film on those circuit patterns at a time by electroplating. However, in this method, there is a limitation in manufacturing high-density printed wiring boards. That is, as the circuit-pattern density is higher, the reliability of circuit patterns formed by electroplating deteriorates.
To eliminate the above-described problems, US Patent No. 5,494, 781 discloses an improved method of manufacturing a printed wiring board. According to this method, it is possible to simultaneously form the additional metal film on the isolated circuit patterns by electroplating without supplying electric current to the isolated circuit patterns through the feeder circuits. That is, as shown in FIG. 19A, by pattering a metal thin film formed on a substrate (not shown), circuit patterns (30P, 32P) isolated from each other and a conductive layer 40P extending therebetween are provided on the substrate. After a resist film 90P is formed on the conductive layer 40P, electroplating is performed by the passage of electric current through the isolated circuit patterns (30P, 32P) connected by the conductive layer 40P to simultaneously form an additional metal film 50P on these circuit patterns, as shown in FIG. 19B. At this time, since the conductive layer 40P is covered with the resist film 90P, the additional film 50P is not formed on the conductive layer. After the electroplating, the resist film 90P is removed to expose the conductive layer 40P, and then the conductive layer 40P is removed by soft etching to make electrical insulation between the isolated circuit patterns (30P, 32P), as shown in FIG. 19C.
However, since the step of forming the resist film 90P on the conductive layer 40P is needed, it consequently leads to an (increase in production cost. In particular, when forming a three-dimensional circuit pattern on a substrate for MID (molded interconnect device), or manufacturing a high-density printed wiring board, the difficulty of forming the resist film on the conductive layer comes into a problem. In addition, when the removal of the conductive layer 40P after the electroplating is not enough, there is a fear that insulation failure occurs.
On the other hand, Japanese Patent Early Publication [kokai] No. 10-93225 discloses a method of manufacturing a printed wiring board, which includes the capability of efficiently forming a conductive pattern by electroplating at a relatively low cost. In this method, as shown in FIG. 20A, an adhesive layer 10R for electroless plating and a plating resist layer 20R are formed on a substrate 1R. Then, required portions of the plating resist layer 20R is removed to expose the adhesive layer 10R. On this exposed adhesive layer 10R, conductive patterns 8R, pad 7R and lead 9R for electroplating performed later are formed by electroless plating (FIG. 20B). Next, as shown in FIG. 20C, electroplating is performed by the passage of electric current through the lead 9R to form a thick metal film 50R on the conductive patterns 8R, the pad 7R and the lead 9R. Subsequently, as shown in FIG. 20D, electrical insulation between the conductive patterns 8R and the lead 9R is obtained by punching or etching the pad 7R with the thick metal film 50. In FIG. 20D, the numeral 40R designates a through hole formed in the substrate 1R by the punching step.
In addition, another method of manufacturing a printed wiring board is disclosed in Japanese Patent Early Publication [kokai] No. 57-198695. In this method, a resist material is applied on an insulating substrate to expose required regions of the insulating substrate, and then a catalyst treatment for electroless plating is performed. After the resist is removed, a metal thin film is formed on the required regions by electroless plating to obtain electric pathway portions and electric-pathway connecting portions on the insulating substrate. Subsequently, electroplating is performed by the passage of electric current through the metal thin film to form an additional metal film on the electric pathway portions and the electric- pathway connecting portions. After the electroplating, the electric- pathway connecting portions with the additional metal film are removed by means of die-cutting or drilling, to thereby obtain a plurality of circuit patterns, i.e., the electric pathway portions with the additional metal film, that are electrically isolated from each other.
However, in these methods, when the pad or the electric-pathway connecting portions are removed by punching, die-cutting or drilling, there is a problem that the manufacturing yield becomes poor because of the occurrence of cracks in the insulating substrate. In particular, in the case of using a ceramic material or an insulating resin material containing a large amount of filler as the insulating substrate, or a substrate having a relatively large thickness, there is another problem that time required for the punching, die-cutting or drilling is extended, so that the manufacturing efficiency of the printed wiring boards considerably lowers. Thus, there is still plenty of room for improvement in the method of manufacturing printed wiring boards of the prior art from the viewpoints of the manufacturing efficiency and yield.
SUMMARY OF THE INVENTION
Therefore, a concern of the present invention is to provide a method of manufacturing a printed wiring board having a plurality of circuit patterns electrically insulated from each other, which includes the capability of improving manufacturing yield and efficiently forming a metal film by electroplating.
That is, the method of the present invention is characterized by comprising the steps of: providing a substrate with a thin-walled portion; forming a first circuit pattern on the substrate; forming a second circuit pattern isolated from the first circuit pattern on the substrate; forming a conductive layer on the thin-walled portion to make a temporary electrical connection between the first and second circuit patterns; performing electroplating by the passage of electric current through the first and second circuit patterns connected by the conductive layer to simultaneously form a metal film on the first and second circuit patterns; and after the electroplating, removing the thin-walled portion with the conductive layer to provide an electrical insulation between the first and second circuit patterns.
According to the present invention, since the conductive layer is formed on the thin-walled portion, it is possible to readily and efficiently remove the thin-walled portion with the conductive layer by means of punching, drilling and so on after the electroplating. In addition, as mechanical damages and shocks given to the substrate at the time of removing the thin-walled portion decrease, it is possible to prevent the propagation of cracks or the occurrence of fractures in the substrate, and improve the manufacturing yield.
In the present invention, it is preferred that the thin-walled portion is defined between a flat top of the substrate, on which the conductive layer is formed, and a bottom of a concave formed in a bottom surface of the substrate. Alternatively, it is preferred that the thin-walled portion is defined between a flat bottom of the substrate, and a bottom of a concave formed in a top surface of the substrate, on which the conductive layer is formed. In addition, thin-walled portion may be defined between a bottom of a first concave formed in a top surface of the substrate and a bottom of a second concave formed in a bottom surface of the substrate. In this case, the conductive layer is formed on the bottom of at least one of the first and second concaves.
In addition, it is preferred that the thin-walled portion is provided by a projection integrally molded with the substrate such that an outer surface of the projection is used to form the conductive layer, and the projection has a cavity therein. In this case, by removing at least a part of the projection together with the conductive layer, it is possible to obtain the electrical insulation between the first and second circuit patterns. To improve the easiness of removing the thin-walled portion, it is preferred that the thin-walled portion has at least one through hole around the conductive layer formed thereon, or a pair of notches in the vicinity of opposite ends of the thin-walled portion in an extending direction of the conductive layer. To further improve manufacturing efficiency, it is particularly preferred that the first circuit pattern, the second circuit pattern and the conductive layer are formed at a time by patterning a metal thin film provided on the substrate.
A further concern of the present invention is to provide a method of more efficiently manufacturing a printed circuit board. That is, the method is characterized by comprising the steps of: forming a metal thin film on a substrate having a thin-walled portion; providing an initial circuit pattern on the substrate by patterning the metal thin film, the initial circuit pattern comprising first and second circuit patterns isolated from each other and a conductive layer formed on the thin-walled portion to make a temporary electrical connection between the first and second circuit patterns; performing electroplating by the passage of electric current through the initial circuit pattern to form an additional metal film on the initial circuit pattern; and after the electroplating, removing the thin-walled portion with the conductive layer to provide an electrical insulation between the first and second circuit patterns.
Another concern of the present invention is to provide a substrate used in the above-described method of the present invention, and having a thin-walled portion, which is adapted to form a conductive layer for making a temporary electrical connection between circuit patterns isolated from each other on the substrate. These and still other objects and advantages of the present invention will become more apparent from preferred embodiments of the present invention explained below, referring to the attached drawings.
BRIEF EXPLANATION OF THE DRAWINGS FIG. 1 A is a schematic perspective view showing a first step of a method of manufacturing a printed wiring board according to a first embodiment of the present invention and FIG. 1B is a cross-sectional view taken along the line M-M of FIG. 1A; FIG. 2A is a schematic perspective view showing a second step of the method of the first embodiment and FIG. 2B is a cross -sectional view taken along the line M-M of FIG. 2A;
FIG. 3A is a schematic perspective view showing a third step of the method of the first embodiment and FIG. 3B is a cross-sectional view taken along the line M-M of FIG. 3A; FIG. 4A is a schematic perspective view showing a fourth step of the method of the first embodiment and FIG. 4B is a cross-sectional view taken along the line M-M of FIG. 4A;
FIG. 5A is an enlarged plan view of a conductive layer on a thin-walled portion of the present invention and FIG. 5B is a cross-sectional view taken along the line M-M of FIG. 5A;
FIG. 6A is an enlarged plan view of conductive layers on a single thin- walled portion of the present invention and FIG. 6B is a cross-sectional view taken along the line M-M of FIG. 6A; FIG. 7A is an enlarged plan view of a thin-walled portion with a V-shaped groove of the present invention and FIG. 7B is a cross-sectional view taken along the line M-M of FIG. 7A;
FIG. 8A is an enlarged plan view of a thin-walled portion with a pair of apertures of the present invention and FIG. 8B is a cross-sectional view taken along the line M-M of FIG. 8A;
FIG. 9A is an enlarged plan view of a thin-walled portion with a plurality of holes of the present invention and FIG. 9B is a cross-sectional view taken along the line M-M of FIG. 9A;
FIG. 10 is a schematic cross-sectional view showing the step of removing the thin-wailed portion by use of an ultrasonic-applied punch;
FIG. 11 is a schematic cross-sectional view showing the step of removing the thin-walled portion by use of a laser beam;
FIG. 12 is a schematic cross-sectional view showing the step of removing the thin-walled portion by use of a fluid jet; FIG. 13 is a schematic cross-sectional view showing a modification of the substrate used for the method of the present invention;
FIG. 14 is a schematic cross-sectional view showing a further modification of the substrate used for the method of the present invention; ,
FIGS. 15A and 15B are schematic cross-sectional views showing another modification of the substrate used for the method of the present invention;
FIGS. 16A and 16B are schematic cross-sectional views showing a method of manufacturing a printed wiring board according to a second embodiment of the present invention;
FIGS. 17A to 17E are schematic cross-sectional views showing a method of manufacturing a printed wiring board according to a third embodiment of the present invention;
FIG. 18 is a perspective view of a printed wiring board with circuit patterns electrically isolated from each other;
FIGS. 19A to 19C are schematic perspective views showing a method of manufacturing a printed wiring board disclosed in US Patent No. 5,494,781; and
FIGS. 20A to 20D are schematic perspective views showing a method of manufacturing a printed wiring board disclosed in Japanese Patent Early Publication [kokai] No. 10-93225.
BEST MODE FOR CARRYING OUT THE INVENTION
A method of manufacturing a printed wiring board of the present invention is explained in detail according to the following preferred embodiments.
(First Embodiment)
A substrate used in the first embodiment is shown in FIGS. 1 A and 1 B. The substrate 1 has a thin-walled portion 10 defined between a flat top 12 of the substrate and a bottom 13 of a concave 14 formed in a bottom surface of the substrate. It is preferred that the thin-walled portion 10 is integrally formed with the substrate 1 by injection molding or transfer molding. The substrate 1 can be made from a ceramic material or an electrically-insulating resin material. For example, the ceramic material comprises alumina, silicon nitride, silicon carbide, zirconia and so on, and the resin material comprises liquid polymer, poly phthal amide, poly phthal sulfone, poly buthylene terephthalete (PBT), syndiotactic polystyrene (SPS), epoxy resin and so on. In addition, the substrate with the thin- walled portion may be formed by injection-molding a mixture of a resin binder and a ceramic powder to form a molded body having a required shape, and then degreasing and sintering the molded body. The thin- walled portion 10 may be formed in the substrate 1 by mechanical machining.
In addition, as shown in FIG. 1 A, first and second circuit patterns (20, 22) isolated from each other are formed on the flat top 12 of the substrate 1. Then, as shown in FIG. 2A and 2B, a conductive layer 40 is formed on the thin-walled portion 10 to make a temporary electrical connection between the first and second circuit patterns (20, 22). The conductive layer 40 is used only in a step of electroplating performed later. Next, as shown in FIGS. 3A and 3B, electroplating such as copper electroplating is performed by the passage of electric current through the first and second circuit patterns (20, 22) connected by the conductive layer 40 to simultaneously form an additional metal (copper) film 50 having a desired thickness on these circuit patterns. For example, when electric current is supplied to the first circuit pattern 20, it flows to the second circuit pattern 22 through the conductive layer 40 on the thin-walled portion 10.
After the electroplating, the thin-walled portion 10 having the conductive layer 40 and the additional metal film 50 are removed to provide electrical insulation between the first and second circuit patterns (20, 22), as shown in FIGS. 4A and 4B. It is preferred that the thin-walled portion 10 is removed together with the conductive layer 40 and the additional metal film 50 from the substrate 1 by punching. In the figures, the numeral 15 designates a through hole formed in the substrate 1 by punching the thin-walled portion 10. When the substrate 1 is made from the resin material, it is preferred that a thickness (T) of the thin-walled portion 10 is 2 mm or less. When the substrate 1 is made from the ceramic material, it is preferred that the thickness (T) of the thin-walled portion 10 is 1 mm or less. In addition, it is preferred that a ratio of the thickness (T) of the thin-walled portion 10 to a punching diameter (D) that is substantially equal to the diameter of the through hole 15 formed in the substrate 1 by punching the thin-walled portion 10 is 2 or less (T/D≤2). In this case, it is possible to carry out the punching operation with accuracy, and effectively prevent the occurrence of cracks and fractures of the substrate. In the above method, to improve manufacturing efficiency, it is particularly preferred that the formation of the first and second circuit patterns (20, 22) and the formation of the conductive layer 40 are performed at a time. That is, a metal thin film such as copper is formed on the flat top 12 of the substrate 1 having the thin-walled portion 10. The metal thin film can be formed by means of vacuum deposition, DC sputtering, or RF sputtering. It is preferred that a thickness of the metal thin film is less than 1 μm. As an example, the thickness is about 0.3 μm.
Then, an initial circuit pattern is formed on the substrate 1 by patterning the metal thin film. As the patterning method, it is preferred to use a laser patterning, in which the laser beam is irradiated to the metal thin film along a desired pattern by use of a galvanometer mirror. According to this method, it is possible to efficiently form a high-density pattern of the metal thin film with accuracy. For example, a second or third harmonic YAG laser is preferably used in the laser patterning. In addition, it is preferred that the laser beam has a wavelength, at which a laser- absorption rate in the substrate 1 is much different from laser-absorption rate in the metal thin film. The initial circuit pattern comprises the first and second circuit patterns (20, 22) isolated from each other, the conductive layer 40 formed on the thin-walled portion 10 to make the temporary electrical connection between these circuit patterns.
Subsequently, electroplating such as copper electroplating is performed by the passage of electric current through the initial circuit pattern to form an additional metal film 50 on the initial circuit pattern. After the electroplating, the thin-walled portion 10 with the conductive layers 40 and the additional metal film 50 is removed, so that electrical insulation between the first and second circuit patterns (20, 22) is made by the formation of the through-hole 15. Nickel plating, silver plating and/or gold plating may be performed on the additional metal film 50 prior to the step of removing the thin-walled portion 10, if necessary.
By the way, since the initial circuit pattern is electrically separated from a useless region of the remaining metal thin film on the substrate by the laser patterning, the additional metal film 50 is not formed on the useless region of the metal thin film at the step of electroplating. This useless region of the metal thin film can be readily removed by soft etching.
In this embodiment, as shown in FIG. 1A, the first and second circuit patterns (20, 22) are formed on the substrate 1. However, if necessary, a plurality of additional circuit patterns may be formed on the substrate. For example, when additional circuit patterns isolated from each other are formed on the substrate having the first and second circuit patterns, a conductive layer 40 can be formed on the thin-walled portion 10, as shown in FIGS. 5A and 5B, to thereby make a temporary electrical connection among the first and second circuit patterns and the additional circuit patterns. After the electroplating step, by removing the thin-walled portion 10 with the additional metal film 50 and the conductive layer 40 formed in the pattern shown in FIG. 5A, the first and second circuit patterns and the additional circuit patterns can be readily isolated from each other. Alternatively, as shown in FIG. 6A and 6B, a plurality of conductive layers (40, 41, 42) may be formed on a single thin-walled portion 10.
In these cases, it is possible to increase a degree of flexibility in circuit design by reducing the total number of thin-walled portions 10 to be formed in the substrate 1. Therefore, these modifications are particularly effective to manufacture high-density printed wiring boards. In addition, there is an advantage that time required to remove the thin-walled portions after the electroplating becomes short as a whole.
To prevent the occurrence of burrs and chipping of the substrate material or peeling of the circuit patterns at the step of removing the thin- walled portion 10, it is preferred to form a pair of notches 16 in the vicinity of opposite ends of the thin-walled portion in an extending direction of the conductive layer 40. For example, as shown in FIGS. 7A and 7B, a V- shaped groove 16 may be formed in the thin-walled portion 10 to extend in a loop. Since the thin-walled portion 10 is removed at the V-shaped groove 16 from the substrate 1 , it is possible to provide the electrical insulation between the circuit patterns with a high degree of reliability, while reducing the occurrence of burrs and chipping of the substrate material. In addition, there is an advantage of simplifying a subsequent cleaning step. In addition, it is preferred to form at least one through hole adjacent to the conductive layer 40 in the thin-walled portion 10. For example, as shown in FIGS. 8A and 8B, a pair of half-moon-shaped apertures 17 may be formed at opposite sides of the conductive layer 40 extending on the thin-walled portion 10. Alternatively, as shown in FIGS. 9A and 9B, a plurality of through-holes 18 having a small diameter may be formed at the margins of the thin-walled portion 10. In these cases, it is possible to further improve the easiness of removing the thin-walled portion 10.
As the means of removing the thin-walled portion 10 from the substrate 1, it is possible to give shocks or vibrations to the thin-walled portion, or blast a fluid such as water or air to the thin-walled portion under high speed and high pressure. As preferred examples, the thin-walled portion 10 can be removed by use of a punch 60, to which ultrasonic vibrations are applied, as shown in FIG. 10. In this figure, the numerals 80 and 82 designate a hone and an ultrasonic vibrator, respectively. In this case, there is an advantage of effectively preventing the occurrence of burrs at the through-hole 15 formed by punching the thin-walled portion 10. In addition, the thin-walled portion 10 may be removed by use of a laser beam 84 such as YAG laser or C02 laser, as shown in FIG. 11. In this case, since the thin-walled portion 10 can be removed with accuracy, it is particularly useful to form high-density circuit patterns isolated from each other on the substrate 1. In addition, when the substrate 1 is made from a resin material, it is possible to reduce deformation or warping of the substrate as compared with the case of mechanically removing the thin- walled portion 10 by punching or drilling. Alternatively, the thin-walled portion 10 may be removed by use of a fluid jet 86 selected from a liquid such as water, a powder such as ceramic powder and a mixture thereof, as shown in FIG. 12.
In place of the substrate of FIGS. 1A and 1B, it is possible to use a substrate 1 having a thin-walled portion 10, as shown in FIG. 13, which is defined between a flat bottom 11 of the substrate, and a bottom 13 of a concave 14 formed in a top surface of the substrate, on which the conductive layer 40 extends. In this case, the thin-walled portion 10 is removed together with the conductive layer and the additional metal film 50 on the bottom 13 of the concave 14 by use of a punch 60, to thereby make the electrical insulation between the circuit patterns (20, 22).
Alternatively, as shown in FIG. 14, it is preferred to use a substrate 1 having a thin-walled portion 10, which is defined between a bottom of a first concave 14a formed in a top surface of the substrate, and a bottom of a second concave 14b formed in a bottom surface of the substrate. In FIG. 14, the conductive layer 40 is formed on the bottom of the first concave 14a. However, the conductive layer 40 may be formed on the bottom of the second concave 14b, or both of the bottoms of the first and second concaves (14a, 14b). In particular, when the circuit patterns isolated from each other are formed on each of the top and bottom surface of the substrate 1 , the electrical insulation between the circuit patterns on both of the top and bottom surfaces of the substrate 1 is obtained at a time by punching the thin-walled portion 10. Therefore, the manufacturing efficiency is further improved. In addition, from the viewpoints of reducing the occurrence of burrs and warping of the substrate 1 , and improving the easiness of removing the thin-walled portion 10, it is preferred that notches (16) described above is formed in a surface of the thin-walled portion 10, from which the punch 60 comes out. Moreover, a substrate 1 having a thin-walled portion 10 shown in
FIGS. 15A and 15B may be used. The thin-walled portion 10 is provided by a projection 19 integrally molded with the substrate 1 such that an outer surface of the projection is used to form the conductive layer 40, and the projection 19 has a cavity (=concave 14) therein. In this case, at least a part of the projection 19 is removed together with the conductive layer 40 and the additional metal film 50 by punching, drilling, cutting, grinding or end milling in order to provide the electrical insulation between the circuit patterns (20, 22) with a high degree of reliability. In addition, when the projection 19 is removed by performing the end milling 88 from an adequate direction, it is possible to effectively reduce the occurrence of burrs or peeling of the circuit patterns around the through-hole 15 formed in the thin-walled portion 10 by the end milling.
When the substrate is made from an electrically-insulating resin material, it is preferred to heat the substrate 1 prior to the step of removing the thin-walled portion 10 with the conductive layer 40 and the additional metal film 50. In this case, since the substrate becomes soft by heating, it is possible to easily and efficiently remove the thin-walled portion 10 by punching. (Second Embodiment) In this embodiment, as shown in FIGS. 16A and 16B, before the step of removing the thin-walled portion 10 with the conductive layer 40 and the additional metal film 50 from the substrate 1, an auxiliary substrate 70 having at least one projection 72 is placed under the substrate, i.e., at a side opposed to the top surface having the conductive layer 40 of the substrate 1. The auxiliary substrate 70 is preferably made from a metal material such as silver, aluminum and copper. Next, the auxiliary substrate 70 is moved toward the substrate 1, as shown by the arrows in FIG. 16A, so that the thin-walled portion 10 with the conductive layer 40 and the additional metal film 50 is punched by use of the projections 72. Then, the auxiliary substrate 70 is bonded to the substrate 1 under the condition that the projections 72 pass through the substrate 1 , as shown in FIG. 16B. When an adhesive is used to bond the auxiliary substrate 70 to the substrate 1 , it is preferred to use an epoxy resin or an acrylic resin as the adhesive. When the auxiliary substrate 70 is made from a resin material having excellent thermal conductivity and electrical insulating property, the auxiliary substrate may be bonded to the substrate by pressing the projections 72 into the substrate 1 without using the adhesive.
When the auxiliary substrate 70 is made from the metal material, it is preferred that the projection 72 has a recess 76 in its side surface. When the projection 72 passes through the thin-walled portion 10, a clearance D is provided between the side surface of the projection 72 and the circuit patterns (20, 22, 50) on the substrate 1 , as shown in FIG. 16B. This clearance D presents the electrical insulation therebetween. In addition, the auxiliary substrate 70 of the metal material also functions as a heat sink. Of course, to improve desired properties of the substrate, the auxiliary substrate 70 may be made from a ceramic material or a resin material.
In addition, as another application, of the projections 72 of the auxiliary substrate '70, a dent (not shown) for mounting an electronic part such as LED may be formed in a top of the projection. In this case, an electrical connection between the electronic part and a required circuit pattern on the substrate can be made by wire bonding. (Third Embodiment)
In this embodiment, a substrate 1 having thin-walled portions 10, which are defined between a flat top 12 and concaves 14 formed in its bottom surface, is used, as shown in FIG. 17A. Next, a first, second and third circuit patterns (20, 22, 24) electrically isolated from each other are formed on the flat top 12 of the substrate 1 (FIG. 17B). In addition, conductive layers 40 are formed on the thin-walled portions 10 to make a temporary electrical connection between these circuit patterns. As described in the first embodiment, from the viewpoint of improving manufacturing efficiency, it is particularly preferred that the formation of the first, second and third circuit patterns (20, 22, 24) and the formation of the conductive layers 40 are performed at a time by laser-patterning a metal thin film on the substrate 1.
Subsequently, as shown in FIG. 17D, electroplating is performed by the passage of electric current through those circuit patterns (20, 22, 24) connected by the conductive layers 40 to simultaneously form an additional metal film 50 on those circuit patterns. Then, an auxiliary substrate 70 having projections 72 is bonded to the substrate 1 such that each of projections fits into the corresponding concave 14 of the substrate. Each of the projections 72 has a through hole 74. Subsequently, the thin-walled portions 10 are punched from the above of the flat top of the substrate 1 by use of punches 60, so that the punches proceed into the through holes 74 of the projections 72. Thus, since the auxiliary substrate 70 works as a punch receiving die, it is possible to accurately punch the thin-walled portions 10, as shown in FIG. 17E. In addition, since the thin-walled portions 10 can be removed without using a dedicated die for holding the substrate 1 , it is useful to save the manufacturing cost. Moreover, when the auxiliary substrate 70 is made from a metal material, it also works as a heat sink. Similarly, the auxiliary substrate may be used for the substrate 1 shown in FIG. 14. In this case, the thin-walled portions 10 are punched from the above of the additional metal film 50 formed on the substrate 1 by use of the punches 60.
INDUSTRIAL APPLICABILITY
In the present invention, the conductive layer for making a temporary electrical connection between circuit patterns isolated from each other is formed on the thin-walled portion of the substrate, and then electroplating is performed by the passage of electric current through the circuit patterns connected by the conductive layer, so that a metal film can be formed on those circuit patterns at a time by electroplating. This brings an advantage of saving time required for the electroplating step in the method of manufacturing the printed wiring boards. In addition, after the electroplating step, the electrical insulation between the circuit patterns can be readily obtained with reliability by removing the thin-walled portion with the conductive layer from the substrate by, for example, punching or the use of a laser beam. Thus, the present invention is particularly useful to efficiently manufacture high-density printed wiring boards.

Claims

CLAIMS:
1. A method of producing a printed wiring board comprising the steps of: providing a substrate with a thin-walled portion; forming a first circuit pattern on said substrate; forming a second circuit pattern isolated from the first circuit pattern on said substrate; forming a conductive layer on said thin-walled portion to make a temporary electrical connection between the first and second circuit patterns; performing electroplating by the passage of electric current through the first and second circuit patterns connected by the conductive layer to simultaneously form a metal film on the first and second circuit patterns; and after the electroplating, removing said thin-walled portion with the conductive layer to provide electrical insulation between the first and second circuit patterns.
2. The method as set forth in claim 1 , wherein said thin-walled portion is defined between a flat top of said substrate, on which the conductive layer is formed, and a bottom of a concave formed in a bottom surface of said substrate.
3. The method as set forth in claim 1 , wherein said thin-walled portion is defined between a flat bottom of said substrate, and a bottom of a concave formed in a top surface of said substrate, on which the conductive layer is formed.
4. The method as set forth in claim 1 , wherein said thin-walled portion is defined between a bottom of a first concave formed in a top surface of said substrate and a bottom of a second concave formed in a bottom surface of said substrate, and wherein the conductive layer is formed on the bottom of at least one of said first and second concaves.
5. The method as set forth in claim 1 , wherein said thin-walled portion is provided by a projection integrally molded with said substrate such that an outer surface of said projection is used to form the conductive layer, and said projection has a cavity therein, and wherein at least a part of said projection is removed together with the conductive layer to provide the electrical insulation between the first and second circuit patterns.
6. The method as set forth in claim 1 , wherein said thin-walled portion has at least one through hole around the conductive layer formed thereon.
7. The method as set forth in claim 1 , wherein said thin-walled portion has a pair of notches in the vicinity of opposite ends of said thin-walled portion in an extending direction of the conductive layer, and wherein said thin-walled portion between said notches is removed together with the conductive layer to provide the electrical insulation between the first and second circuit patterns.
8. The method as set forth in claim 1, wherein the step of removing said thin-walled portion with the conductive layer comprises the sub-steps of: placing an auxiliary substrate with a projection at a side opposed to the conductive layer of said substrate; punching said thin-walled portion with the conductive layer by use of said projection; and bonding said auxiliary substrate to said substrate, while maintaining an electrical insulation between said projection passing through said substrate and the first and second circuit patterns.
9. The method as set forth in claim 8, wherein said projection has a recess formed in its side surface to provide the electrical insulation between said projection passing through said substrate and the first and second circuit patterns
10. The method as set forth in claim 2, wherein the step of removing said thin-walled portion with the conductive layer comprises the sub-steps of: providing an auxiliary substrate having a projection and a hole passing through said projection in its axial direction; attaching said auxiliary substrate to said substrate such that said projection fits into the concave of said substrate; and punching said thin-walled portion from the above of the flat top of said substrate by use of a punch, so that said punch proceeds into the hole of said projection.
11. The method as set forth in claim 1 , wherein said substrate is heated prior to the step of removing said thin-walled portion with the conductive layer.
12. The method as set forth in claim 1 , wherein the step of removing said thin-walled portion with the conductive layer is performed by use of a punch, while applying ultrasonic vibrations to said punch.
13. The method as set forth in claim 1 , wherein the step of removing said thin-walled portion with the conductive layer is performed by use of a laser beam.
14. The method as set forth in claim 1 , wherein the step of removing said thin-walled portion with the conductive layer is performed by use of a jet of fluid selected from a liquid, a powder and a mixture thereof.
15. The method as set forth in claim 1 , wherein said substrate is made from a ceramic material.
16. The method as set forth in claim 1 , wherein the first and second circuit patterns and the conductive layer are formed at a time by patterning a metal thin film provided on said substrate.
17. The method as set forth in claim 16, wherein said patterning includes a laser patterning.
18. A substrate used in the method as set forth in claim 1 , and having a thin-walled portion, which is adapted to form a conductive layer for making a temporary electrical connection between circuit patterns isolated from each other on said substrate.
19. A method of manufacturing a printed wiring board comprising: forming a metal thin film on a substrate having a thin-walled portion; providing an initial circuit pattern on said substrate by patterning the metal thin film, said initial circuit pattern comprising first and second circuit patterns isolated from each other and a conductive layer formed on said thin-walled portion to make a temporary electrical connection between the first and second circuit patterns; performing electroplating by the passage of electric current through the initial circuit pattern to form an additional metal film on the initial circuit pattern; and after the electroplating, removing said thin-walled portion with the conductive layer to provide electrical insulation between the first and second circuit patterns.
PCT/JP2002/007684 2002-07-29 2002-07-29 Method of manufacturing printed wiring boards and substrate used for the method WO2004012487A1 (en)

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AU2002319914A AU2002319914A1 (en) 2002-07-29 2002-07-29 Method of manufacturing printed wiring boards and substrate used for the method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107072037A (en) * 2017-03-15 2017-08-18 西华大学 A kind of circuit board and a kind of net substrate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3601522A (en) * 1970-06-18 1971-08-24 American Lava Corp Composite ceramic package breakaway notch
DE3843230C1 (en) * 1988-12-22 1989-09-21 W.C. Heraeus Gmbh, 6450 Hanau, De Process for making a metallic pattern on a base, in particular for the laser structuring of conductor tracks
JPH03183190A (en) * 1989-12-12 1991-08-09 Satosen Co Ltd Manufacture of printed-circuit board
US5112230A (en) * 1991-01-14 1992-05-12 Motorola, Inc. Reconfigurable substrate for electric circuit connections
JPH1093225A (en) * 1997-10-20 1998-04-10 Ibiden Co Ltd Manufacturing method of printed wiring board
US5834833A (en) * 1996-03-21 1998-11-10 Nec Corporation Electrical component having a selective cut-off conductor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3601522A (en) * 1970-06-18 1971-08-24 American Lava Corp Composite ceramic package breakaway notch
DE3843230C1 (en) * 1988-12-22 1989-09-21 W.C. Heraeus Gmbh, 6450 Hanau, De Process for making a metallic pattern on a base, in particular for the laser structuring of conductor tracks
JPH03183190A (en) * 1989-12-12 1991-08-09 Satosen Co Ltd Manufacture of printed-circuit board
US5112230A (en) * 1991-01-14 1992-05-12 Motorola, Inc. Reconfigurable substrate for electric circuit connections
US5834833A (en) * 1996-03-21 1998-11-10 Nec Corporation Electrical component having a selective cut-off conductor
JPH1093225A (en) * 1997-10-20 1998-04-10 Ibiden Co Ltd Manufacturing method of printed wiring board

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 015, no. 438 (E - 1130) 8 November 1991 (1991-11-08) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 09 31 July 1998 (1998-07-31) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107072037A (en) * 2017-03-15 2017-08-18 西华大学 A kind of circuit board and a kind of net substrate

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