WO2004012485A2 - Mounting surfaces for electronic devices - Google Patents

Mounting surfaces for electronic devices Download PDF

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Publication number
WO2004012485A2
WO2004012485A2 PCT/US2003/022548 US0322548W WO2004012485A2 WO 2004012485 A2 WO2004012485 A2 WO 2004012485A2 US 0322548 W US0322548 W US 0322548W WO 2004012485 A2 WO2004012485 A2 WO 2004012485A2
Authority
WO
WIPO (PCT)
Prior art keywords
mounting surface
stamped
gap
mount
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/022548
Other languages
French (fr)
Other versions
WO2004012485A3 (en
Inventor
Jr. Frank J. Mosna
Alexander J. Elliot
William M. Strom
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Motorola Inc filed Critical Freescale Semiconductor Inc
Priority to AU2003256617A priority Critical patent/AU2003256617A1/en
Publication of WO2004012485A2 publication Critical patent/WO2004012485A2/en
Publication of WO2004012485A3 publication Critical patent/WO2004012485A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/421Shapes or dispositions
    • H10W70/433Shapes or dispositions of deformation-absorbing parts, e.g. leads having meandering shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/811Multiple chips on leadframes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49121Beam lead frame or beam lead device

Definitions

  • the present invention relates generally to mounting electronic devices.
  • FIG. 1 illustrates aspects of a conventional multi-die package.
  • the package has a power die 110 and a control die 120, both of which are secured to a mounting surface (commonly called a "flag" 130).
  • the power die 110 and the control die 120 must be electrically isolated.
  • One conventional method is to attach at least one die (such as the control die 120) to the flag 130 with a non-conductive epoxy compound (not seen).
  • the epoxy compound is applied by placing dots of epoxy compound on the flag 130 and then using pressure to push the control die 120 onto the flag 130. The epoxy compound is squeezed out evenly under the control die 120. If the epoxy compound layer is too thin, however, there is not enough electrical isolation. This may cause the control die 120 or the power die 110 to short.
  • To electrically isolate the control die 110 ' and the power die 120 by physically isolating the mounting surfaces of the control die 110 and the power die 120 has proven to be difficult or costly. First, to simply create two separate mounting surfaces and then attach each of those mounting surfaces to another leadframe (not illustrated), requires more components than a single flag 130. This increases cost and forces a larger package size.
  • stamping two mounting surfaces out of a single material is constrained because stamping causes the stamped material to become bent or deformed. This deformation interferes with the assembly and operation of the electronic package.
  • the thicker the material to be stamped the greater the required physical isolation of the two mounting surfaces. This drives up the total size of the package.
  • FIG. 1 shows a control die and a power die attached to a flag in accordance with the prior art.
  • FIG. 2 shows the result of forming a plurality of mounting surfaces in accordance with the present invention.
  • FIG. 3 shows a reduced gap between two mounting surfaces in accordance with the present invention.
  • FIG. 4 shows two singulated mounting surfaces in accordance with the present invention.
  • FIG. 5 shows two mounting surfaces attached to the leadframe in accordance with the present invention.
  • FIG. 6 shows two mounting surfaces with the gap filled in accordance with the present invention.
  • FIG. 7 shows an electronic device package with two electronic devices mounted on two mounting surfaces in accordance with the present invention.
  • FIG. 2 illustrates various aspects of an example embodiment of the present invention.
  • a method of making a mount for at least two electronic devices comprises stamping a first mounting surface 210 from a material 240 and stamping a second mounting surface 220 from the material 240.
  • the material 240 comprises oxygen-free high-conductive copper alloy, but in alternate embodiments, any suitable material is substituted for copper alloy.
  • first mounting surfaces 210 and second mounting surfaces 220 are stamped out of the same material 240 wherein the second stamped surface 220 is mechanically connected with the first surface 210.
  • the mounting surfaces 210 and 220 are stamped by progressive stamping with a standard stamping tool, which stamps out the shape to be formed by making many individual stamps.
  • the hatched region indicates the areas of the material 240 that are removed.
  • the first mounting surface 210 and the second mounting surface 220 are, in some embodiments, stamped with a collapsible connection 230 on either side of the first mounting surface 210 and second mounting surface 220. Between the first mounting surface 210 and the second mounting surface 220 is a gap 250. Attachment holes 280 are formed on either side of the first mounting surface 210 and the second mounting surface 220. The function of these attachment holes 280 is explained below. Conventional stamping cannot stamp the gap 250 between the first mounting surface 210 and the second mounting surface 220 less than about 1.5 times the thickness of the material 240 (for most materials and stamping methods).
  • the first mounting surface 210 and the second mounting surface 220 are stamped with a gap 250, which is at least 1.2 times the thickness of the material 240; and, many times, is greater than 1.5 times the thickness of material 240.
  • the thickness of the material 240 causes the gap 250 to be too large. Therefore, it is desirable for the gap 250 to be reduced.
  • FIG. 3 illustrates an example embodiment of the first mounting surface 210 and the second mounting surface 220 with the gap 250 reduced.
  • various methods are used to reduce the gap 250 to below the 1.5 or 1.2 times material thickness limit.
  • a force is used to deform the collapsible connection 230 and bring the first mounting surface 210 and the second mounting surface 220 closer together.
  • applying a force on the outside 274 of the first mounting surface 210 and the outside 275 of the second mounting surface 220 deforms the collapsible connection 230.
  • force is applied to the outsides 272 and 273 of the collapsible connection 230.
  • the force is applied with a conventional tool or a tool specifically designed for reducing the gap 250.
  • conventional tools include stamping tools, clamps, presses, and crimpers to name only a few.
  • a specifically designed tool (not illustrated) uses a N-shape. The open end of the "N" is pressed downward on the outsides 274 and 275 to provide a narrowing surface against which the first and second mounting surfaces 210 and 220 are pressed.
  • a curved shape here in the specific form of an "S"
  • any deformable connection suffices.
  • the collapsible connection 230 is not limited to the type of deforming associated with a curved shape.
  • a straight connection having a weak area bends upon application of pressure.
  • a straight link with no designed-in weakened area is used.
  • the first mounting surface 210, the second mounting surface 220, and the collapsible connections 230 are "singulated” by, for example, cutting them from the outer edges 260 (sometimes called “rails") and the rest of the material 240.
  • FIG. 4 illustrates a singulated first mounting surface 210 and second mounting surface 220, with attachment holes 280, and two collapsible connections 230.
  • the singulated first mounting surface 210 and second mounting surface 220 are mounted onto a leadframe 510.
  • the leadframe 510 includes a plurality of leads 520, which are used to provide electrical communication to electronic devices to be mounted on first and second mounting surfaces 210 and 220.
  • the leadframe 510 comprises holes (not seen), which correspond to the attachment holes 280 on either side of the first mounting surface 210 and the second mounting surface 220.
  • the first mounting surface 210 and second mounting surface 220 are staked to the leadframe 510 by staking a pin or rivet through the attachment holes 280 on either side of the first mounting surface 210 and second mounting surface 220 and the leadframe 510.
  • the edges of the pin or rivet are deformed, securing the mounting surfaces 210 and 220 to the leadframe 510.
  • the mounting surfaces 210 and 220 are attached to the leadframe 510 by soldering, gluing, or any other method of attaching.
  • the collapsible connections 230 are removed (e.g., by cutting). By removing the collapsible connections 230, the first mounting surface 210 and the second mounting surface 220 are physically and electrically isolated.
  • circuit 700 As seen in FIG. 7, with the first mounting surface 210 and the second mounting surface 220 electrically isolated and attached to the leadframe 510, electronic components 720 and 730 are attached to the first and second mounting surfaces 210 and 220 (for example, by soldering, gluing, or any other method of attaching electronic components) creating a circuit 700.
  • an encapsulant is applied and surrounds the circuit 700 and fills the gap 250. Filling the gap 250 further electrically isolates the first mounting surface 210 and the second mounting surface 220.
  • the encapsulant comprises plastic, rubber, or any other encapsulant used in semiconductor technology.
  • the material of the first electronic component mounting surface 210 and the second electronic component mounting surface 220 is thicker than the material of the leadframe 510, which also provides heat dissipation.

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)
  • Casings For Electric Apparatus (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A mount, packaged device, and method of making the same are provided. In one embodiment, a method for making a mount for at least two electronic devices comprises forming a first mounting surface (210) from a material (240), and forming a second mounting surface (220) from the material (240). The first mounting surface (210) is connected to, but spaced from, the second mounting surface (220) by a mounting surface distance (250). The method further comprises reducing the mounting surface distance (250).

Description

MOUNTING SURFACES FOR ELECTRONIC DEVICES
BACKGROUND OF THE INVENTION:
The present invention relates generally to mounting electronic devices.
FIG. 1 illustrates aspects of a conventional multi-die package. The package has a power die 110 and a control die 120, both of which are secured to a mounting surface (commonly called a "flag" 130).
In many applications, the power die 110 and the control die 120 must be electrically isolated. One conventional method is to attach at least one die (such as the control die 120) to the flag 130 with a non-conductive epoxy compound (not seen). Typically, the epoxy compound is applied by placing dots of epoxy compound on the flag 130 and then using pressure to push the control die 120 onto the flag 130. The epoxy compound is squeezed out evenly under the control die 120. If the epoxy compound layer is too thin, however, there is not enough electrical isolation. This may cause the control die 120 or the power die 110 to short. To electrically isolate the control die 110 ' and the power die 120 by physically isolating the mounting surfaces of the control die 110 and the power die 120 has proven to be difficult or costly. First, to simply create two separate mounting surfaces and then attach each of those mounting surfaces to another leadframe (not illustrated), requires more components than a single flag 130. This increases cost and forces a larger package size.
Furthermore, stamping two mounting surfaces out of a single material is constrained because stamping causes the stamped material to become bent or deformed. This deformation interferes with the assembly and operation of the electronic package. Thus, the thicker the material to be stamped, the greater the required physical isolation of the two mounting surfaces. This drives up the total size of the package.
BRIEF DESCRIPTIONS OF THE FIGURES:
FIG. 1 shows a control die and a power die attached to a flag in accordance with the prior art.
FIG. 2 shows the result of forming a plurality of mounting surfaces in accordance with the present invention.
FIG. 3 shows a reduced gap between two mounting surfaces in accordance with the present invention.
FIG. 4 shows two singulated mounting surfaces in accordance with the present invention. FIG. 5 shows two mounting surfaces attached to the leadframe in accordance with the present invention.
FIG. 6 shows two mounting surfaces with the gap filled in accordance with the present invention.
FIG. 7 shows an electronic device package with two electronic devices mounted on two mounting surfaces in accordance with the present invention.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE PRESENT INVENTION:
FIG. 2 illustrates various aspects of an example embodiment of the present invention. In one example embodiment, a method of making a mount for at least two electronic devices is provided. The method comprises stamping a first mounting surface 210 from a material 240 and stamping a second mounting surface 220 from the material 240. Commonly, the material 240 comprises oxygen-free high-conductive copper alloy, but in alternate embodiments, any suitable material is substituted for copper alloy. Depending on manufacturing conditions, in some embodiments, many first mounting surfaces 210 and second mounting surfaces 220 are stamped out of the same material 240 wherein the second stamped surface 220 is mechanically connected with the first surface 210.
In the illustrated embodiment, the mounting surfaces 210 and 220 are stamped by progressive stamping with a standard stamping tool, which stamps out the shape to be formed by making many individual stamps. The hatched region indicates the areas of the material 240 that are removed.
The first mounting surface 210 and the second mounting surface 220 are, in some embodiments, stamped with a collapsible connection 230 on either side of the first mounting surface 210 and second mounting surface 220. Between the first mounting surface 210 and the second mounting surface 220 is a gap 250. Attachment holes 280 are formed on either side of the first mounting surface 210 and the second mounting surface 220. The function of these attachment holes 280 is explained below. Conventional stamping cannot stamp the gap 250 between the first mounting surface 210 and the second mounting surface 220 less than about 1.5 times the thickness of the material 240 (for most materials and stamping methods).
In no case is it believed a material suitable for electronics can be stamped closer than about 1.2 times the thickness. Therefore, the first mounting surface 210 and the second mounting surface 220 are stamped with a gap 250, which is at least 1.2 times the thickness of the material 240; and, many times, is greater than 1.5 times the thickness of material 240. However, for many applications, the thickness of the material 240 causes the gap 250 to be too large. Therefore, it is desirable for the gap 250 to be reduced.
FIG. 3 illustrates an example embodiment of the first mounting surface 210 and the second mounting surface 220 with the gap 250 reduced. In example embodiments of the invention, various methods are used to reduce the gap 250 to below the 1.5 or 1.2 times material thickness limit. Generally, a force is used to deform the collapsible connection 230 and bring the first mounting surface 210 and the second mounting surface 220 closer together. For example, applying a force on the outside 274 of the first mounting surface 210 and the outside 275 of the second mounting surface 220 deforms the collapsible connection 230. In another example, force is applied to the outsides 272 and 273 of the collapsible connection 230. In alternate embodiments, the force is applied with a conventional tool or a tool specifically designed for reducing the gap 250. Examples of conventional tools include stamping tools, clamps, presses, and crimpers to name only a few. In one embodiment, a specifically designed tool (not illustrated) uses a N-shape. The open end of the "N" is pressed downward on the outsides 274 and 275 to provide a narrowing surface against which the first and second mounting surfaces 210 and 220 are pressed. Although the illustrated example shows a curved shape (here in the specific form of an "S") for the collapsible connection 230, any deformable connection suffices. For example, the collapsible connection 230 is not limited to the type of deforming associated with a curved shape. In still a further embodiment, a straight connection having a weak area (for example, a thinner cross-section than surrounding portions of material 240) bends upon application of pressure. In still a further embodiment, a straight link with no designed-in weakened area is used. An important function of the collapsible connection 230, in any event, is that it comprises a deformable means for holding the mounting surfaces 210 and 220 at the distance at which they are formed while being pliable enough to reduce the gap 250 to a distance desired for use in a package upon application (directly or indirectly) of some force to the connection 230.
In a further embodiment, once the gap 250 is reduced to a desired distance, the first mounting surface 210, the second mounting surface 220, and the collapsible connections 230 are "singulated" by, for example, cutting them from the outer edges 260 (sometimes called "rails") and the rest of the material 240. FIG. 4 illustrates a singulated first mounting surface 210 and second mounting surface 220, with attachment holes 280, and two collapsible connections 230.
In still a further embodiment, as illustrated in FIG. 5, the singulated first mounting surface 210 and second mounting surface 220 are mounted onto a leadframe 510. The leadframe 510 includes a plurality of leads 520, which are used to provide electrical communication to electronic devices to be mounted on first and second mounting surfaces 210 and 220. The leadframe 510 comprises holes (not seen), which correspond to the attachment holes 280 on either side of the first mounting surface 210 and the second mounting surface 220. The first mounting surface 210 and second mounting surface 220 are staked to the leadframe 510 by staking a pin or rivet through the attachment holes 280 on either side of the first mounting surface 210 and second mounting surface 220 and the leadframe 510. The edges of the pin or rivet are deformed, securing the mounting surfaces 210 and 220 to the leadframe 510. In various alternate embodiments, the mounting surfaces 210 and 220 are attached to the leadframe 510 by soldering, gluing, or any other method of attaching.
In a further embodiment, illustrated in FIG. 6, once the first mounting surface 210 and the second mounting surface 220 are attached to the leadframe 510, the collapsible connections 230 are removed (e.g., by cutting). By removing the collapsible connections 230, the first mounting surface 210 and the second mounting surface 220 are physically and electrically isolated.
As seen in FIG. 7, with the first mounting surface 210 and the second mounting surface 220 electrically isolated and attached to the leadframe 510, electronic components 720 and 730 are attached to the first and second mounting surfaces 210 and 220 (for example, by soldering, gluing, or any other method of attaching electronic components) creating a circuit 700.
In still a further embodiment, after electronic components 720 and 730 are mounted on the mounting surfaces 210 and 220, an encapsulant is applied and surrounds the circuit 700 and fills the gap 250. Filling the gap 250 further electrically isolates the first mounting surface 210 and the second mounting surface 220. In various embodiments, the encapsulant comprises plastic, rubber, or any other encapsulant used in semiconductor technology. In some embodiments, one side of each of the mounting surfaces 210 and
220 is not encapsulated. Instead, the mounting surfaces 210 and 220 are left exposed to dissipate heat. In some embodiments (for example, power packages), the material of the first electronic component mounting surface 210 and the second electronic component mounting surface 220 is thicker than the material of the leadframe 510, which also provides heat dissipation.
The example embodiments of the present invention have been described with a certain degree of particularity; however, many changes may be made in the details without departing from the scope of the invention. It is understood that the invention is not limited to the embodiments set forth herein, but is to be limited only by the scope of the attached claims, including the full range of equivalency to which each is entitled.

Claims

We claim:
1. A method of making a mount for at least two electronic devices, the method comprising: stamping a first mounting surface (210) from a material (240); stamping a second mounting surface (220) from the material, wherein the first mounting surface is connected to, but spaced from, the second mounting surface by a mounting surface gap (250); and reducing the mounting surface gap.
2. The method of claim 1, wherein the reducing comprises reducing the mounting surface gap to less than about 1.5 times the thickness of the material.
3. The method of claim 1, wherein the stamping a second mounting surface comprises forming a collapsible connection (230) that connects the first mounting surface and the second mounting surface, and reducing comprises deforming the collapsible connection.
4. The method of claim 1, further comprising electrically isolating the first mounting surface and the second mounting surface.
5. The method of claim 4, further comprising encapsulating the first mounting surface and the second mounting surface within a same plastic package,
6. The method of claim 1, wherein the first mounting surface and the second mounting surface are stamped essentially concurrently.
7. A packaged electronic device comprising: a first stamped mounting surface (210) and a second stamped mounting surface (220), wherein the first stamped mounting surface and the second stamped mounting surface comprise the same material; a gap (250) between the first stamped mounting surface and the second stamped mounting surface; a first electronic device (720) mounted on the first stamped mounting surface; and a second electronic device (730) mounted on the second stamped mounting surface; wherein the gap is less than about 1.5 times a thickness of the first stamped mounting surface.
8. The package of claim 7, further comprising an encapsulant covering at least a portion of the first stamped mounting surface.
9. The package of claim 20, wherein the encapsulant substantially fills the
gap-
10. The package of claim 7 wherein the first electronic device and the second electronic device are electrically isolated.
11. A mount for at least two electronic components, the mount comprising: a first mounting surface (210); a second mounting surface (220); and a deformable means (230) for holding the first mounting surface and the second mounting surface.
12. A mount as in claim 11, wherein the deformable means comprises a substantially straight link.
13. A mount as in claim 11, wherein the deformable means comprises a curved shape.
14. A mount as in claim 13, wherein the deformable means comprises a S shape.
PCT/US2003/022548 2002-07-31 2003-07-17 Mounting surfaces for electronic devices Ceased WO2004012485A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003256617A AU2003256617A1 (en) 2002-07-31 2003-07-17 Mounting surfaces for electronic devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/208,867 2002-07-31
US10/208,867 US6996897B2 (en) 2002-07-31 2002-07-31 Method of making a mount for electronic devices

Publications (2)

Publication Number Publication Date
WO2004012485A2 true WO2004012485A2 (en) 2004-02-05
WO2004012485A3 WO2004012485A3 (en) 2004-04-08

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PCT/US2003/022548 Ceased WO2004012485A2 (en) 2002-07-31 2003-07-17 Mounting surfaces for electronic devices

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US (1) US6996897B2 (en)
AU (1) AU2003256617A1 (en)
MY (1) MY146202A (en)
TW (1) TWI326473B (en)
WO (1) WO2004012485A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6996897B2 (en) * 2002-07-31 2006-02-14 Freescale Semiconductor, Inc. Method of making a mount for electronic devices
US7012324B2 (en) 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Lead frame with flag support structure
US20070134409A1 (en) * 2004-03-10 2007-06-14 Frankiewicz Gregory P Light-Pipe Arrangement with Reduced Fresnel-Reflection Losses
US7445967B2 (en) * 2006-01-20 2008-11-04 Freescale Semiconductor, Inc. Method of packaging a semiconductor die and package thereof
WO2018087027A1 (en) * 2016-11-11 2018-05-17 Lumileds Holding B.V. Method of manufacturing a lead frame

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559401A (en) 1978-07-05 1980-01-23 Hitachi Ltd Leed frame
JPS61257443A (en) * 1985-05-08 1986-11-14 Mitsubishi Shindo Kk Cu alloy as lead material for semiconductor device
US4829362A (en) 1986-04-28 1989-05-09 Motorola, Inc. Lead frame with die bond flag for ceramic packages
JPH0350758A (en) 1989-07-18 1991-03-05 Toshiba Corp Resin seal type semiconductor device
US5068764A (en) 1990-03-05 1991-11-26 Thermalloy Incorporated Electronic device package mounting assembly
CA2037006A1 (en) 1990-03-16 1991-09-17 Hisao Go Lead frame
US5049973A (en) 1990-06-26 1991-09-17 Harris Semiconductor Patents, Inc. Heat sink and multi mount pad lead frame package and method for electrically isolating semiconductor die(s)
JP3088193B2 (en) * 1992-06-05 2000-09-18 三菱電機株式会社 Method for manufacturing semiconductor device having LOC structure and lead frame used therein
US5233222A (en) 1992-07-27 1993-08-03 Motorola, Inc. Semiconductor device having window-frame flag with tapered edge in opening
US5767443A (en) 1993-07-10 1998-06-16 Micron Technology, Inc. Multi-die encapsulation device
DE4404986B4 (en) * 1994-02-17 2008-08-21 Robert Bosch Gmbh Device for contacting electrical conductors and method for producing such a device
US5566749A (en) 1994-04-12 1996-10-22 Thermalloy, Inc. Stamped and formed heat sink
US5594234A (en) 1994-11-14 1997-01-14 Texas Instruments Incorporated Downset exposed die mount pad leadframe and package
JP2767404B2 (en) * 1994-12-14 1998-06-18 アナムインダストリアル株式会社 Lead frame structure of semiconductor package
JPH0964266A (en) 1995-08-18 1997-03-07 Sony Corp Lead frame
SG46955A1 (en) 1995-10-28 1998-03-20 Inst Of Microelectronics Ic packaging lead frame for reducing chip stress and deformation
US5739586A (en) 1996-08-30 1998-04-14 Scientific-Atlanta, Inc. Heat sink assembly including a printed wiring board and a metal case
US5856911A (en) 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
JPH10321791A (en) 1997-03-17 1998-12-04 Tokai Rika Co Ltd Operational amplifier device
EP0887850A3 (en) 1997-06-23 2001-05-02 STMicroelectronics, Inc. Lead-frame forming for improved thermal performance
US6049125A (en) 1997-12-29 2000-04-11 Micron Technology, Inc. Semiconductor package with heat sink and method of fabrication
JP4090103B2 (en) * 1998-03-02 2008-05-28 太陽インキ製造株式会社 Photosensitive composition and fired product pattern obtained using the same
US5969949A (en) 1998-03-31 1999-10-19 Sun Microsystems, Inc. Interfitting heat sink and heat spreader slug
US5969950A (en) 1998-11-04 1999-10-19 Sun Microsystems, Inc. Enhanced heat sink attachment
US6163068A (en) 1999-04-22 2000-12-19 Yao; Hsia Kuang Multi-chip semiconductor encapsulation method and its finished product
US6395983B1 (en) * 1999-05-18 2002-05-28 Pulse Engineering, Inc. Electronic packaging device and method
US6996897B2 (en) * 2002-07-31 2006-02-14 Freescale Semiconductor, Inc. Method of making a mount for electronic devices

Also Published As

Publication number Publication date
TW200405485A (en) 2004-04-01
US6996897B2 (en) 2006-02-14
MY146202A (en) 2012-07-31
WO2004012485A3 (en) 2004-04-08
AU2003256617A1 (en) 2004-02-16
TWI326473B (en) 2010-06-21
US20040022016A1 (en) 2004-02-05
AU2003256617A8 (en) 2004-02-16

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