WO2004012092A3 - Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif - Google Patents

Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif Download PDF

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Publication number
WO2004012092A3
WO2004012092A3 PCT/FR2003/002313 FR0302313W WO2004012092A3 WO 2004012092 A3 WO2004012092 A3 WO 2004012092A3 FR 0302313 W FR0302313 W FR 0302313W WO 2004012092 A3 WO2004012092 A3 WO 2004012092A3
Authority
WO
WIPO (PCT)
Prior art keywords
master
method implemented
bus
modules
matrix bus
Prior art date
Application number
PCT/FR2003/002313
Other languages
English (en)
Other versions
WO2004012092A2 (fr
Inventor
Didier Marie Francois Rousseau
Original Assignee
Genod
Didier Marie Francois Rousseau
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Genod, Didier Marie Francois Rousseau filed Critical Genod
Priority to AU2003273461A priority Critical patent/AU2003273461A1/en
Publication of WO2004012092A2 publication Critical patent/WO2004012092A2/fr
Publication of WO2004012092A3 publication Critical patent/WO2004012092A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Abstract

L'invention concerne un dispositif de bus matriciel entre une pluralité de modules maîtres et une pluralité de modules esclaves. Ce dispositif comprend une pluralité de modules d'arbitrage répartis dans la matrice, à l'intersection entre chaque module maître et chaque module esclave. Le bus peut être de type SoC. Avantageusement, au sein de cette architecture matricielle, les arbitres et les contrôleurs sont distribués. Ce bus permet des communications en parallèle, en mode point à point ainsi que des transmissions en mode diffusion (un maître et plusieurs esclaves).
PCT/FR2003/002313 2002-07-25 2003-07-22 Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif WO2004012092A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003273461A AU2003273461A1 (en) 2002-07-25 2003-07-22 Multiple master, multiple slave matrix bus device, and method implemented in such a device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR02/09419 2002-07-25
FR0209419A FR2842922B1 (fr) 2002-07-25 2002-07-25 Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif

Publications (2)

Publication Number Publication Date
WO2004012092A2 WO2004012092A2 (fr) 2004-02-05
WO2004012092A3 true WO2004012092A3 (fr) 2004-04-08

Family

ID=30011459

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2003/002313 WO2004012092A2 (fr) 2002-07-25 2003-07-22 Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif

Country Status (3)

Country Link
AU (1) AU2003273461A1 (fr)
FR (1) FR2842922B1 (fr)
WO (1) WO2004012092A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050220731A1 (en) * 2004-03-23 2005-10-06 Philippe Ilekti Nail varnish composition comprising at least one polymer and at least one plasticizer
FR2928758B1 (fr) * 2008-03-13 2012-10-12 Mbda France Systeme de routage de donnees.

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053942A (en) * 1988-11-01 1991-10-01 The Regents Of The University Of California Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system
US5168570A (en) * 1989-12-29 1992-12-01 Supercomputer Systems Limited Partnership Method and apparatus for a multiple request toggling priority system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053942A (en) * 1988-11-01 1991-10-01 The Regents Of The University Of California Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system
US5168570A (en) * 1989-12-29 1992-12-01 Supercomputer Systems Limited Partnership Method and apparatus for a multiple request toggling priority system

Also Published As

Publication number Publication date
FR2842922A1 (fr) 2004-01-30
FR2842922B1 (fr) 2004-11-05
AU2003273461A1 (en) 2004-02-16
AU2003273461A8 (en) 2004-02-16
WO2004012092A2 (fr) 2004-02-05

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