FR2842922B1 - Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif - Google Patents

Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif

Info

Publication number
FR2842922B1
FR2842922B1 FR0209419A FR0209419A FR2842922B1 FR 2842922 B1 FR2842922 B1 FR 2842922B1 FR 0209419 A FR0209419 A FR 0209419A FR 0209419 A FR0209419 A FR 0209419A FR 2842922 B1 FR2842922 B1 FR 2842922B1
Authority
FR
France
Prior art keywords
master
method implemented
matrix bus
slave matrix
slave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0209419A
Other languages
English (en)
Other versions
FR2842922A1 (fr
Inventor
Didier Marie Francois Rousseau
Patrick Mahe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GENOD
Original Assignee
GENOD
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GENOD filed Critical GENOD
Priority to FR0209419A priority Critical patent/FR2842922B1/fr
Priority to PCT/FR2003/002313 priority patent/WO2004012092A2/fr
Priority to AU2003273461A priority patent/AU2003273461A1/en
Publication of FR2842922A1 publication Critical patent/FR2842922A1/fr
Application granted granted Critical
Publication of FR2842922B1 publication Critical patent/FR2842922B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
FR0209419A 2002-07-25 2002-07-25 Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif Expired - Fee Related FR2842922B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0209419A FR2842922B1 (fr) 2002-07-25 2002-07-25 Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif
PCT/FR2003/002313 WO2004012092A2 (fr) 2002-07-25 2003-07-22 Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif
AU2003273461A AU2003273461A1 (en) 2002-07-25 2003-07-22 Multiple master, multiple slave matrix bus device, and method implemented in such a device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0209419A FR2842922B1 (fr) 2002-07-25 2002-07-25 Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif

Publications (2)

Publication Number Publication Date
FR2842922A1 FR2842922A1 (fr) 2004-01-30
FR2842922B1 true FR2842922B1 (fr) 2004-11-05

Family

ID=30011459

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0209419A Expired - Fee Related FR2842922B1 (fr) 2002-07-25 2002-07-25 Dispositif de bus matriciel multi-maitres, multi-esclaves, et procede mis en oeuvre dans un tel dispositif

Country Status (3)

Country Link
AU (1) AU2003273461A1 (fr)
FR (1) FR2842922B1 (fr)
WO (1) WO2004012092A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050220731A1 (en) * 2004-03-23 2005-10-06 Philippe Ilekti Nail varnish composition comprising at least one polymer and at least one plasticizer
FR2928758B1 (fr) * 2008-03-13 2012-10-12 Mbda France Systeme de routage de donnees.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053942A (en) * 1988-11-01 1991-10-01 The Regents Of The University Of California Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system
US5168570A (en) * 1989-12-29 1992-12-01 Supercomputer Systems Limited Partnership Method and apparatus for a multiple request toggling priority system

Also Published As

Publication number Publication date
WO2004012092A2 (fr) 2004-02-05
AU2003273461A8 (en) 2004-02-16
FR2842922A1 (fr) 2004-01-30
WO2004012092A3 (fr) 2004-04-08
AU2003273461A1 (en) 2004-02-16

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20060331