AU2003273461A1 - Multiple master, multiple slave matrix bus device, and method implemented in such a device - Google Patents

Multiple master, multiple slave matrix bus device, and method implemented in such a device

Info

Publication number
AU2003273461A1
AU2003273461A1 AU2003273461A AU2003273461A AU2003273461A1 AU 2003273461 A1 AU2003273461 A1 AU 2003273461A1 AU 2003273461 A AU2003273461 A AU 2003273461A AU 2003273461 A AU2003273461 A AU 2003273461A AU 2003273461 A1 AU2003273461 A1 AU 2003273461A1
Authority
AU
Australia
Prior art keywords
method implemented
matrix bus
master
slave matrix
bus device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003273461A
Other versions
AU2003273461A8 (en
Inventor
Didier Marie Francois Rousseau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GENOD
Original Assignee
GENOD
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GENOD filed Critical GENOD
Publication of AU2003273461A1 publication Critical patent/AU2003273461A1/en
Publication of AU2003273461A8 publication Critical patent/AU2003273461A8/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
AU2003273461A 2002-07-25 2003-07-22 Multiple master, multiple slave matrix bus device, and method implemented in such a device Abandoned AU2003273461A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR02/09419 2002-07-25
FR0209419A FR2842922B1 (en) 2002-07-25 2002-07-25 MULTI-MASTER, MULTI-SLAVE MATRIX BUS DEVICE AND METHOD IMPLEMENTED IN SUCH A DEVICE
PCT/FR2003/002313 WO2004012092A2 (en) 2002-07-25 2003-07-22 Multiple master, multiple slave matrix bus device, and method implemented in such a device

Publications (2)

Publication Number Publication Date
AU2003273461A1 true AU2003273461A1 (en) 2004-02-16
AU2003273461A8 AU2003273461A8 (en) 2004-02-16

Family

ID=30011459

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003273461A Abandoned AU2003273461A1 (en) 2002-07-25 2003-07-22 Multiple master, multiple slave matrix bus device, and method implemented in such a device

Country Status (3)

Country Link
AU (1) AU2003273461A1 (en)
FR (1) FR2842922B1 (en)
WO (1) WO2004012092A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050220731A1 (en) * 2004-03-23 2005-10-06 Philippe Ilekti Nail varnish composition comprising at least one polymer and at least one plasticizer
FR2928758B1 (en) * 2008-03-13 2012-10-12 Mbda France DATA ROUTING SYSTEM.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053942A (en) * 1988-11-01 1991-10-01 The Regents Of The University Of California Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system
US5168570A (en) * 1989-12-29 1992-12-01 Supercomputer Systems Limited Partnership Method and apparatus for a multiple request toggling priority system

Also Published As

Publication number Publication date
FR2842922A1 (en) 2004-01-30
FR2842922B1 (en) 2004-11-05
WO2004012092A3 (en) 2004-04-08
AU2003273461A8 (en) 2004-02-16
WO2004012092A2 (en) 2004-02-05

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase