WO2004008490A2 - Egalisateur de connexion selectionnable, egalisateur auto-configure, circuit de reception possedant une fonction d'etalonnage d'egalisateur et systeme a caracteristiques de reflexion groupees - Google Patents

Egalisateur de connexion selectionnable, egalisateur auto-configure, circuit de reception possedant une fonction d'etalonnage d'egalisateur et systeme a caracteristiques de reflexion groupees Download PDF

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Publication number
WO2004008490A2
WO2004008490A2 PCT/US2003/021566 US0321566W WO2004008490A2 WO 2004008490 A2 WO2004008490 A2 WO 2004008490A2 US 0321566 W US0321566 W US 0321566W WO 2004008490 A2 WO2004008490 A2 WO 2004008490A2
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WIPO (PCT)
Prior art keywords
thε
signal
circuit
data
values
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PCT/US2003/021566
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English (en)
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WO2004008490A3 (fr
Inventor
Jared L. Zerbe
Vladimir M. Stojanovic
Fred F. Chen
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Rambus Inc.
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Priority claimed from US10/195,129 external-priority patent/US7292629B2/en
Priority claimed from US10/195,140 external-priority patent/US8861667B1/en
Priority claimed from US10/195,130 external-priority patent/US7362800B1/en
Application filed by Rambus Inc. filed Critical Rambus Inc.
Priority to AU2003251839A priority Critical patent/AU2003251839A1/en
Publication of WO2004008490A2 publication Critical patent/WO2004008490A2/fr
Publication of WO2004008490A3 publication Critical patent/WO2004008490A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive

Definitions

  • the pr ⁇ s ⁇ nt invention relates generally to high spe ⁇ d signaling within and b ⁇ tween int ⁇ grated circuit devices, and more particularly to reducing latent signal distortions in high spe ⁇ d signaling systems.
  • Equalizing driver circuits are often used in high spe ⁇ d signaling syst ⁇ ms to mitigat ⁇ th ⁇ ⁇ ff ⁇ cts of int ⁇ r-symbol int ⁇ rf ⁇ r ⁇ nc ⁇ and crosstalk.
  • signaling system 100 of Figur ⁇ 1 for example, data values queu ⁇ d in buff ⁇ r 104 ar ⁇ output to signal path 102 by output driv ⁇ r 101 simultaneously with transmission of an equalizing signal by equalizing driver 109.
  • the equalizing driv ⁇ r 109 includ ⁇ s a shift r ⁇ gist ⁇ r 113 and a bank of output driv ⁇ rs 111 to g ⁇ n ⁇ rate an equalizing signal based on the two most rec ⁇ ntly transmitt ⁇ d data valu ⁇ s and the data value to be transmitted after the present, ref ⁇ r ⁇ nce value.
  • the ⁇ qualizing driv ⁇ r 109 constitutes a thre ⁇ -tap (i. ⁇ ., thr ⁇ data sourc ⁇ ) equalizer for reducing inter- symbol interference that results from disp ⁇ rsion of signals transmitt ⁇ d n ⁇ ar in tim ⁇ to the r ⁇ f ⁇ r ⁇ nc ⁇ valu ⁇ (i. ⁇ ., disp ⁇ rsion-typ ⁇ ISI).
  • Whil ⁇ the ⁇ qualizing driv ⁇ r 109 is ⁇ ff ⁇ ctiv ⁇ for r ⁇ ducing relatively low-latency distortions such as dispersion-typ ⁇ 1ST, oth ⁇ r typ ⁇ s of syst ⁇ matic distortions, such as signal r ⁇ fl ⁇ ctions (also r ⁇ f ⁇ rr ⁇ d to as r ⁇ fl ⁇ ction-typ ⁇ ISI), tend to have a much higher latency (i. ⁇ ., occur much later in time r ⁇ lative to transmission of the ref ⁇ r ⁇ nc ⁇ value) and therefore would require a substantially larger number of taps and a correspondingly larg ⁇ r shift r ⁇ gist ⁇ r to count ⁇ ract.
  • relatively low-latency distortions such as dispersion-typ ⁇ 1ST
  • oth ⁇ r typ ⁇ s of syst ⁇ matic distortions such as signal r ⁇ fl ⁇ ctions (also r ⁇ f ⁇ rr ⁇ d to as r ⁇ fl ⁇ ction-typ ⁇ ISI
  • a first refl ⁇ ction, A T occurs wh ⁇ n a ref ⁇ r ⁇ nce signal encounters an imp ⁇ danc ⁇ discontinuity at a transmit-sid ⁇ interfac ⁇ 105 between a transmit-side portion (102A) and a backplan ⁇ portion (102B) of the signal path 102 (e.g., a connector interfac ⁇ to a backplan ⁇ ).
  • th ⁇ reflection will arrive at the input of a rec ⁇ iv ⁇ r 103 with a lat ⁇ ncy (i.e., d ⁇ lay r ⁇ lativ ⁇ to arrival of th ⁇ unr ⁇ fl ⁇ cted ref ⁇ r ⁇ nc ⁇ signal) ⁇ qual to approximately twic ⁇ th ⁇ r ⁇ fl ⁇ ction flight tim ⁇ b ⁇ tw ⁇ n th ⁇ transmit-sid ⁇ int ⁇ rfac ⁇ 105 and th ⁇ transmit circuit output.
  • a lat ⁇ ncy i.e., d ⁇ lay r ⁇ lativ ⁇ to arrival of th ⁇ unr ⁇ fl ⁇ cted ref ⁇ r ⁇ nc ⁇ signal
  • Figure 2 is a wav ⁇ form diagram of reflections A , A R , B, C T , C R and D illustrating their r ⁇ sp ⁇ ctiv ⁇ latencies r ⁇ lative to reference signal arrival time, T (A2 TR corresponds to additional reflections produced by the int ⁇ rface 105). Because such reflections may occur at latenci ⁇ s on th ⁇ order of tens or ev ⁇ n hundreds of signal transmission intervals, the shift regist ⁇ r 113 would n ⁇ d to b ⁇ substantially deeper in order to store the tap values need ⁇ d to mitigat ⁇ th ⁇ resulting distortions.
  • the precise tim ⁇ at which r ⁇ fl ⁇ ctions arriv ⁇ at the receiv ⁇ r 103 ar ⁇ d ⁇ p ⁇ nd ⁇ nt upon syst ⁇ m configuration meaning that a gen ⁇ rally applicable equalizer, whether implem ⁇ nt ⁇ d on th ⁇ transmit or receiv ⁇ sid ⁇ of the signaling syst ⁇ m 100, would need a relatively large number of equalizing taps to be able to compensat ⁇ for a r ⁇ fl ⁇ ction occurring at any tim ⁇ b ⁇ tw ⁇ en the signal transmit time and a worst case lat ⁇ ncy.
  • each additional equalizing tap increases the parasitic capacitance of the transmit or receive circuit, degrading the fr ⁇ qu ⁇ ncy r ⁇ spons ⁇ of th ⁇ circuit and pot ⁇ ntially increasing th ⁇ imp ⁇ dance discontinuity (and therefore the magnitude of reflected signal) at the circuit input/output.
  • Th ⁇ present invention is illustrated by way of ⁇ xampl ⁇ , and not by way of limitation, in th ⁇ figures of the accompanying drawings and in which like r ⁇ f ⁇ r ⁇ nc ⁇ num ⁇ rals r ⁇ f ⁇ r to similar elem ⁇ nts and in which:
  • Figure 1 illustrates a prior-art signaling system
  • Figure 2 is a waveform diagram of refl ⁇ ct ⁇ d signals produced by the prior-art signaling system of Figure 1 ;
  • Figure 3 illustrat ⁇ s a signaling syst ⁇ m according an ⁇ mbodim ⁇ nt of th ⁇ invention
  • Figure 4 illustrates an ex ⁇ mplary relationship b ⁇ tw ⁇ n clock and data signals in th ⁇ signaling syst ⁇ m of Figure 3
  • Figure 5 illustrates the manner in which pre- ⁇ mphasis and s ⁇ l ⁇ ctabl ⁇ - tap equalization are employed to reduce low- and high-latency distortions in th ⁇ signaling syst ⁇ m of Figure 3;
  • Figure 6 illustrates a transmit device having circuitry for s ⁇ l ⁇ cting betwe ⁇ n t ⁇ mporal ⁇ qualization and cross-talk cancellation data sources;
  • Figure 7 illustrates transmit and receive devices configured to perform near-end cross-talk cancellation;
  • Figure 8 illustrates a transceiver device that includes both an ⁇ qualizing transmitt ⁇ r and an equalizing receiv ⁇ r
  • Figure 9 illustrates an equalizing transceiv ⁇ r according to an ⁇ mbodim ⁇ nt in which both transmitt ⁇ d and receiv ⁇ d data valu ⁇ s are stor ⁇ d and s ⁇ l ⁇ ctiv ⁇ ly us ⁇ d to source ⁇ qualiz ⁇ r taps;
  • Figure 10 illustrates an ⁇ x ⁇ mplary buff ⁇ r that may b ⁇ us ⁇ d within the receiv ⁇ r of Figure 3;
  • Figure 11 is a flow diagram of an ⁇ xemplary method of s ⁇ l ⁇ cting a data valu ⁇ having desired symbol latency from the buffer of Figure 10;
  • Figure 12 illustrates an ex ⁇ mplary ⁇ mbodim ⁇ nt of a tap s ⁇ l ⁇ ct circuit
  • Figure 13 illustrates an ex ⁇ mplary embodiment of the select logic of Figure 12
  • Figure 14 illustrates a gen ⁇ raliz ⁇ d sel ⁇ ct circuit that may b ⁇ us ⁇ d to s ⁇ l ⁇ ct Q tap values from the buffer circuit of Figure 12;
  • Figure 15 illustrat ⁇ s an ⁇ mbodim ⁇ nt of a switch ⁇ l ⁇ m ⁇ nt that may b ⁇ us ⁇ d within th ⁇ switch matrix of Figure 14;
  • Figure 16 illustrat ⁇ s an embodiment of an equalizing receiv ⁇ r;
  • Figure 17 illustrat ⁇ s th ⁇ rec ⁇ iv ⁇ circuit of Figure 16 in greater detail
  • Figure 18 illustrates an exemplary timing relationship between clock, data and equalization signals in the equalizing receiver of Figure 16;
  • Figure 19 illustrates a current-sinking output driv ⁇ r that may be used within the equalizing receiv ⁇ r of Figure 16;
  • Figure 20 illustrates an embodim ⁇ nt of a push-pull typ ⁇ of sub-driver circuit that may be us ⁇ d within an ⁇ qualizing output driv ⁇ r;
  • Figure 21 illustrates another ⁇ mbodim ⁇ nt of a sub-driv ⁇ r circuit that may b ⁇ us ⁇ d within an equalizing output driver
  • Figure 22 illustrates an Var ⁇ type of equalizing circuit that may be us ⁇ d in ⁇ mbodim ⁇ nts of th ⁇ inv ⁇ ntion;
  • Figure 23 illustrates an embodiment of a lev ⁇ l shifting circuit that may be used within the equalizing circuit of Figure 22;
  • Figure 24 illustrates another type of equalizing circuit that may be used in embodiments of the invention;
  • Figure 25 illustrates an embodiment of a level shifting circuit that us ⁇ d within th ⁇ ⁇ qualizing circuit of Figure 24;
  • Figure 26 illustrates an equalizing receiver according to an embodiment of the invention;
  • Figure 27 illustrates a shift regist ⁇ r and tap selector that may be us ⁇ d within th ⁇ ⁇ qualizing r ⁇ c ⁇ iv ⁇ r of Figure 26;
  • Figure 28 illustrates an equalizing receiver for receiving a double data rate, multilev ⁇ l input signal according to an embodiment of the invention
  • Figure 29 illustrates an exemplary encoding of bits according to the level of a sampled, multilevel input signal
  • Figure 30 illustrat ⁇ s an ex ⁇ mplary timing relationship b ⁇ tw ⁇ en clock, data and equalization signals in an equalizing receiv ⁇ r;
  • Figure 31 illustrates an ⁇ mbodim ⁇ nt of an ⁇ qualizing receiver that generat ⁇ s r ⁇ c ⁇ iv ⁇ and ⁇ qualization clock signals having th ⁇ phas ⁇ relationship shown in Figure 30;
  • Figure 32 illustrat ⁇ s the use of embedded scoping to gen ⁇ rate a trace of a data signal ov ⁇ r a singl ⁇ symbol time;
  • Figure 33 illustrates an embodiment of a signaling system that employs ⁇ mb ⁇ dded scoping to determine equalizer tap selections, tap weights and tap polarities;
  • Figure 34 illustrates an exemplary trace record for a pulse waveform captured by an emb ⁇ dded scope within the signaling system of Figure 33;
  • Figure 35 illustrates a method of setting equalization coefficients in a signaling system according to the invention.
  • Figure 36 illustrat ⁇ s a signaling system that employs path length symmetry to reduce the total number of equalization taps ne ⁇ ded to compensate for reflection-type ISI.
  • circuit el ⁇ m ⁇ nts or circuit blocks may be shown as multi-conductor or single conductor signal lines.
  • Each of the multi-conductor signal lines may alternatively be singl ⁇ signal conductor lines, and each of the single conductor signal lines may alt ⁇ rnativ ⁇ ly b ⁇ multi-conductor signal lines.
  • a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic stat ⁇ or discharged to a low logic state) to indicate a particular condition.
  • a signal is said to b ⁇ "d ⁇ ass ⁇ rt ⁇ d” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating stat ⁇ that may occur wh ⁇ n th ⁇ signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition).
  • a signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled betw ⁇ n th ⁇ signal driving and signal receiving circuits.
  • a signal line is said to be “activated” wh ⁇ n a signal is asserted on the signal line, and “deactivated” when the signal is deasserted.
  • th ⁇ prefix symbol "/" attached to signal names indicat ⁇ s that th ⁇ signal is an active low signal (i.e., the asserted state is a logic low state).
  • a line over a signal name (e.g., ' ⁇ signal name > ') is also used to indicate an active low signal. Active low signals may be changed to active high signals and vice-versa as is gen ⁇ rally known in the art.
  • equalizing refers to counteracting, canceling or otherwise reducing signal distortion.
  • equalizing refers to counteracting, canceling or otherwise reducing signal distortion.
  • hi one embodim ⁇ nt, low-latency distortions e.g., disp ⁇ rsion-type
  • ISI, cross-talk, etc. are reduced by a transmit-side ⁇ qualization circuit, and high-latency distortions (e.g., signal reflections) ar ⁇ reduced by a rec ⁇ iv ⁇ -sid ⁇ equalization circuit; the lat ⁇ ncy of r ⁇ c ⁇ iv ⁇ -sid ⁇ equalization taps being offset relative to the reception time of a ref ⁇ r ⁇ nc ⁇ signal by th ⁇ numb ⁇ r of transmit- side equalization taps.
  • a s ⁇ lect circuit is provided to selectively route a relativ ⁇ ly small subs ⁇ t of th ⁇ stored data values to equalizing taps within the equalizing rec ⁇ iver. By this arrangem ⁇ nt, reflected signals arriving at various, latent times may be counteracted by routing of selected stored data valu ⁇ s to the rec ⁇ ive-side equalization taps.
  • the parasitic capacitance of the equalizing rec ⁇ iver is small relativ ⁇ to th ⁇ parasitic capacitance that would result from providing a dedicated tap for each stor ⁇ d data valu ⁇ .
  • Signaling System with Selectable-Tap Equalizer Figure 3 illustrates a signaling system 117 according to an ⁇ mbodim ⁇ nt of the invention.
  • the system 117 includes an equalizing transmitter 115 and equalizing receiver 116 coupled to one another via a high-spe ⁇ d signal path 122, and a controller 141 coupl ⁇ d to th ⁇ transmitt ⁇ r 115 and the receiv ⁇ r 116 via relatively low-speed signal paths 142A and 142B, respectively.
  • the signal path 122 is formed by component signal paths 122 A, 122B and 122C ( ⁇ .g., transmission lin ⁇ s that introduce respective, nonzero propagation delays and exhibit resp ⁇ ctiv ⁇ impedance characteristics), each disposed on respective circuit boards that are coupled to one another via circuit board interfac ⁇ s 125 and 127 ( ⁇ .g., connectors).
  • signal path 122B is form ⁇ d on a backplan ⁇ and signal paths
  • 122A and 122C ar ⁇ form ⁇ d on respective daughterboards (e.g., line cards) that are removably coupled to the backplane via connectors 125 and 127.
  • the transmitt ⁇ r 115 and r ⁇ c ⁇ iv ⁇ r 116 ar ⁇ impl ⁇ mented in r ⁇ sp ⁇ ctiv ⁇ int ⁇ grat ⁇ d circuit (IC) devices that are mounted on the daughterboards.
  • the controller which may be a g ⁇ neral or special purpos ⁇ processor, state machin ⁇ or other logic circuit, is impl ⁇ m ⁇ nt ⁇ d within a third int ⁇ grated circuit device mounted to a yet another circuit board.
  • signal paths 142 A and 142B ar ⁇ us ⁇ d to convey configuration information from the controller 141 to the transmitter 115 and rec ⁇ iv ⁇ r 116, r ⁇ sp ⁇ ctiv ⁇ ly, and may b ⁇ dispos ⁇ d on the sam ⁇ circuit board (or circuit boards) as signal path 122 or impl ⁇ mented by an Cod ⁇ structure such as a cable.
  • the controller may Var ⁇ ly b ⁇ coupl ⁇ d to th ⁇ transmitter 115 and rec ⁇ iv ⁇ r 116 by a shared signal path such as a multi-drop bus. Th ⁇ op ⁇ ration of th ⁇ controller 141 is discussed in greater detail below.
  • th ⁇ IC d ⁇ vices containing the transmitter 115, rec ⁇ iv ⁇ r 116 and controller 141 may be mounted to a common structure with the signaling paths 122, 142A and 142B coupled directly to the IC devices (e.g., all thre ⁇ ICs mount ⁇ d to a circuit board and coupled to one another via circuit board traces, or all thre ⁇ ICs packaged within a single multi-chip module with signal paths 122 and 142 formed b ⁇ tw ⁇ n the ICs by bond wires or oth ⁇ r conducting structures).
  • IC devices e.g., all thre ⁇ ICs mount ⁇ d to a circuit board and coupled to one another via circuit board traces, or all thre ⁇ ICs packaged within a single multi-chip module with signal paths 122 and 142 formed b ⁇ tw ⁇ n the ICs by bond wires or oth ⁇ r conducting structures.
  • the transmitter 115, r ⁇ c ⁇ iv ⁇ r 116 and controller 141, or any subset thereof, may be included within the same IC devic ⁇ ( ⁇ .g., syst ⁇ m on chip) and th ⁇ signaling paths 122 and/or 142 implemented by a metal layer or other conducting structure within th ⁇ IC d ⁇ vice.
  • IC devic ⁇ ⁇ .g., syst ⁇ m on chip
  • th ⁇ signaling paths 122 and/or 142 implemented by a metal layer or other conducting structure within th ⁇ IC d ⁇ vice.
  • the transmitter 115 transmits data on the signaling path 122 during succ ⁇ ssiv ⁇ tim ⁇ intervals, ref ⁇ rr ⁇ d to herein as symbol times.
  • ⁇ ach symbol time, Ts corresponds to a half cycle of a transmit clock signal, TCLK, such that two data values (e.g., valu ⁇ s A and B) are transmitted on signaling path 122 per transmit clock cycle.
  • Th ⁇ transmitt ⁇ d data signal arriv ⁇ s at th ⁇ input of receiver 116 after propagation time, Tp, and is sampled by the rec ⁇ iver 116 in r ⁇ spons ⁇ to ⁇ dges of a receive clock signal, RCLK.
  • th ⁇ receive clock signal has a quadrature phase relation to data valid windows (i.e., data eyes) in the incoming data signal such that each sample is captured at the midpoint of a data ey ⁇ .
  • data valid windows i.e., data eyes
  • th ⁇ sampling instant may b ⁇ skewed relative to data eye midpoints as necessary to satisfy signal setup and hold time requirements in the receiver 116.
  • more or f ⁇ wer symbols may be transmitted per cycle of the transmit clock signal.
  • the ⁇ qualizing transmitt ⁇ r 115 includ ⁇ s a transmit shift regist ⁇ r 124, output driv ⁇ r 121 and transmit ⁇ qualizer 129; the transmit equalizer 129 itself including a shift register 120 and a bank of output drivers 131.
  • the data value at th ⁇ h ⁇ ad of the transmit shift regist ⁇ r 124 referred to herein as the primary data value, is driv ⁇ n onto the signal path 122 by the output driv ⁇ r 121, and the equalizer 129 simultaneously drives an equalizing signal onto the signal path 122.
  • This type of ⁇ qualization is referred to herein as transmit preemphasis.
  • the signal driven onto th ⁇ signal path 122 by th ⁇ output driver 121 (referred to herein as the primary signal) is a multi-lev ⁇ l signal having on ⁇ of four possibl ⁇ stat ⁇ s ( ⁇ .g., d ⁇ fin ⁇ d by four distinct signal ranges) and therefore constitutes a symbol repr ⁇ s ⁇ ntativ ⁇ of two binary bits of information.
  • th ⁇ primary signal may hav ⁇ more or f ⁇ w ⁇ r possibl ⁇ states and therefore represent more or few ⁇ r than two binary bits.
  • th ⁇ primary signal may b ⁇ singl ⁇ - ⁇ nd ⁇ d or diff ⁇ r ⁇ ntial (an additional signal line is provid ⁇ d to carry th ⁇ compl ⁇ m ⁇ nt signal in th ⁇ differential case), and may be a voltage or current mode signal.
  • Each of the output driv ⁇ rs 131 within th ⁇ equalizing circuit 129 form either a pre-tap driver or post-tap driver according to whether the source data value has already been transmitted (post-tap data) or is yet to be transmitted
  • th ⁇ equalizer includes N post-tap drivers sourced by data valu ⁇ s within th ⁇ shift r ⁇ gist ⁇ r 120 and one pre-tap driver sourced by a data valu ⁇ within th ⁇ transmit shift register 124.
  • the resultant equalizing signal driven onto the data path 122 will have a signal level according to data values having symbol latencies of -1, 1,
  • the rec ⁇ iv ⁇ r 116 includes a sampling circuit 123, buffer 132, tap sel ⁇ ct circuit 128 and tap select logic 139. Data signals are sampled by the sampling circuit 123, then stored in the buffer 134 for eventual use by application logic (not shown). Because the buffered data is stored for at least a predetermined time, and represents historical data up to a pred ⁇ termin ⁇ d numb ⁇ r of symbol latencies, the buffered data forms an ideal source of post-tap data values.
  • buff ring of r ⁇ c ⁇ iv ⁇ d data in r ⁇ c ⁇ iv ⁇ r 116 incurs no additional storage overh ⁇ ad b ⁇ caus ⁇ th ⁇ r ⁇ c ⁇ iv ⁇ d data values ar ⁇ buffered in any event to facilitate transfer to receiv ⁇ -sid ⁇ application logic.
  • th ⁇ tap s ⁇ lect circuit 128 enabl ⁇ s a subs ⁇ t of data valu ⁇ s within th ⁇ buff ⁇ r ⁇ d data to b ⁇ s ⁇ lected to source equaliz ⁇ r taps in a r ⁇ c ⁇ iv ⁇ -side equalizer circuit.
  • a relativ ⁇ ly small numb ⁇ r of data valu ⁇ s may b ⁇ selected to form receiv ⁇ -side equalization taps having lat ⁇ ncies that match th ⁇ latencies of the distortions.
  • high latency distortions may be reduced by rec ⁇ iv ⁇ -side equalization without dramatically increasing the parasitic capacitance of the receiver (i.e., as would result from a large number of receiv ⁇ -sid ⁇ ⁇ qualization taps).
  • the tap s ⁇ l ⁇ ct logic is a configuration circuit that outputs a tap s ⁇ l ⁇ ct signal 134 according to a configuration value.
  • the configuration value may be automatically generated by system 117 (e.g., at system startup) or may be empirically d ⁇ t ⁇ rmin ⁇ d and stored within the configuration circuit or els ⁇ wh ⁇ r ⁇ within syst ⁇ m 117.
  • the receiv ⁇ r 116 includes an output driv ⁇ r 140 (illustrated in dashed outline in Figure 3 to indicate its optional nature) to drive an equalizing signal onto the signal path 122 (and therefore to the input of the sampling circuit 123) coincidentally with the symbol time of an incoming signal.
  • the sampling circuit 123 includes a preamplifier having an equalizing subcircuit.
  • an ⁇ qualizing subcircuit is coupl ⁇ d to the sampling circuit itself.
  • the distribution of low- and high-latency equalization functions b ⁇ tw ⁇ n th ⁇ ⁇ qualizing transmitt ⁇ r 115 and equalizing rec ⁇ iv ⁇ r 116 is achi ⁇ v ⁇ d through us ⁇ of a d ⁇ ad rang ⁇ within the receive-side buffer 132. That is, the range of stored data values that may be selected to source receiv ⁇ -sid ⁇ equalization taps (i. ⁇ ., R) is offs ⁇ t from the sampling instant by a number of symbol times, M.
  • M is equal to N
  • the rec ⁇ iv ⁇ r 116 is said to have a dead range of four symbol times.
  • buffer 132 is formed by a shift register having a dead range component 133 and a sel ⁇ ctabl ⁇ -rang ⁇ component 135, the tap selector 128 being coupl ⁇ d to th ⁇ s ⁇ l ⁇ ctable-range component 135 to s ⁇ l ⁇ ct th ⁇ subset of tap data sources therefrom.
  • th ⁇ d ⁇ ad rang ⁇ component of the buff ⁇ r 132 may include few ⁇ r than M storag ⁇ ⁇ l ⁇ m ⁇ nts or even zero storage el ⁇ m ⁇ nts, d ⁇ p ⁇ nding on th ⁇ tim ⁇ required to r ⁇ c ⁇ iv ⁇ data and transf ⁇ r data into th ⁇ buff ⁇ r 132.
  • th ⁇ tap selector 128 may be coupled to one or more storag ⁇ ⁇ l ⁇ ments within the dead range component 133 to enabl ⁇ th ⁇ siz ⁇ of the dead range to be programmed according to the configuration of the transmit circuit 115.
  • th ⁇ buff ⁇ r 132 may include one or more parallel r ⁇ gist ⁇ rs in addition to (or instead of) the shift register formed by components 133 and 135.
  • Figure 5 illustrates the manner in which pre- ⁇ mphasis at the transmitter 115 and selectable-tap equalization within the receiver 116 are employed to reduce low- and high-latency distortions in the signaling syst ⁇ m of Figur ⁇ 3.
  • the primary signal is transmitted during a transmit interval 149 (i.e., a symbol time) that starts at time T, and the corresponding primary value is used to generate a transmit-side equalization signal (i.e., pre ⁇ mphasis signal) ov ⁇ r a window of N symbol tim ⁇ s following th ⁇ transmit int ⁇ rval 149.
  • a transmit-side equalization signal i.e., pre ⁇ mphasis signal
  • Th ⁇ transmit-side equalization signal is used to reduce low-latency distortions that may result from any number of sources including, without limitation, dispersion-typ ⁇ ISI, inductive and capacitive coupling (which may be compensated, for exampl ⁇ , by sourcing a pr ⁇ - ⁇ mphasis output driv ⁇ r within bank 131 with a valu ⁇ being transmitted on a neighboring signal path), and low-latency refl ⁇ ctions ( ⁇ .g., r ⁇ fl ⁇ ctions that do not trav ⁇ l significantly further than the unrefl ⁇ cted primary signal and therefore arrive at the rec ⁇ iver shortly aft ⁇ r th ⁇ primary signal).
  • sources including, without limitation, dispersion-typ ⁇ ISI, inductive and capacitive coupling (which may be compensated, for exampl ⁇ , by sourcing a pr ⁇ - ⁇ mphasis output driv ⁇ r within bank 131 with a valu ⁇ being transmitted on a neighboring signal path), and low-latency refl ⁇
  • the primary signal is sampled by the rec ⁇ iver 116 during a reception interval (i.e., data valid window) that corresponds to the transmit interval 149, the reception interval being shifted relative to the transmit int ⁇ rval according to th ⁇ signal flight time betw ⁇ n the transmitter 115 and rec ⁇ iv ⁇ r 116.
  • Th ⁇ s ⁇ l ⁇ ctable-tap equaliz ⁇ r within th ⁇ rec ⁇ iv ⁇ r 116 has a dead range of M symbol tim ⁇ s and a selectable range of R symbol times.
  • th ⁇ sampled primary value (i.e., the primary received during the reception interval) is s ⁇ l ⁇ ctabl ⁇ to sourc ⁇ an equalizer tap within the rec ⁇ iver 116 when the symbol latency of the sampled primary value is great ⁇ r than M symbol tim ⁇ s and l ⁇ ss or ⁇ qual to R symbol tim ⁇ s.
  • previously r ⁇ c ⁇ ived values having symbol latencies ranging from M+l to R may be selected by the tap sel ⁇ ctor 128 of Figur ⁇ 3 and us ⁇ d to reduce high-latency distortions.
  • Intervals 150 l3 150 , and 150 within interval 153 illustrate equalization windows achi ⁇ v ⁇ d by tap s ⁇ l ⁇ ctions within th ⁇ tap selector 128.
  • interval 150 ⁇ corresponds to one or more tap selections used to ⁇ qualize a distortion occurring shortly aft ⁇ r th ⁇ dead rang ⁇
  • interval 150 corresponds to one or more tap s ⁇ lections used to reduce a distortion caused by a signal transmission dozens or even hundreds of symbol times prior to the current reception interval.
  • the polarity of signal contributions which form the transmit preemphasis signal may b ⁇ fix ⁇ d or programmable and may be established (or controlled) within the data shift regist ⁇ rs (i. ⁇ ., 124 and 120) or by the output drivers thems ⁇ lv ⁇ s ( ⁇ .g., output driv ⁇ rs within bank 131).
  • the polarity of signal contributions which form th ⁇ receiv ⁇ r equalization signal may be fixed or programmable and may be establish ⁇ d (or controlled) within a data storage circuit (i.e., buff ⁇ r 132) or within a r ⁇ c ⁇ iv ⁇ r ⁇ qualization circuit.
  • the controller 141 is used to configure one or more of the values of N, M and R (i.e., the number of transmit-side post-tap ⁇ qualiz ⁇ rs, th ⁇ r ⁇ c ⁇ iv ⁇ -side d ⁇ ad rang ⁇ and th ⁇ r ⁇ c ⁇ ive-sid ⁇ s ⁇ l ⁇ ctabl ⁇ rang ⁇ ) according to syst ⁇ m n ⁇ ds.
  • the controller includes a nonvolatile memory to store ⁇ mpirically or analytically determined values of N, M and R.
  • th ⁇ signaling syst ⁇ m 117 may include a separate storage (e.g., flash memory, or other non- volatile media) to store values of N, M and R (or values that may be used to d ⁇ t ⁇ rmin ⁇ N, M and R), the controller 141 being coupled to access such separat ⁇ storage via signal path 142 or another path.
  • the controller 141 communicates the post-tap equalizer count, N, to the transmitter 115 and the dead range and selectable range valu ⁇ s, M and R, to th ⁇ receiver 116.
  • th ⁇ values of N, M and R may be det ⁇ rmin ⁇ d at production tim ⁇ (e.g., through system testing) or design time, and pre-programm ⁇ d into configuration circuitry within th ⁇ transmitt ⁇ r 115 and/or r ⁇ c ⁇ iv ⁇ r 116, or fix ⁇ d by design of the transmitter 115 and/or receiv ⁇ r 116.
  • th ⁇ controller 141 and signal path 142 may b ⁇ omitt ⁇ d altog ⁇ th ⁇ r.
  • embodiments of the invention may additionally include circuitry to automatically det ⁇ rmin ⁇ distortion lat ⁇ nci ⁇ s and to s ⁇ lect correspondingly latent data tap sources from the buffer 132, thus providing a system-ind ⁇ pendent solution for r ⁇ ducing systematic distortion ev ⁇ nts of virtually any lat ⁇ ncy.
  • the controller 141 may be used to coordinate operation of the transmitter 115 and rec ⁇ iv ⁇ r 116 during such automatic distortion latency det ⁇ rmination, and also to d ⁇ termine appropriat ⁇ s ⁇ ttings of N, M and
  • the transmit-side equalizer 129 may be us ⁇ d to reduce signal distortion resulting from inductive and capacitiv ⁇ coupling of signals transmitt ⁇ d on n ⁇ ighboring signal paths; a type of equalization referred to as far-end cross-talk cancellation.
  • the output driver bank 131 includes additional output driv ⁇ rs to g ⁇ n ⁇ rat ⁇ ⁇ qualization signals bas ⁇ d on valu ⁇ s b ⁇ ing transmitt ⁇ d on signal paths that ar ⁇ adjacent or otherwise proximal to the signal path 122.
  • an equalizing signal having a polarity opposite that of an interfering neighboring signal is transmitted on the signal path 122, ther ⁇ by reducing the signal interf ⁇ r ⁇ nc ⁇ .
  • Th ⁇ numb ⁇ r of ⁇ qualizer taps ne ⁇ d ⁇ d for cross-talk cancellation within a given signaling system is dep ⁇ nd ⁇ nt on th ⁇ physical layout of signal paths relative to one another.
  • ⁇ xampl ⁇ in a syst ⁇ m in which signal paths 122 ar ⁇ arranged relativ ⁇ to on ⁇ anoth ⁇ r such that cross-talk int ⁇ rf ⁇ r ⁇ nc ⁇ is negligible (e.g., paths 122 are spaced apart, arranged in an orthogonal disposition (e.g., twisted pair), etc.), no equaliz ⁇ r taps may b ⁇ n ⁇ d ⁇ d for cross-talk cancellation.
  • on ⁇ or more equaliz ⁇ r taps may b ⁇ n ⁇ d ⁇ d for ⁇ ach adjacent pair of signal paths.
  • ⁇ qualiz ⁇ r taps are sel ⁇ ctively coupled to either pre-tap, post- tap or cross-talk cancellation data sources (i.e., primary value being transmitt ⁇ d on n ⁇ ighboring path).
  • ⁇ qualiz ⁇ r taps may be selectively configured, according to syst ⁇ m requirements, to provide eith ⁇ r t ⁇ mporal ⁇ qualization (i. ⁇ ., pr ⁇ -tap and/or post-tap ⁇ qualization) or cross-talk canc ⁇ llation.
  • Figure 6 illustrat ⁇ s a transmit d ⁇ vice 154 having circuitry for sel ⁇ cting b ⁇ tw ⁇ n temporal equalization and cross-talk cancellation data sources.
  • the transmit device 154 includes transmitters 152 t and 152 , each for transmitting data signals on a respectiv ⁇ signal path 122i and 122 2 .
  • R ⁇ sp ⁇ ctiv ⁇ sources of transmit data values (TX DATA1 and TX DATA2) are provided from other logic (not shown) within transmit d ⁇ vic ⁇ 154.
  • additional transmitters may b ⁇ provid ⁇ d in accordance with the number of signal paths 122 and/or th ⁇ number of sources of transmit data values.
  • Each of the transmitters 152 includes a transmit shift register (124 ls 124 2 ), output driver (121 1 , 121 2 ), post-tap data shift regist ⁇ r (120 1 ⁇ 120 2 ) and output driver bank (131 l5 131 2 ) that operate gen ⁇ rally as d ⁇ scribed in reference to Figure 3.
  • Each transmitt ⁇ r 152 additionally includes a tap data source selector (153 l5 153 2 ) having one or more multipl ⁇ x ⁇ rs for selectively coupling eith ⁇ r a local data value (e.g., a pre-tap or post-tap data value from corresponding transmit shift regist ⁇ r 124 or post-tap data shift register 120) or a remote data value (e.g., a primary value suppli ⁇ d from th ⁇ head of a transmit shift regist ⁇ r 124 of another transmitter, or a post-tap data value supplied from the post-tap data shift regist ⁇ r of anoth ⁇ r transmitter) to be the equalization tap data source.
  • a local data value e.g., a pre-tap or post-tap data value from corresponding transmit shift regist ⁇ r 124 or post-tap data shift register 120
  • a remote data value e.g., a primary value suppli ⁇ d from th ⁇ head of a transmit shift regist ⁇ r 124 of another transmitter,
  • multiplexer A within tap data source sel ⁇ ctor 153 ⁇ has a first input coupled to a storage el ⁇ ment within post-tap data shift register 120 ⁇ and a s ⁇ cond input coupl ⁇ d to th ⁇ output of transmit shift register 124 2 , and selects, according to a select signal SEL , ⁇ ith ⁇ r a post-tap data valu ⁇ within shift regist ⁇ r 120 l5 or th ⁇ r ⁇ mot ⁇ primary valu ⁇ output by shift register
  • Multipl ⁇ x ⁇ r J within tap data source sel ⁇ ctor 153i has a first input coupled to a storage element within the transmit shift regist ⁇ r 124 1 and a second input coupled to th ⁇ output of th ⁇ transmit shift r ⁇ gist ⁇ r 124 2 , and s ⁇ lects, according to a select signal SELu, either a pre-tap data value within the transmit shift regist ⁇ r 124 ls or th ⁇ r ⁇ mot ⁇ primary valu ⁇ to b ⁇ th ⁇ data tap source for an output driver within output driver bank 131 ⁇ .
  • additional multiplex ⁇ rs may b ⁇ provid ⁇ d within th ⁇ tap data source selectors 153 to select betwe ⁇ n local data valu ⁇ s (pre- or post-tap) and remote post-tap data values.
  • select signal SEL IK - Tap data source selector 153 2 similarly includes on ⁇ or more multiplexers to select between pre-tap, post-tap and or cross-talk cancellation data sources for output driver bank 131 2 .
  • output drivers within banks 131 may alternatively be used to generate temporal ⁇ qualization signals or cross-talk cancellation signals according to system ne ⁇ ds.
  • multiplexer A of data source sel ⁇ ctor 153 ⁇ may include one or more inputs to receive pre-tap data values from register 124j, one or more inputs to receive post-tap data values from post-tap register 120 ! , and/or one or more inputs to r ⁇ c ⁇ ive cross-talk canc ⁇ llation data valu ⁇ s (i. ⁇ ., r ⁇ mot ⁇ primary, pr ⁇ -tap and or post-tap valu ⁇ s from any numb ⁇ r of oth ⁇ r transmitt ⁇ rs 152).
  • ⁇ ach output driv ⁇ r within an output driv ⁇ r bank 131 may b ⁇ sourc ⁇ d by a multipl ⁇ x ⁇ r that s ⁇ l ⁇ cts b ⁇ tw ⁇ n any numb ⁇ r of pr ⁇ -tap, post-tap and/or cross-talk cancellation data sources. Also, not all output drivers within output driver banks 131 ne ⁇ d b ⁇ f ⁇ d by multipl ⁇ x ⁇ rs, but rather may be coupled to dedicated tap data sources.
  • the select signals, SEL ⁇ (including signals SEL !A ,
  • SEL U , SEL ⁇ K , ⁇ tc.) and SEL 2 ar ⁇ g ⁇ n ⁇ rat ⁇ d by a configuration circuit (not shown) within transmit device 151 or els ⁇ wher ⁇ in a signaling syst ⁇ m that includes transmit device 151.
  • the configuration circuit may be pre- programm ⁇ d or may be programm ⁇ d at system start-up, for example, by a controller similar to controller 141 of Figure 3.
  • selectiv ⁇ -tap transmit-sid ⁇ pr ⁇ mphasis may b ⁇ us ⁇ d to cancel or reduce interference between signals transmitted in the same direction on neighboring or oth ⁇ rwis ⁇ proximal signal lin ⁇ s (i. ⁇ ., far- ⁇ nd cross-talk).
  • S ⁇ l ⁇ ctiv ⁇ -tap r ⁇ c ⁇ ive-side ⁇ qualization may similarly be used to reduce interference betw ⁇ n outgoing and incoming transmissions on proximal signal lin ⁇ s; int ⁇ rf ⁇ r ⁇ nc ⁇ r ⁇ f ⁇ rr ⁇ d to h ⁇ rein as near- ⁇ nd cross-talk.
  • the transmit device 118 includes an output driver 121, transmit shift register 124, post-tap data shift regist ⁇ r 120, and output driver bank 131, all of which operate gen ⁇ rally as described above in ref ⁇ r ⁇ nc ⁇ to transmit device 115 of Figure 3 to ⁇ nabl ⁇ g ⁇ n ⁇ ration of an ⁇ qualiz ⁇ d transmit signal (TX OUT) on signal path 122 ⁇ .
  • the transmit device 118 may additionally include sel ⁇ ct circuitry as described in ref ⁇ r ⁇ nc ⁇ to Figur ⁇ 6 to enable sel ⁇ ction of various equalization data sources.
  • Th ⁇ receiv ⁇ d ⁇ vic ⁇ 119 includes a sampling circuit 123, buffer 132, tap sel ⁇ ct circuit 137, tap select logic 139 and equalization circuit (e.g., included within the sampling circuit 123 or implement ⁇ d as an output driv ⁇ r 140) to r ⁇ c ⁇ iv ⁇ an incoming signal (RX IN) on signal path 122 2 .
  • RX IN incoming signal
  • TX OUT transmit signal
  • pre-tap, primary and post-tap data values used to gen ⁇ rat ⁇ th ⁇ TX OUT signal i.e., from transmit shift register 124 and post-tap data shift regist ⁇ r 120
  • th ⁇ tap s ⁇ l ⁇ ct logic 139 may s ⁇ lect, as tap values for the r ⁇ c ⁇ iv ⁇ r ⁇ qualization circuit, any combination of the r ⁇ ceiv ⁇ d data valu ⁇ s stor ⁇ d within buff ⁇ r 132, and th ⁇ pr ⁇ - tap, post-tap and primary data valu ⁇ s us ⁇ d to g ⁇ nerate th ⁇ TX OUT signal.
  • tap sel ⁇ ct logic 139 outputs a control signal to th ⁇ tap s ⁇ l ⁇ ctor 137 to control tap data source selection according system configuration information.
  • the pre-tap, post-tap and/or primary data values may b ⁇ s ⁇ l ⁇ ct ⁇ d with the polarity necessary to achiev ⁇ a subtractiv ⁇ effect on th ⁇ corresponding cross-talk interf ⁇ r ⁇ nc ⁇ (the appropriate polarity being establish ⁇ d or controlled within the buffer 132 or receiver equalizing circuit), thereby enabling reduction of near- ⁇ nd cross-talk int ⁇ rference.
  • the tap select circuit 137 is shown in Figure 7, any numb ⁇ r of tap select circuits may be used.
  • FIG. 8 illustrates a transceiver device 151 that may be coupled to either or both sides of signaling path 122, and that includ ⁇ s both an ⁇ qualizing transmitt ⁇ r 115 and an ⁇ qualizing receiv ⁇ r 116 according to embodiments described herein (transmitters and r ⁇ ceiv ⁇ rs according to th ⁇ cross-talk canceling embodim ⁇ nts d ⁇ scribed in reference to
  • Th ⁇ transc ⁇ iv ⁇ r d ⁇ vic ⁇ 151 additionally includ ⁇ s an application logic circuit 154 to provide transmit data to the ⁇ qualizing transmitter 115 and to rec ⁇ iv ⁇ sampl ⁇ d data from the equalizing rec ⁇ iv ⁇ r 116.
  • Th ⁇ application logic circuit 154 also outputs an ⁇ nabl ⁇ signal
  • the transceiv ⁇ r 155 includes a transmit shift regist ⁇ r 124, output driv ⁇ r 121, post-tap data shift r ⁇ gist ⁇ r 120 and output driv ⁇ r bank 131 (which may include output drivers sourced by pre- tap data valu ⁇ s, cross-talk cancellation values, or by tap data source sel ⁇ ctors as d ⁇ scrib ⁇ d in reference to. Figure 6), all of which operat ⁇ g ⁇ nerally as described in reference to Figure 3 to output, during a giv ⁇ n transmit interval, a primary signal and corresponding equalization signal onto signal path 122.
  • the transceiv ⁇ r also includes a sampling circuit 123, buffer circuit 132, tap selector 156 and tap select logic 157.
  • the sampling circuit 123 samples data signals transmitted on signal path 122 (i.e., by a remote transmitter or transceiver) and stores the corresponding data values in buffer circuit 132.
  • the tap selector 156 is coupled to the buffer circuit 132 as well as the transmit shift regist ⁇ r (including th ⁇ h ⁇ ad of th ⁇ transmit shift register which contains the primary data value) and the post-tap data shift regist ⁇ r 120, and th ⁇ refore enables any combination of received data values (i. ⁇ ., from buff ⁇ r 132) and pre-tap, primary and/or post-tap transmit data values to be. selected as source data taps within an equalizing circuit (i.e., output driver 140 or an equalizing circuit within the sampling circuit 123).
  • the tap sel ⁇ ct logic 157 outputs a control signal to the tap s ⁇ lector according syst ⁇ m configuration information
  • the tap s ⁇ l ⁇ ct logic 157 and tap s ⁇ lector 156 operate to sel ⁇ ct tap valu ⁇ s from the transmit shift register 124, data tap shift regist ⁇ r 120, and/or buff ⁇ r circuit 132 in any combination. Th ⁇ selected tap values are then used to source equaliz ⁇ r taps within an equalizing output driver 140 or an equalizing circuit within sampling circuit 123.
  • the transceiver embodim ⁇ nts d ⁇ scrib ⁇ d in reference to Figures 8 and 9 include an enabl ⁇ lin ⁇ to alternat ⁇ ly enable transmission or reception of signals
  • the enable line may be omitted and transmission and reception of signals may occur simultaneously (i. ⁇ ., simultan ⁇ ous bi-dir ⁇ ctional signaling).
  • multilevel signaling may be used to enable an outgoing signal to b ⁇ transmitt ⁇ d simultaneously (in ⁇ ff ⁇ ct, superimposed on) an incoming signal.
  • th ⁇ receive circuit may subtract the locally transmitted signal from an incoming signal to recover only the desired portion (i.e., r ⁇ mot ⁇ ly transmitted portion) of the incoming signal.
  • the locally transmitt ⁇ d signal may produce dispersion- and reflection-type ISI that may b ⁇ compensated by an equalizing rec ⁇ iv ⁇ r having, as an ⁇ xample, the configuration of Figure 9, but omitting the enabl ⁇ line.
  • th ⁇ transmit shift register 124 and post- tap data register 120 may be sel ⁇ ct ⁇ d by tap s ⁇ lect circuit 156 to source tap data values for equalization of low- and/or high-lat ⁇ ncy distortions resulting from th ⁇ local signal transmission (i. ⁇ ., by output driver 121).
  • the post-tap data register may need to be extended (i.e., have an increased number of entri ⁇ s) to ⁇ nable reduction of high-latency distortions resulting from the local signal transmission.
  • the rec ⁇ iv ⁇ circuit tap s ⁇ l ⁇ ctions, controlled by tap s ⁇ lect logic 157, may b ⁇ determin ⁇ d ⁇ mpirically or during run-tim ⁇ , for ⁇ xampl ⁇ , by using th ⁇ m ⁇ thods and circuits described below for determining equalization tap latencies, weights and polarities.
  • Figure 10 illustrat ⁇ s an ⁇ x ⁇ mplary buffer 159 that may be used within the receiver 116 of Figure 3 and that includes both a serial shift register 161 as w ⁇ ll as a numb ⁇ r (K) of parall ⁇ l-load r ⁇ gist ⁇ rs 165rl65 ⁇ .
  • a serial shift register 161 as w ⁇ ll as a numb ⁇ r (K) of parall ⁇ l-load r ⁇ gist ⁇ rs 165rl65 ⁇ .
  • a newly sampl ⁇ d data value 160 is loaded from sampling circuit 123 into the shift register 161.
  • the shift register is formed by N storage elements (depicted as flip-flops 163]-163H, though latches or other types of storage el ⁇ m ⁇ nts may b ⁇ us ⁇ d) coupl ⁇ d in daisy chain fashion such that, as th ⁇ n ⁇ wly sampl ⁇ d value 160 is loaded into the first storag ⁇ ⁇ l ⁇ ment 163 ! in the shift register 161, the contents of each storage element 163 except the last (163N) is shifted to th ⁇ n ⁇ xt storag ⁇ elem ⁇ nt in th ⁇ chain in response to a receive clock signal (RCLK).
  • N storage elements depicted as flip-flops 163]-163H, though latches or other types of storage el ⁇ m ⁇ nts may b ⁇ us ⁇ d
  • the symbol latency of the input value 160 is i-1
  • the symbol latencies of the outputs of the remaining storage elem ⁇ nts 163 in the shift regist ⁇ r 161 are, from left to right, i+1, i+2, ..., and i+(N-l), r ⁇ sp ⁇ ctiv ⁇ ly.
  • a shift counter 169 (which may be included within or separat ⁇ from buffer circuit 159) maintains a count of the number of data values shifted into the shift register 161, incrementing the shift count in response to each transition of RCLK.
  • the shift counter 169 asserts a load signal 164 (LD) upon reaching a count that corresponds to a full shift regist ⁇ r, then rolls the shift count back to a starting valu ⁇ .
  • the load signal 164 is routed to strobe inputs of storag ⁇ el ⁇ m ⁇ nts within th ⁇ parallel-load registers 165, enabling parall ⁇ l load register 165 ! to be loaded with the contents of the shift register, and enabling each of the parallel-load regist ⁇ rs 165 2 -165 to b ⁇ load ⁇ d with the content of a preceding one of the parallel load regist ⁇ rs (i.e.,
  • the symbol latency of a data value stored within any of th ⁇ parall ⁇ l-load r ⁇ gist ⁇ rs 165 is d ⁇ p ⁇ nd ⁇ nt on how many data valu ⁇ s hav ⁇ been shifted into the shift register since the last assertion of the load signal 164; a measure indicated by the shift count.
  • the shift count is 1, indicating that the load signal 164 was asserted at the immediately preceding edge of RCLK
  • the content of storage el ⁇ m ⁇ nt 167i of parall ⁇ l- load register 165i has a symbol latency of i+1 (i. ⁇ ., on ⁇ symbol tim ⁇ old ⁇ r than th ⁇ content of storage ⁇ lement 163 ⁇ of the shift regist ⁇ r).
  • Wh ⁇ n the next valu ⁇ is shifted into th ⁇ s ⁇ rial shift register 161, th ⁇ contents of the parallel r ⁇ gist ⁇ rs 165 remain unchanged, meaning that th ⁇ latency of each data value stored in th ⁇ parall ⁇ l registers 165 is increased by a symbol time.
  • the content latency (i.e., lat ⁇ ncy of a stor ⁇ d valu ⁇ ) of a given storag ⁇ ⁇ l ⁇ m ⁇ nt within on ⁇ of parall ⁇ l regist ⁇ rs 165 is d ⁇ pendent upon the value of the shift count. Ref ⁇ rring to parall ⁇ l load r ⁇ gist ⁇ r 165 l5 for example, the content latency of storag ⁇ ⁇ l ⁇ ment 167 !
  • the content lat ⁇ ncy of storag ⁇ ⁇ l ⁇ ment 167 2 is i+SC+1, and so forth to storage el ⁇ m ⁇ nt 167 N , which has a content latency of i+(N-l)+SC.
  • the content latencies of storage el ⁇ m ⁇ nts within the parallel-load registers 165 2 -165 ⁇ are similarly dependent upon the shift clock value, SC, but are increased by N for each parall ⁇ l load away from register 165 ⁇ .
  • the content latency of th ⁇ leftmost storage el ⁇ m ⁇ nt within r ⁇ gist ⁇ r 165 2 is i+N+SC
  • the content latency of the leftmost storage el ⁇ m ⁇ nt within register 165 ⁇ is i+(K-l)N + SC.
  • the content latencies of the storage el ⁇ m ⁇ nts within registers 165 -165 ⁇ are incrementally relat ⁇ d to th ⁇ content latency of th ⁇ corresponding leftmost storag ⁇ ⁇ l ⁇ m ⁇ nt in th ⁇ sam ⁇ manner that the content latencies of storage el ⁇ ments 167 2 -167 N relate to the content latency of storage el ⁇ m ⁇ nt 167].
  • the desired data value is located at a shift- count-depend ⁇ nt bit position within one of the parallel-load regist ⁇ rs 165.
  • N the desired data valu ⁇ is locat ⁇ d within register 165] at bit position X-SC, as indicated at 181.
  • the symbol latency of storage el ⁇ ment 167 N is increased, and the storage el ⁇ m ⁇ nt one position to the left of storage element 167 N (i. ⁇ ., 167N- I ) now contains th ⁇ data valu ⁇ having the desired symbol latency and is therefore selected to supply the data value to an equalizer tap.
  • th ⁇ n X is compared with 2N+SC at 183. If X is less than 2N+SC, then parallel-load regist ⁇ r 165 2 contains the desired tap value at bit position X-N-SC as indicated at 185. The decision flow continues in this manner to 187 at which point X is compared with (K-1)N+SC. If X is l ⁇ ss than (K-1)N+SC, th ⁇ n parall ⁇ l-load r ⁇ gist ⁇ r 165 . ! contains the desired tap value at position X-(K-1)N - SC as indicated at 189.
  • Figure 12 illustrates an exemplary embodim ⁇ nt of a tap select circuit for sel ⁇ cting a tap valu ⁇ (DATA, + ⁇ ) from a buff ⁇ r circuit 210 that includes an eight-bit serial shift regist ⁇ r 161 and two ⁇ ight bit parall ⁇ l-load registers 165 ls
  • the data value in th ⁇ first (leftmost) storage el ⁇ m ⁇ nt within the shift register 161 has a symbol latency of one and that the dead range is four symbol times (i.e., the leftmost four storage el ⁇ m ⁇ nts within th ⁇ shift register 161 are not used to source tap values to the equalizer).
  • the data values stored in parallel-load register 165 ! will have symbol latencies ranging from 2-9 symbol tim ⁇ s, and th ⁇ data valu ⁇ s stor ⁇ d in parall ⁇ l-load r ⁇ gist ⁇ r 165 2 will hav ⁇ symbol lat ⁇ ncies ranging from 10-17 symbol times.
  • refactions (or other distortions) appearing at the receiver input betw ⁇ en 5 and 17 symbol times after the corresponding primary signal may be reduced by sel ⁇ cting data values having corresponding symbol latencies from the buffer circuit 210 to drive the rec ⁇ iv ⁇ -sid ⁇ ⁇ qualiz ⁇ r taps (i.e., to be tap data values).
  • Multiplexers 205, 207j and 207 2 are responsiv ⁇ to low order bits of a latency value 200 (X[4:0]) to select tap positions within the shift register 161, parallel-load regist ⁇ r 165 l5 and parallel-load r ⁇ gist ⁇ r 165 2 .
  • Th ⁇ lat ⁇ ncy valu ⁇ 200 is additionally suppli ⁇ d to a s ⁇ lect logic circuit 201 which generates a register select signal, SEL[1:0], to sel ⁇ ct one of th ⁇ thr ⁇ r ⁇ gist ⁇ rs 161, 165 ⁇ and 165 2 within th ⁇ buff ⁇ r circuit 210 to source the tap data value, DATAj+ ⁇ .
  • Th ⁇ least significant two bits of the latency value 200 are input to multiplex ⁇ r 205 to s ⁇ lect on ⁇ of th ⁇ four s ⁇ l ⁇ ctabl ⁇ data values within the serial shift regist ⁇ r 161.
  • Th ⁇ l ⁇ ast three significant bits of the latency value 200 are input to a subtract circuit 203 which subtracts the shift count 202 from the thre ⁇ -bit lat ⁇ ncy valu ⁇ to produce a tap select value for the parallel-load regist ⁇ rs 165 1? 165 .
  • th ⁇ s ⁇ lect value 200 corresponds to a desired symbol latency as shown in Table 1 below, and the shift count 202 is encoded in a three-bit value, SC[2:0], as shown in Table 2 below.
  • SC[2:0] 000
  • th ⁇ l ⁇ ftmost bit positions within r ⁇ gist ⁇ rs 165 hav ⁇ symbol lat ⁇ nci ⁇ s 9 and 17 wh ⁇ n th ⁇ shift count is eight.
  • Figure 13 illustrates an exemplary embodim ⁇ nt of th ⁇ s ⁇ l ⁇ ct logic 201 of Figur ⁇ 12.
  • the select logic 201 includes a comparator circuit 215 to compare the latency select value 200 with N (th ⁇ siz ⁇ , in bits, of each of registers within buffer circuit 210), a summing circuit 217 to sum the shift count 202 with N (ther ⁇ by gen ⁇ rating SC+N), and a comparator circuit 219 to compare the latency select value 202 with the output of the summing circuit 217.
  • the summing circuit and comparators may have numerous implementations depending on the size of N and the number of bits used to form the latency select value 200 and shift count 202.
  • the sum of the shift count and N may be formed simply by including an additional bit in parallel with the thre ⁇ shift count bits, the additional bit forming the most significant bit of the resulting sum (i.e., sum[3]) while SC[2:0] form the less significant thre ⁇ bits of th ⁇ sum (i. ⁇ ., sum[2:0]).
  • the comparator 215 may be impl ⁇ m ⁇ nt ⁇ d by a NOR gat ⁇ having inputs coupl ⁇ d to X[4] and X[3].
  • th ⁇ X ⁇ N output will be high only if both X[4] and X[3] are low.
  • Numerous other logic circuits may be used to implement the sel ⁇ ct logic circuit 201 of Figure 12 in Var ⁇ ⁇ mbodiments. More generally, specific numbers of bits and registers have be ⁇ n described for purpose of example only. Alternativ ⁇ embodiments may included ⁇ diff ⁇ r ⁇ nt numbers of regist ⁇ rs having various siz ⁇ s, and latency select values and shift count values having different sizes.
  • any circuit for sel ⁇ cting a data value based on a latency sel ⁇ ct value may alternatively be used without departing from the spirit and scope of the pres ⁇ nt inv ⁇ ntion.
  • Figure 14 illustrat ⁇ s a g ⁇ n ⁇ raliz ⁇ d sel ⁇ ct circuit 230 that may b ⁇ us ⁇ d to select Q tap values from the buff ⁇ r circuit 210 of Figur ⁇ 12.
  • Th ⁇ s ⁇ l ⁇ ct circuit 230 includes a switch matrix 231 and tap select logic 235.
  • each of the possibl ⁇ tap data sources within the buffer circuit 210 (i.e., the rightmost four bits within shift register 161 and all the bits within the parallel-load registers 165) are coupled to respective column lines 234 of the switch matrix 231, and each of the Q tap outputs are coupled to resp ⁇ ctiv ⁇ row lin ⁇ s 236 of th ⁇ switch matrix 231.
  • a switch clement 233 is provid ⁇ d at ⁇ ach row-column int ⁇ rs ⁇ ction to enable the tap data source for the column to be selectively coupled to the tap output for the row.
  • each enable signal includes Q component signals coupled respectively to the Q switch elements within a corresponding column.
  • the column 1 data value i.e., th ⁇ data value stored in shift regist ⁇ r position 4
  • sel ⁇ ct signal E 1 [Q:1] 100..00.
  • E j [i] l for each column data value, j, to be coupled to a tap output, i.
  • the Q tap outputs may b ⁇ s ⁇ l ⁇ ct ⁇ d from among th ⁇ complete range of data values stored within buffer circuit 210.
  • the sel ⁇ ct logic includes combinatorial logic that operates as d ⁇ scribed in ref ⁇ rence to Figure 10 to gen ⁇ rat ⁇ ⁇ ach ⁇ nabl ⁇ signal.
  • a stat ⁇ machine or other processing logic may be used to generate the enable signals in accordance with the latency selection values and shift count.
  • FIG. 15 illustrat ⁇ s an ⁇ mbodim ⁇ nt of a switch element 233 that may be used within th ⁇ switch matrix 231 of Figur ⁇ 14.
  • Th ⁇ switch ⁇ l ⁇ ment includes a transistor 235 having source and drain terminals coupled betwe ⁇ n th ⁇ i th row lin ⁇ 236; (TAP;) and th ⁇ j th column line 235 j (DATAj) of the switch matrix, and a gate t ⁇ rminal coupl ⁇ d to r ⁇ c ⁇ iv ⁇ the i th component signal of enabl ⁇ signal j (i. ⁇ ., E j [i]).
  • transistor 235 is switched on to couple the s ⁇ lected data source to the tap output.
  • Other types of switching el ⁇ ments may b ⁇ us ⁇ d in alt ⁇ rnati ve ⁇ mbodim ⁇ nts .
  • th ⁇ tap values selected by the tap sel ⁇ ct logic 139 and s ⁇ l ⁇ ct circuit 128 may be used in a number of different equalizing circuits to counteract distortion ev ⁇ nts.
  • an equalizing output driver 140 is coupled in parallel with the sampling circuit 123 to drive an equalizing signal back onto the signal path 122 during each symbol reception interval (i.e., symbol time during which a valid symbol is pres ⁇ nt at the input of the receiver).
  • symbol reception interval i.e., symbol time during which a valid symbol is pres ⁇ nt at the input of the receiver.
  • Figure 17 illustrat ⁇ s th ⁇ r ⁇ c ⁇ iv ⁇ circuit of Figure 16 in greater detail.
  • the sampling circuit 123 may include any number of preamplifiers 240 ! -240 N coupled in series with a sampler 241.
  • the sampler 241 may be any type of circuit for det ⁇ cting th ⁇ level of an input signal, including but not limited to a latching circuit that latches the signal level in response to a rising or falling clock edg ⁇ , or an integrating circuit that integrat ⁇ s the input signal over a finite period of time (e.g., a symbol time or portion of a symbol time).
  • Th ⁇ ⁇ qualizing output driv ⁇ r 140 may b ⁇ coupled to the signal path 122 (i.e., the input of the first pr ⁇ amplifi ⁇ r 240 ⁇ ) or, alternatively, to the output of any of the preamplifi ⁇ rs 240. Also, as discussed below, the output driv ⁇ r 140 may be coupl ⁇ d to the sampler 241 to affect the sampling operation. In one embodim ⁇ nt, th ⁇ ⁇ qualizing output driv ⁇ r 140 of Figures 15 and
  • EQCLK equalizer clock signal
  • the equaliz ⁇ r clock signal may b ⁇ furth ⁇ r offs ⁇ t from th ⁇ r ⁇ c ⁇ iv ⁇ clock signal as shown by arrow 245 to account for the time required for the ⁇ qualization data (i. ⁇ ., selected tap values) to propagat ⁇ through the equalizing output driver 140 or other equalizing circuit.
  • Figure 19 illustrates a current-sinking output driver 250 that may be us ⁇ d to impl ⁇ m ⁇ nt th ⁇ equalizing output driver 140 of Figure 16.
  • the output driver includes a plurality of sub-driver circuits 251 ⁇ 251 ⁇ each sub-driver circuit 251 including a current source 257, clocking transistor 255 and data tap transistor 253 coupled in seri ⁇ s between an output node 254 and a ref ⁇ r ⁇ nc ⁇ voltage (ground in this exampl ⁇ ).
  • Control terminals (e.g., gate terminals) of the data tap transistors 253 of the sub-driver circuits 251 ar ⁇ coupl ⁇ d to r ⁇ c ⁇ ive resp ⁇ ctive data tap values (designat ⁇ d EQD ⁇ -EQDN in Figure 19) from a sel ⁇ ct circuit, control terminals of the current sources 257 are coupled to resp ⁇ ctiv ⁇ tap w ⁇ ight valu ⁇ s, EQW P EQW N , and control terminals of the clocking transistors are coupled in common to r ⁇ c ⁇ ive th ⁇ ⁇ qualiz ⁇ r clock signal, EQCLK.
  • th ⁇ tap w ⁇ ights provid ⁇ d to th ⁇ output driv ⁇ r 250 or oth ⁇ r ⁇ qualizing circuits described herein may be pr ⁇ d ⁇ t ⁇ rmin ⁇ d valu ⁇ s, or may be determin ⁇ d dynamically according to th ⁇ l ⁇ v ⁇ l of the distortions to be reduced. Because the sub-driver circuits 251 are coupled in parallel to the output node, the overall equalization signal gen ⁇ rat ⁇ d by output driver 250 during a given symbol time is the sum of contributions from the individual sub-driver circuits 251.
  • output driver 250 outputs an equalization signal only when the equalizer clock signal is high (i.e., ev ⁇ n phas ⁇ s of EQCLK).
  • An additional instance of output driver 250 may be provided to output an equalization signal when a complem ⁇ nt ⁇ qualiz ⁇ r clock signal (i.e., /EQLCK) is high.
  • Figure 20 illustrat ⁇ s an embodiment of a push-pull type of sub-driver circuit 260 that may be used within an ⁇ qualizing output driver inst ⁇ ad of th ⁇ pull-down sub-driv ⁇ r circuits 251 described in ref ⁇ r ⁇ nc ⁇ to Figure 19.
  • current is eith ⁇ r sourc ⁇ d or sunk via the driver output according to the state of the tap data value, EQDi.
  • Th ⁇ sub- driv ⁇ r circuit 260 includes switching transistors 263 and 265, and AND gate 261.
  • a first input of the AND gate 261 is coupled to receiv ⁇ the tap data value, EQDj, and a s ⁇ cond input of th ⁇ AND gat ⁇ 261 is coupl ⁇ d to a clock line to receiv ⁇ th ⁇ ⁇ qualiz ⁇ r clock signal, EQCLK.
  • Th ⁇ output of th ⁇ AND gat ⁇ 261 is coupled to the gate terminals of transistors 263 and 265 such that, during each high phase of the equalizer clock signal, th ⁇ tap data valu ⁇ is pass ⁇ d to th ⁇ gat ⁇ t ⁇ rminals of transistors 263 and 265 to ⁇ stablish th ⁇ output stat ⁇ of th ⁇ sub-driv ⁇ r circuit 260.
  • ⁇ v ⁇ ry other half cycle of the equalizer clock signal constitutes an output enable interval for the sub-driver circuit 260. If the tap data value, EQDj, is high during a given output enable interval, transistor 265 is switched on, causing th ⁇ sub-driv ⁇ r circuit 260 to sink current via the output nod ⁇ (OUTj). Conversely, if the tap data value is low during the output enable interval, transistor 263 is switched on to source current via the output nod ⁇ .
  • a pull-down biasing circuit ( ⁇ .g., current source) may be coupled between the pull-down data tap transistor 265 and ground, and a pull-up biasing circuit may be coupled betw ⁇ n the pull-up data tap transistor 263 and the supply reference voltage (e.g., V DD ) to enable weighted control of the current sourcing and sinking strength of the push-pull sub-driv ⁇ r circuit 260.
  • V DD supply reference voltage
  • an additional instance of the sub-driver circuit 260 may be provided with a complement equalizer clock signal (/EQCLK) and complem ⁇ nt tap data valu ⁇ (/EQDj) being input to AND gate 261 to ⁇ nable the sub-driver circuit 260 to output an equalizing signal during the alternat ⁇ half cycle of the equalizer clock signal.
  • Figure 21 illustrates another embodim ⁇ nt of a sub-driver circuit 275 that may be used within an equalizing output driver.
  • the sub-driver circuit 275 includes a differential transistor pair 277 having control terminals coupled to outputs of AND gates 261 ⁇ and 261 2 , respectively.
  • a tap data value (EQDi) and an equaliz ⁇ r clock signal (EQCLK) are input to AND gate 261 ⁇
  • a complem ⁇ nt of th ⁇ tap data valu ⁇ (/EQDj) and th ⁇ equalizer clock signal are input to AND gate 261 2 -
  • the tap data value and complement tap data value are applied to respective inputs of the differential pair 277 during ev ⁇ ry other half cycle of the equalizer clock signal.
  • Output nodes of the differential pair 277 are pulled up through resp ⁇ ctiv ⁇ r ⁇ sistiv ⁇ loads 283 (R), and source terminals of the differential pair are coupled to ground via a current source 281.
  • the resistiv ⁇ loads 283 may b ⁇ , for example, termination el ⁇ ments coupled to th ⁇ signal path (not shown) rather than resistive ⁇ l ⁇ ments included within the sub-driver circuit 275. Accordingly, the sub-driver circuit 275 is enabled, during ev ⁇ ry other half cycle of the equalizer clock signal, to output a differential ⁇ qualizing signal on output nod ⁇ s OUT,- and /OUT; in accordance with the complem ⁇ ntary tap data valu ⁇ s, EQDj and /EQDi.
  • a counterpart instance of sub-driver circuit 275 may be provided to generat ⁇ a diff ⁇ rential equalizing signal during the alternate half clock cycle of the equaliz ⁇ r clock signal.
  • the current source 281 is controlled by the tap weight value, EQW,-, in the manner described in reference to Figure 19, though different weighting schemes may be used in alternative embodim ⁇ nts (e.g., using weight-bias ⁇ d pull-up ⁇ l ⁇ m ⁇ nts in place of resistive el ⁇ m ⁇ nts 283).
  • Figure 22 illustrates an Var ⁇ typ ⁇ of ⁇ qualizing circuit 290 that may b ⁇ us ⁇ d in ⁇ mbodim ⁇ nts of th ⁇ inv ⁇ ntion.
  • ⁇ qualization is p ⁇ rform ⁇ d in conjunction with preamphfication of th ⁇ incoming signal, and therefore affects the level of preamphfication applied to th ⁇ incoming signal. That is, th ⁇ ⁇ qualizing circuit
  • Equalizing circuit 290 includes a differential amplifier 294 formed by differential transistor pair 291, biasing current source 292 and resistive loads
  • output lines P O U T and /P OUT are coupled to input terminals of a differential amplifier within a sampling circuit so that amplifier 294 eff ⁇ ctively forms a first stage in a two-stage amplifier (i.e., amplifier 294 is a preamplifier).
  • Equalizing circuit 290 additionally includes a level shifting circuit 296 coupled to the differ ⁇ ntial amplifier 294 to provide preamplifi ⁇ r equalization.
  • the lev ⁇ l shifting circuit 296 includes a pair of sub-circuits 298 1 and 298 2 ⁇ ach coupled betw ⁇ en a respective one of the diff ⁇ rential amplifier outputs
  • 298 includes a respective plurality of data tap transistors (295 ! -295N and 297 ! -
  • each of the data tap transistors 295 is sized (e.g., by width-length ratio) to achieve a respective tap weight EQ N -EQWi.
  • each data tap value may be coupled to the control terminal of a sel ⁇ ct ⁇ d on ⁇ of th ⁇ data tap transistors 295 according to the desir ⁇ d tap w ⁇ ight.
  • Th ⁇ transistors 297 are similarly weighted and therefore allow coupling of the complem ⁇ nt data tap valu ⁇ s according to desired tap weights.
  • the weights of the individual data tap transistors 295 (and 297) may b ⁇ incr ⁇ m ⁇ ntally r ⁇ lat ⁇ d (i.e., EQW !
  • the clocking transistor 299 is switched on during every other half cycle of th ⁇ equalizer clock signal to enable the operation of the subcircuits 298.
  • the subcircuits 298 operate to increas ⁇ or d ⁇ crease the difference between the pr ⁇ amplifi ⁇ d output signals (or ⁇ v ⁇ n change the polarity of th ⁇ diff ⁇ rence) by drawing more current from one of the preamplifier output lines (P OUT or /P OUT ) than the other in accordance with the sel ⁇ ct ⁇ d data tap valu ⁇ s.
  • the subcircuits 298 act to differentially shift the level of the preamplified output signal generated by differential amplifier 294.
  • An additional instance of the equalizing circuit 290 may be provided to enable preamplifier equalization during th ⁇ alternate half cycl ⁇ of th ⁇ ⁇ qualiz ⁇ r clock signal.
  • Figure 23 illustrates an alternative lev ⁇ l shifting circuit 305 that may be substituted for circuit 296 of Figure 22.
  • circuit 305 differential pairs of data tap transistors 307 307 N are coupled to output lines POUT and /POUT in the same manner as in circuit 296, but instead of sizing the data tap transistors to achieve tap weighting, tap weighted current sources 311 ! -3 H N are coupled in series with the diff ⁇ r ntial pairs of data tap transistors 307 ! -307 N , respectively.
  • current source 31 ⁇ is controlled by (i.e., draws a bias current according to) weight value EQWi and is coupl ⁇ d via clocking transistors 309 ! to data tap transistors 307].
  • weight values EQW J -EQWN may be configured (e.g., via run-time calibration or production time programming) as necessary to establish a desir ⁇ d equalizing signal contribution from each differ ⁇ ntial pair of data tap valu ⁇ s 307.
  • An additional instance of th ⁇ equalizing circuit 290 may be provided to enable preamplifier equalization during the alternate half cycl ⁇ of th ⁇ ⁇ qualiz ⁇ r clock signal (i.e., by driving clocking transistors 309 with complement equalizing clock, /EQCLK).
  • Figure 24 illustrates anoth ⁇ r typ ⁇ of ⁇ qualizing circuit 320 that may be used in embodiments of the inv ⁇ ntion.
  • a l ⁇ vel shifting circuit 330 is coupled to low impedance inputs of a differ ⁇ ntial sampling circuit 328, and is us ⁇ d to affect the lev ⁇ l of th ⁇ input signal b ⁇ for ⁇ the sampled signal is captured.
  • the sampling circuit includes differential transistor pair 329 to precharg ⁇ input nodes S ⁇ N and /S ⁇ N according to th ⁇ state of a differential input (e.g., the output of a preamplifier 294 of Figure 22, or a differential data signal), during a first half cycle of the receive clock (which enabl ⁇ s clocking transistor 331).
  • a differential input e.g., the output of a preamplifier 294 of Figure 22, or a differential data signal
  • transistors 321 and 325 ar ⁇ switched on by the low-going rec ⁇ iv ⁇ clock signal, thereby enabling a cross-coupled latch formed by transistors 322, 323, 325 and 326 to latch the state of the precharg ⁇ d signal l ⁇ v ⁇ ls on nod ⁇ s S ⁇ N and /S ⁇ N -
  • the l ⁇ v ⁇ l shifting circuit 330 is similar to th ⁇ circuit 296 of Figur ⁇ 22 ⁇ xc ⁇ pt that clocking transistor 341 is ⁇ nabl ⁇ d by th ⁇ receive clock signal
  • RCLK equalizer clock signal
  • the equalizer clock signal being used to switch on switching transistors 335 ! -335 N and 339 1 -339 N during every other half cycle.
  • Data tap transistors 333 ! -333 N which are controlled by respective tap data values EQD ⁇ EQD N , are coupled in s ⁇ ries with the switching transistors 335]-335 N , resp ⁇ ctiv ⁇ ly.
  • data tap transistors 337 ! -337 N ar ⁇ coupl ⁇ d in s ⁇ ries with switching transistors 339 ! -339 N and are controlled by respective complem ⁇ nt tap data valu ⁇ s /EQD !
  • th ⁇ data tap transistors 333, 337 and switching transistors 335, 339 are sized to provide different current draws according to pred ⁇ t ⁇ rmin ⁇ d weights, EQW1-EQWN, thereby permitting different data taps to make different level-shifting contributions, hi one embodim ⁇ nt, for ⁇ xampl ⁇ , the switching transistors 335 and 339 are binary weighted such that, when switched on, the current draw through transistor pair 333 N /335 is 2 N-1 times the current through transistor pair 333 1 /335 1 (and the current draw through transistor pair 337 N /339 N is 2 _1 times the current through transistor pair 337 ⁇ 339 ! .
  • Other weighting schemes may also be used including, without limitation, thermom ⁇ t ⁇ r coding of high-gain transistor pairs, linear weighting schemes, or any combination of exponential (e.g., binary), linear and fhermomet ⁇ r coded weightings.
  • the ⁇ qualiz ⁇ r clock is phas ⁇ advanced relative to the receive clock signal such that transistors 337 and 339 are switched on in advance of clocking transistor 341.
  • transistors 333 and 337 ar ⁇ poised to shift the lev ⁇ l of th ⁇ sampling circuit input nodes, S I N and
  • sampling circuit input nodes S I N and /S ⁇ N are diff ⁇ rentially discharged according to the tap data values EQD ⁇ -EQD N , /EQD ! -/EQDN and the resp ⁇ ctive weights of transistors 333 and 337.
  • Cons ⁇ qu ⁇ ntly, th ⁇ signal l ⁇ v ⁇ ls at th ⁇ input nod ⁇ s, SIN and /S I N, of sampling circuit 328 ar ⁇ differentially shifted by the lev ⁇ l shifting circuit 330 to reduce static offsets in the incoming data signal (applied to control terminals of differential pair 329) caused by reflections or other distortions.
  • Figure 25 illustrates an Var ⁇ lev ⁇ l shifting circuit 342 that may b ⁇ substitut ⁇ d for circuit 330 of Figur ⁇ 24.
  • the level shifting circuit 342 includes data tap transistors 333, 33 and equaliz ⁇ r-clock- ⁇ nabl ⁇ d switching transistors 335, 339 coupl ⁇ d as described in reference to Figure 24. However, rather than being coupl ⁇ d to a clocking transistor 335, th ⁇ source terminals of transistors 335 I -335 N are coupled to ground via capacitive ⁇ lements 334r 334 N , respectively, and the source terminals of transistors 339 !
  • the data tap transistors 333, 337 and switching transistors 335, 339 have uniform sizes (i. ⁇ ., uniform weighting), and the capacitive elements 334, 338 have weighted capacitive values to permit a broad range of capacitances to be coupled to th ⁇ input nod ⁇ s of sampling circuit 328.
  • the capacitive el ⁇ ments 334 are implem ⁇ nt ⁇ d by source-to-drain coupled transistors and are binary w ⁇ ight ⁇ d
  • capacitive elem ⁇ nt 335 has twice the capacitance of capacitive el ⁇ m ⁇ nt 335 ⁇ , and capacitive elem ⁇ nt 335 N has 2 N"1 tim ⁇ s th ⁇ capacitance of capacitive ⁇ l ⁇ ment 335i.
  • Other weighting relationships e.g., thermom ⁇ t ⁇ r coding, linear, uniform, etc.
  • the data tap transistors 333, 337 and/or switching transistors 335, 339 may be weighted in Var ⁇ ⁇ mbodiments instead of
  • an incoming data signal may include two symbols per receiv ⁇ clock cycl ⁇ (sometimes referred to as a "double data rat ⁇ " signal), and ⁇ ach symbol may hav ⁇ more than two possibl ⁇ stat ⁇ s (i. ⁇ ., may have a signal lev ⁇ l falling within mor ⁇ than two distinct ranges of signals).
  • the receiv ⁇ clock frequency may be so high that by the time a sampled data value is loaded into th ⁇ buff ⁇ r circuit 132, the data value already has a latency of several symbol times. All thes ⁇ factors present challeng ⁇ s to th ⁇ buff ⁇ ring and s ⁇ l ⁇ ction of tap valu ⁇ s d ⁇ scrib ⁇ d in reference to Figure 3.
  • Figure 26 illustrat ⁇ s an equalizing rec ⁇ iver 350 according to an .embodiment of the inv ⁇ ntion.
  • Th ⁇ r ⁇ c ⁇ iv ⁇ r 350 includes a double data rate sampling circuit 351, shift regist ⁇ r 353, s ⁇ l ⁇ ct circuit 355 and equalizing output driv ⁇ r 357.
  • Th ⁇ sampling circuit 351 includes a pair of sub-circuits 36l! and 361 2 to sample the incoming data signal in response to rising edges in the receiv ⁇ clock (RCLK) and complement receive clock (/RCLK), resp ⁇ ctively. Falling clock edges may alternatively be us ⁇ d to tim ⁇ th ⁇ sampling instant.
  • sampling circuit 351 outputs ⁇ v ⁇ n phas ⁇ data (EVEN IN) and odd phas ⁇ data (ODD IN) to the shift r ⁇ gist ⁇ r 353 via signal lin ⁇ s 362i and
  • th ⁇ d ⁇ ad rang ⁇ is assum ⁇ d to b ⁇ fiv ⁇ symbol lat ⁇ nci ⁇ s (oth ⁇ r d ⁇ ad rang ⁇ s may be used) such that data values D ⁇ +5 -
  • the sel ⁇ ct circuit 355 includes N tap selectors, 365 ! -365 N , that sel ⁇ ct from among th ⁇ plurality of data valu ⁇ s stored within the shift regist ⁇ r 353 and output a s ⁇ l ⁇ cted tap data value to a respective one of N output sub-drivers 369 ! -369 N within the equalizing output driv ⁇ r 357.
  • Each of th ⁇ output sub-driv ⁇ rs 369 in turn, driv ⁇ s a component ⁇ qualizing signal onto th ⁇ signal path 122.
  • th ⁇ ⁇ qualizing output driv ⁇ r 357 may b ⁇ replaced by an equalizing circuit that operates within a preamplifi ⁇ r circuit (not shown in Figur ⁇ 26) or sampling circuit 351 as described above in ref ⁇ rence to Figures 17-20.
  • Figure 27 illustrates the shift register 353 and one of the tap selectors 365 of Figure 26 according to more specific embodiments.
  • Th ⁇ shift r ⁇ gist ⁇ r includes a pair of shift sub-circuits 383] and 383 2 to store ev ⁇ n phas ⁇ data and odd phase data, respectively.
  • ⁇ ach of the shift sub- circuits 383 includes a numb ⁇ r of storag ⁇ ⁇ l ⁇ m ⁇ nts 381 (e.g., latches) coupled in a daisy chain configuration (i.e., output to input) to enabl ⁇ an input data valu ⁇ to b ⁇ shift ⁇ d progressively from a first (i.e., leftmost) storage el ⁇ m ⁇ nt 381 in th ⁇ chain to a last (rightmost) storage ⁇ l ⁇ ment 381 in the chain.
  • a numb ⁇ r of storag ⁇ ⁇ l ⁇ m ⁇ nts 381 e.g., latches
  • a daisy chain configuration i.e., output to input
  • Each of the shift sub-circuits 383 is responsive to the rec ⁇ iv ⁇ clock and compl ⁇ m ⁇ nt r ⁇ c ⁇ iv ⁇ clock signals such that the contents of each shift sub-circuit 383 is shifted during each half clock cycle of the receiv ⁇ clock signal.
  • each even phase data value stored in shift sub-circuit 383 ⁇ is designated by a prime (i.e., ') in Figur ⁇ 27 to indicate that the data value was load ⁇ d synchronously with th ⁇ loading of a newly received odd phase data value into shift sub-circuit 383 2 .
  • a prime i.e., '
  • two instances of each odd phas ⁇ data valu ⁇ ar ⁇ stored in the shift sub-circuit 383 2 with the second instance of the odd phase data value being designat ⁇ d by a prim ⁇ to indicate that the data valu ⁇ was load ⁇ d synchronously with th ⁇ loading of a newly received even phase data value into shift sub-circuit 383 ! .
  • the shift sub-circuits 383 collectively contain a sequence of data values, A', B, C, D, E' F, G', H, that may be us ⁇ d to generate odd phase equalizing signals (i.e., driving an equalizing signal onto th ⁇ signal path or aff ⁇ cting signal levels within a preamplifier or sampling circuit during odd phase symbol reception), and a sequ ⁇ nc ⁇ of data valu ⁇ s, B', C, D', E, F', G, H', I, that may be us ⁇ d to g ⁇ n ⁇ rat ⁇ ⁇ v ⁇ n phas ⁇ ⁇ qualizing signals.
  • th ⁇ outputs of each of the storage elements 381 within shift sub- circuit 383 ! are coupled to respective inputs of an even tap data select circuit 387 ! within the tap selector 365, and the outputs of each of the storage el ⁇ m ⁇ nts 381 within th ⁇ shift sub-circuit 383 2 are coupled to respective inputs of an odd tap data s ⁇ lect circuit 387 2 within the tap selector 365.
  • the even and odd tap data sel ⁇ ct circuits 387 are responsive to a select signal, S[2:0], to output sel ⁇ ct ⁇ d tap data values from the even and odd phases sequences of data values, resp ⁇ ctively.
  • Th ⁇ s ⁇ lect signal may be generated, for example, by tap the select logic 139 described in ref ⁇ r ⁇ nc ⁇ to Figur ⁇ 3.
  • the output of the ev ⁇ n tap data s ⁇ l ⁇ ct circuit is clocked into a flip-flop
  • flip-flop 387 2 is clocked into a flip-flop 391 2 (or other storage elem ⁇ nt) so that, at any giv ⁇ n tim ⁇ , the output of flip-flop 391 2 is delayed by two symbol times relativ ⁇ to th ⁇ most lat ⁇ nt data valu ⁇ suppli ⁇ d to th ⁇ odd tap data select circuit
  • the flip-flops 391 eff ⁇ ctiv ⁇ ly increas ⁇ the latency of selected even and odd data tap values by two symbol times.
  • S ⁇ l ⁇ ct circuits 393i and 393 2 ar ⁇ provided to ext ⁇ nd th ⁇ ov ⁇ rall lat ⁇ ncy rang ⁇ of th ⁇ even and odd data tap sel ⁇ ctions within tap s ⁇ lector 365 by allowing s ⁇ lection of tap data directly from the ev ⁇ n and odd data inputs to the shift regist ⁇ r 353 (i. ⁇ ., EVEN IN and ODD IN) or from the outputs of flip-flops 391.
  • Sel ⁇ ct bit S[3] is provided ( ⁇ .g., by the tap select logic 139 of Figure 3) to select between the fast path data (i.e., connections 384 ! and 384 2 to the inputs of the sub shift circuits 383) and the selected data values stored in flip-flops 391.
  • Flip-flops 395 ⁇ and 395 2 (or other storage elem ⁇ nts) ar ⁇ provid ⁇ d to synchroniz ⁇ th ⁇ outputs of multiplexers 393 ⁇ and 393 2 with the receiv ⁇ clock and complement receive clock, resp ⁇ ctiv ⁇ ly.
  • ⁇ ven and odd data tap values, ETD and OTD, each having a range of latencies according to the depth of the shift sub-circuits 383 and the number of fast path taps (of which signal lines 384 ! and 384 are ⁇ xamples) are output to the equalizing circuit (not shown in Figure 27) to enabl ⁇ even and odd phase equalization of an incoming signal.
  • Figur ⁇ 28 illustrates an equalizing receiver 405 for receiving a double data rate, multilevel input signal according to an embodiment of the invention.
  • the receiver 405 includes a sampling circuit 407, shift register 411, select circuit 421 and ⁇ qualizing output driv ⁇ r 427.
  • Th ⁇ sampling circuit includes ev ⁇ n and odd phas ⁇ sampling sub-circuits 409i and 409 2 to capture even and odd phase samples of the incoming multilevel data signal and to generate a multi-bit output indicative of the sampled signal lev ⁇ l.
  • the incoming data signal has one of four possible signal lev ⁇ ls, ⁇ ach l ⁇ vel being defined by a distinct range of voltages.
  • each sample is resolved (i.e., by sampling sub-circuits 409) to a thermom ⁇ ter code in which bits A, B, and C hav ⁇ valu ⁇ s according to which of four voltage ranges the sampled signal level falls within.
  • bits A,B and C are set according to the following relationships betw ⁇ en the sampled signal, Vs, and high, middle and low threshold voltage l ⁇ v ⁇ ls:
  • schem ⁇ s may be us ⁇ d in alternative embodiments.
  • more or fewer threshold l ⁇ vels (and th ⁇ r ⁇ fore signal ranges) may be used, and current levels may be used to indicate signal lev ⁇ l instead of voltage levels.
  • each of th ⁇ bits is input to a respective one of shift registers 413 A -413 C and used to source a tap value for s ⁇ lection by a respective set of select circuits 422 A ⁇ 422Q (each sel ⁇ ct circuit including N tap s ⁇ l ⁇ ct s ⁇ l ⁇ ctors 423 ! -423N).
  • Each of th ⁇ shift r ⁇ gist ⁇ rs 413 and select circuits 422 operates generally as described in reference to Figures 21 and 22 to g ⁇ n ⁇ rate a set of selected tap values, 424 A -424 C - Corresponding tap values from within each set 424 are provided to a respective one of output sub-drivers 429 ! -429N within ⁇ qualizing output driv ⁇ r 427, wh ⁇ re th ⁇ y ar ⁇ used to gen ⁇ rat ⁇ a multi-level equalization signal.
  • the tap valu ⁇ s output by tap s ⁇ lector 423 1 within each of the select circuits 422 are input to output sub-driver 429 j of the ⁇ qualizing output driv ⁇ r 427.
  • the equalization signal gen ⁇ rat ⁇ d by a r ⁇ ceive-sid ⁇ equalizing output driver to b ⁇ driv ⁇ n onto th ⁇ signal path in phas ⁇ alignment with data eyes in the incoming data signal.
  • rec ⁇ iv ⁇ clock (or compl ⁇ m ⁇ nt r ⁇ c ⁇ iv ⁇ clock) may b ⁇ us ⁇ d to clock th ⁇ ⁇ qualizing output driv ⁇ r (or preamp or sampling circuit equalizer)
  • propagation delay through the equalizing driver tends to become significant in high frequ ⁇ ncy systems, producing undesired timing offset betw ⁇ n th ⁇ incoming data signal and th ⁇ ⁇ qualization signal, hi on ⁇ ⁇ mbodim ⁇ nt
  • clock data recovery circuitry within an equalizing receiver is used to gen ⁇ rat ⁇ an ⁇ qualization clock signal (EQCLK) that is phas ⁇ advanced relative to the receive clock signal according to the propagation delay (i.e., clock-to-Q) of an equalizing output driver.
  • EQCLK ⁇ qualization clock signal
  • the equalizing output driver outputs an equalization signal having the desired phase relation with the incoming data signal.
  • a d ⁇ sired phase relationship b ⁇ tw ⁇ n th ⁇ incoming data signal (RX DATA) and ⁇ qualization signal (EQ DATA) is achieved.
  • the equalization data tap is assumed to have a symbol latency of five symbol times, such that an equalization signal bas ⁇ d on received symbol A is transmitted by the equalizing output driver during the reception interval for symbol F.
  • the receiver 450 includes a sampling circuit 451, shift register 453, clock-data-recov ⁇ ry (CDR) circuit 457, application logic 455, tap data sel ⁇ ctor 461, signal generator 462, equalizer clock gen ⁇ rator 459, and ⁇ qualization data source sel ⁇ ctor 463.
  • An incoming data signal (DATA) on signal path 122 is sampled by the sampling circuit 451 in response to a rec ⁇ ive clock signal (RCLK). The samples are output to the shift register 453 where they are stored for parallel output to the application logic 455 and the CDR circuit 457.
  • DATA incoming data signal
  • RCLK rec ⁇ ive clock signal
  • th ⁇ receive clock signal includes multiple component clock signals including a data clock signal and its complem ⁇ nt for capturing even and odd phase data samples, and an ⁇ dge clock signal and complem ⁇ nt edg ⁇ clock signal for capturing ⁇ dg ⁇ samples (i.e., transitions of the data signal between successive data eyes).
  • the data and edg ⁇ sampl ⁇ s are shifted into the shift regist ⁇ r 453 and then supplied as parallel words (i. ⁇ ., a data word and an ⁇ dg ⁇ word) to a phas ⁇ control circuit 467 within the CDR circuit 457.
  • the phas ⁇ control circuit 467 compares adjacent data sampl ⁇ s (i.e., successiv ⁇ ly receiv ⁇ d data samples) within the data word to determine when data signal transitions hav ⁇ taken place, then compares an interv ⁇ ning ⁇ dg ⁇ sampl ⁇ with the preceding data sample (or succ ⁇ ding data sampl ⁇ ) to det ⁇ rmin ⁇ wh ⁇ th ⁇ r th ⁇ ⁇ dg ⁇ sample matches th ⁇ preceding data sample or succeeding data sample. If the ⁇ dge sampl ⁇ matches the data sample that prec ⁇ d ⁇ d th ⁇ data signal transition, then the edge clock is de ⁇ m ⁇ d to be early relativ ⁇ to th ⁇ data signal transition.
  • the edge clock is deem ⁇ d to be lat ⁇ relativ ⁇ to th ⁇ data signal transition.
  • th ⁇ phas ⁇ control circuit 467 asserts an up signal (UP) or down signal (DN). If there is no early/lat ⁇ majority, neither the up signal nor the down signal is assert ⁇ d.
  • the mix logic circuit 471 receiv ⁇ s a set of phase vectors 472 (i.e., clock signals) from a reference loop circuit 470.
  • the phase vectors have incrementally offset phase angles within a cycle of a reference clock signal (REF CLK).
  • th ⁇ r ⁇ ference loop outputs a s ⁇ t of ⁇ ight phas ⁇ v ⁇ ctors that ar ⁇ offs ⁇ t from one another by 45 degrees (i.e., choosing an arbitrary one of the phase vectors to have a z ⁇ ro d ⁇ gre ⁇ angl ⁇ , the remaining s ⁇ v ⁇ n phase vectors have phase angles of 45, 90, 135, 180, 225, 270 and 315 degre ⁇ s).
  • the mix logic 471 maintains a phase count value which includes a v ⁇ ctor s ⁇ l ⁇ ct component to sel ⁇ ct a phas ⁇ -adjacent pair of the phase vectors (i.e., phase vectors that bound a phase angle equal to 360°/N, where N is the total number of phase vectors), and an interpolation component (TNT) which is output to a mixer circuit 473 along with the s ⁇ l ⁇ ct ⁇ d pair of phas ⁇ vectors (VI, V2).
  • the mix ⁇ r circuit mixes the selected pair of phase vectors according to the interpolation component of the phase count to gen ⁇ rat ⁇ complementary edg ⁇ clock signals and complem ⁇ ntary data clock signals that collectively constitute the receiv ⁇ clock signal.
  • Th ⁇ mix logic 471 increments and decrements the phase count value in response to assertion of the up and down signals, resp ⁇ ctiv ⁇ ly, th ⁇ reby shifting the interpolation of the sel ⁇ cted pair of phase vectors (or, if a phase vector boundary is crossed, sel ⁇ cting a n ⁇ w pair of phas ⁇ vectors) to increm ⁇ ntally retard or advance the phase of the rec ⁇ iv ⁇ clock signal.
  • the mix logic 471 increments the phase count, thereby incrementing th ⁇ interpolation component of the count and causing the mixer to incrementally increas ⁇ th ⁇ phase offs ⁇ t (retard the phas ⁇ ) of th ⁇ receive clock signal.
  • the phas ⁇ control signal output begins to dither between assertion of the up signal and the down signal, indicating that edg ⁇ clock components of the rec ⁇ iv ⁇ clock signal hav ⁇ b ⁇ come phase aligned with the edges in the incoming data signal.
  • the equaliz ⁇ r clock g ⁇ n ⁇ rator 459 receives the phase vectors 472 from the reference loop 470 and includes mix logic 481 and an equalizer clock mixer 483 that operate in the same manner as the mix logic 471 and receive clock mixer 473 within the CDR circuit 457. That is, the mix logic 481 maintains a phas ⁇ count valu ⁇ that is incrementally adjusted up or down in response to the up and down signals from the phase control circuit 467.
  • the mix logic selects a phase-adjac ⁇ nt pair of phase vectors 472 based on a vector select component of the phas ⁇ count, and outputs th ⁇ s ⁇ l ⁇ ct ⁇ d vectors (VI, V2) and interpolation component of the phas ⁇ count (INT) to the equalizer clock mixer 483.
  • the equaliz ⁇ r clock mix ⁇ r 483 mix ⁇ s th ⁇ s ⁇ l ⁇ ct ⁇ d v ⁇ ctors in accordance with the interpolation component of the phase count to generate the equalizer clock signal, EQCLK.
  • the equalizer clock signal which may include complem ⁇ ntary component clock signals, is output to the equalizing output driver 465 (or oth ⁇ r typ ⁇ of ⁇ qualization circuit as described above) to time the output of equalizing signals onto signal path 122.
  • the equalizer data source s ⁇ l ⁇ ctor 463 is r ⁇ sponsiv ⁇ to th ⁇ calibration signal 474 to s ⁇ lect either the tap selector 461 (which operates as described above to sel ⁇ ct data tap valu ⁇ s from the shift register 453 and/or one or mor ⁇ parall ⁇ l r ⁇ gist ⁇ rs) or the signal generator 462 that outputs clock pattern 10101010 (e.g., a bi-stable storage elem ⁇ nt that toggles betwe ⁇ n stat ⁇ s in response to each EQCLK transition).
  • the equalization data source s ⁇ lector 463 selects the tap selector 461 to supply select ⁇ d data valu ⁇ s to th ⁇ equalizing output driver 465.
  • the rec ⁇ iv ⁇ r 450 enters a calibration mode in which the signal generator 462 is sel ⁇ cted to supply the clock pattern to the equalizing output driver 465. Also, in calibration mod ⁇ , th ⁇ high stat ⁇ of the calibration signal 474 disables AND gates 468i and 468 2 from passing the up and down signals to the mix logic 471. Thus, the phase count within the CDR circuit remains unchanged in calibration mode, whil ⁇ up and down signals g ⁇ nerated by th ⁇ phase control circuit 467 are used to increment and decrement the phase count value within the mix logic 481.
  • phase control circuit 467 will assert an up or down- signal (as the case may b ⁇ ) to adjust the phase of the receive clock signal relative to the incoming data stream.
  • the receive clock phase is eff ⁇ ctively locked, however (i.e., by operation of the AND gates 468), only the phase count within the equalization clock generator will be adjusted.
  • the normal-mode CDR operation is ⁇ ff ⁇ ctively carried out in rev ⁇ rs ⁇ whil ⁇ th ⁇ receiver 450 is in calibration mode.
  • the phase of the equalizer clock signal is shifted to align transitions in the incoming data signal (i.e., the clock pattern output by th ⁇ ⁇ qualizing output driv ⁇ r) with th ⁇ r ⁇ c ⁇ ive clock signal.
  • the equalizer clock signal is advanced relative to an edge clock component of the receive clock signal by a time substantially equal to the clock-to-Q delay of th ⁇ ⁇ qualizing output driv ⁇ r 465.
  • th ⁇ overall effect of the calibration mode operation is to advance the phase of the equalization clock according to the clock-to-Q tim ⁇ of th ⁇ ⁇ qualizing output driv ⁇ r as shown in Figur ⁇ 30.
  • th ⁇ ⁇ qualizing output driver 465 drives an equalizing signal onto the signal path 122 in phase alignment with the incoming data signal.
  • the calibration signal 474 is assert ⁇ d for a time interval previously determined to be sufficient to achieve phase alignment between transitions in the transmitted clock pattern and the edg ⁇ clock compon ⁇ nt of th ⁇ r ⁇ c ⁇ iv ⁇ clock signal.
  • the up and down signals generated by the phase control circuit may b ⁇ monitored in the calibration mod ⁇ to d ⁇ termine wh ⁇ n th ⁇ up and down signals b ⁇ gin to alt rnat ⁇ , thereby indicating that the desired phase alignment has b ⁇ n obtain ⁇ d.
  • th ⁇ calibration signal is deasserted to enabl ⁇ normal op ⁇ ration of the receive circuit.
  • the CDR circuit returns to adjusting the phas ⁇ count within mix logic 471 in response to the up and down signals from the phase control circuit 467. Because the mix logic 481 within the equalizer clock gen ⁇ rator 459 continues to respond to the same up and down signals, the phase offset betwe ⁇ n th ⁇ ⁇ qualiz ⁇ r clock signal and th ⁇ r ⁇ c ⁇ iv ⁇ clock signal (i.e., th ⁇ phas ⁇ offs ⁇ t ⁇ stablish ⁇ d in th ⁇ calibration mod ⁇ ) is maintain ⁇ d as the phases of the two clocks are adjust ⁇ d.
  • th ⁇ equalizer. clock signal and receive clock signal retain the phase offset established in calibration mode, but otherwise track on ⁇ anoth ⁇ r.
  • signal patterns oth ⁇ r than th ⁇ clock pattern 1010101 may be gen ⁇ rat ⁇ d by the signal generator 462 and used to achieve the desired phase relationship between the equalizer clock signal and th ⁇ receiv ⁇ clock signal.
  • the signal gen ⁇ rator may be implemented by a pseudo random bit s ⁇ quence (PRBS) gen ⁇ rator that g ⁇ nerates a pseudo random bit sequence.
  • PRBS pseudo random bit s ⁇ quence
  • any signal generator random or otherwise, that generates a sequ ⁇ nce of values having a sufficient transition density (i.e., transitions per unit time) to enable phase locking in the equalizing receiver 450 (i.e., phase locking betw ⁇ n transitions in th ⁇ waveform output by output driver 465 and the receive clock signal) may be used to implem ⁇ nt signal g ⁇ n ⁇ rator 462.
  • tap sel ⁇ ction logic may b ⁇ implemented in a number of different ways.
  • the tap s ⁇ lect logic 139 includes a configuration circuit that may be programmed with configuration information that specifies the tap data sources to be selected by sel ⁇ ct circuit 128.
  • Th ⁇ configuration circuit may include a nonvolatile memory, fusible circuit, ⁇ tc. that is programmed at production time according to the symbol latency, amplitude and polarity of empirically observed (or analytically det ⁇ rmined) distortions.
  • the configuration circuit may include memory (volatile or nonvolatile) which is initialized with predetermined configuration information during system startup.
  • a signaling system includes circuitry to automatically det ⁇ rmin ⁇ th ⁇ symbol latency, amplitude and polarity of distortions on the signaling path between a transmitter and receiver, and to program a configuration circuit within the tap sel ⁇ ct logic with configuration information that indicates the tap data sources to be sel ⁇ ct ⁇ d by a s ⁇ lect circuit and the tap w ⁇ ights and polarities to be appli ⁇ d by an ⁇ qualization circuit.
  • a technique called ⁇ mb ⁇ dd ⁇ d scoping is used to det ⁇ rmin ⁇ the symbol latency, amplitude and polarity of signal path distortions.
  • the symbol latency of a given distortion, onc ⁇ known is used to select one or more tap data values having corresponding symbol latencies, and the distortion amplitud ⁇ and polarity ar ⁇ used to det ⁇ rmin ⁇ th ⁇ weight and polarity to be applied to the selected tap data valu ⁇ in gen ⁇ rating an ⁇ qualization response.
  • the symbol latency of a given distortion may be used to det ⁇ rmine whether to counteract the distortion through transmitter pre ⁇ mphasis or r ⁇ c ⁇ iv ⁇ r ⁇ qualization (or both), and the overall range of symbol latencies for det ⁇ ct ⁇ d distortions may b ⁇ used to d ⁇ termine an appropriate dead range for the signaling system.
  • Embedded scoping involves iterativ ⁇ ly receiving a sequence of symbols in a rec ⁇ iver and comparing th ⁇ r ⁇ c ⁇ ived symbol sequence with a local generation of the sequ ⁇ nce to confirm error-fr ⁇ r ⁇ c ⁇ ption.
  • a thr ⁇ shold voltag ⁇ used to distinguish between symbol values in the incoming signal is offset from a calibrated level by a progressively larg ⁇ r amount until a symbol in th ⁇ s ⁇ qu ⁇ nc ⁇ no longer matches the expected value.
  • Th ⁇ threshold voltage offset at which the failure occurs is ref ⁇ rr ⁇ d to h ⁇ rein as a pass/fail offs ⁇ t and represents a measure of the signal level at the sampling instant at which the failure occurred.
  • Furth ⁇ r by sweeping the rec ⁇ iv ⁇ clock signal through an incr ⁇ m ⁇ ntal s ⁇ qu ⁇ nce of phase offsets, and det ⁇ rmining th ⁇ pass/fail offset at each phase offset, a complete trace of the incoming signal may b ⁇ generat ⁇ d.
  • th ⁇ granularity and start stop points of th ⁇ phas ⁇ offs ⁇ ts and/or threshold voltage steps may be controlled (e.g., by configuring a programmable circuit or register) to enable the waveform trace to b ⁇ constrained to sel ⁇ cted points of interest in the incoming signal (e.g., +N° from an int ⁇ nd ⁇ d sampling instant, N r ⁇ pr ⁇ s ⁇ nting a sw ⁇ p angl ⁇ ).
  • Figure 32 illustrates th ⁇ us ⁇ of ⁇ mbedded scoping to generate a time- based trace 490 of an incoming data signal 486.
  • the range of threshold voltage offsets over which the incoming signal 486 is sampled is indicated by V T
  • the range of phase offsets at which th ⁇ signal is sampl ⁇ d is indicated by D .
  • Each sample point within the swe ⁇ p is indicated by a respective dot within a grid of sample points 480. Note that the sweep may be obtained by stepping the voltage threshold through the rang ⁇ of V ⁇ values for each valu ⁇ of
  • V ⁇ (CAL) V ⁇ (CAL)
  • V ⁇ (CAL) the average of the V T offsets between the pass and fail samples, and recorded as a measure of the incoming signal. That is, the pass/fail offset may be us ⁇ d to ⁇ stablish a data point within the trace 490 as shown. Aft ⁇ r sw ⁇ ping through all th ⁇ sampl ⁇ points within the grid 480 (which swe ⁇ p may be repeated numerous times to obtain an average and to discard statistical outliers), a measure of the incoming signal is obtained as illustrated graphically by the trace 490. Embedded scoping has a number of benefits over traditional signal measurem ⁇ nt techniques.
  • the technique is non-invasive (i.e., no probe contact)
  • the el ⁇ ctrical characteristics of the system under test are unaltered, thereby yi ⁇ lding potentially more accurate results.
  • the trace is gen ⁇ rat ⁇ d from th ⁇ p ⁇ rsp ⁇ ctiv ⁇ of th ⁇ receive circuit itself, meaning that any non-ideal characteristics of the rec ⁇ iv ⁇ circuit are accounted for in th ⁇ resulting signal trace information.
  • embedded scoping may be used to p ⁇ rform numerous run-time analyses, including det ⁇ rmining th ⁇ lat ⁇ ncy and amplitude of refactions and oth ⁇ r distortions within th ⁇ signaling syst ⁇ m.
  • FIG 33 illustrates a signaling system 500 according to an embodim ⁇ nt of the invention.
  • the signaling system 500 includes a receive devic ⁇ 501 and transmit d ⁇ vice 509 that employ embedd ⁇ d scoping to determine equaliz ⁇ r tap s ⁇ lections, tap weights and tap polarities.
  • Th ⁇ transmit device 501 includes a pattern generator 503, data selector 505, equalizing transmitter 507 and application logic 502.
  • the application logic 502 performs the core function of th ⁇ transmitting d ⁇ vice ( ⁇ .g., signal processing, instruction processing, routing control, or any other function) and provides transmit data (TX DATA) to a first input of the data selector 505.
  • TX DATA transmit data
  • the application logic 502 outputs a logic low scope signal 506 (SCOPE) to the data sel ⁇ ctor 505 to s ⁇ lect the transmit data to be passed to the equalizing transmitter 507 for transmission to the rec ⁇ iv ⁇ device 509 via signal path 122
  • SCOPE logic low scope signal 506
  • th ⁇ application logic 502 drives the scope signal 506 high to enable a scoping mode of op ⁇ ration within th ⁇ transmit circuit 501.
  • the data sel ⁇ ctor 505 selects a rep ⁇ ating singl ⁇ -symbol pulse sequence (e.g., a test signal such as: 00100...00100...00100...) generated by the pattern generator 503 to be transmitted to th ⁇ r ⁇ c ⁇ iv ⁇ device 509.
  • the receive device 509 includes an equalizing receiv ⁇ r 510 to rec ⁇ iv ⁇ th ⁇ incoming data signal, a pattern register 511 to store a local version of th ⁇ singl ⁇ -symbol pulse sequence, a multiplex ⁇ r 512 to ⁇ nabl ⁇ th ⁇ pattern register 511 to be switched betw ⁇ n load and barr ⁇ l-shifting mod ⁇ s, a XOR gate 513 to compare the rec ⁇ iv ⁇ d data s ⁇ quence with th ⁇ locally g ⁇ n ⁇ rat ⁇ d s ⁇ qu ⁇ nc ⁇ , and application logic 515 (or other logic) to gen ⁇ rat ⁇ a clock adjust signal (CLK ADJ) and threshold voltage adjust signal (THRESH ADJ) to swe ⁇ p th ⁇ receive clock and threshold voltage us ⁇ d within the equalizing receiver through their scoping ranges.
  • the application logic 515 additionally builds a trace record (i. ⁇ ., data indicative of the incoming data sequ ⁇ nc ⁇ ) based on the output of XOR
  • the multiplexer 512 When the receive device 509 is in a scoping mode of operation, the multiplexer 512 is initially set to load the pattern register 511 with the output of the equalizing receiver 510. After a desired sequ ⁇ nce of data (e.g., the singl ⁇ -symbol puls ⁇ sequence) is shifted into the pattern register 511, the multiplexer 512 is set to enable the barrel-shifting mode of the pattern regist ⁇ r
  • the data sequ ⁇ nc ⁇ loaded into th ⁇ pattern r ⁇ gist ⁇ r 511 is r ⁇ p ⁇ atedly output, bit by bit, to a first input of the XOR gate 513.
  • the data sequ ⁇ nc ⁇ r ⁇ c ⁇ iv ⁇ d by the equalizing receiver is input to a second input of the XOR gate 513 so that the received data sequ ⁇ nc ⁇ is compared, bit by bit, with th ⁇ data sequence stored within the pattern regist ⁇ r 511.
  • th ⁇ pattern regist ⁇ r contents are repeatedly compared with a newly received version of the same data sequence (i.e., putatively th ⁇ sam ⁇ data s ⁇ qu ⁇ nc ⁇ ). Any reception error will result in a mismatch betw ⁇ n th ⁇ receiv ⁇ d value and the corresponding value within th ⁇ pattern register and therefore, when compared by XOR gate 513, will result in an error signal being output from the XOR gat ⁇ 513 to the application logic 515.
  • the application logic 515 may then record the adjusted threshold voltage and clock phase offset at which the error occurred to a signal l ⁇ v ⁇ l for a timing offs ⁇ t within a wav ⁇ form trac ⁇ .
  • Figure 34 illustrates an ex ⁇ mplary waveform trace 527 of a pulse data sequence captured by an emb ⁇ dd ⁇ d scope within the signaling system of Figure 33.
  • a primary pulse 529 arrives at the receiver at symbol time, T 0 ;
  • a negative refl ⁇ ction 531 of th ⁇ primary puls ⁇ app ⁇ ars at symbol tim ⁇ T 5 and a positive refl ⁇ ction 533 appears at symbol time T 12 .
  • the application logic 515 of r ⁇ c ⁇ iv ⁇ r 509 may store configuration information in a s ⁇ l ⁇ ct logic circuit within the equalizing receiver 510 (or elsewh ⁇ r ⁇ within th ⁇ receive device 509) to enable sel ⁇ ction of stored data values having symbol latencies of five and twelve symbol times as tap data sourc ⁇ s for an equalizing circuit.
  • the application logic 515 may directly output select signals to sel ⁇ ct th ⁇ d ⁇ sired stored data values as tap data sources.
  • the application logic 515 may also generate tap weights and tap polarity values in accordance with the amplitude and polarity of the distortions 531 and 533, and store or output the weights and polarity values as necessary to apply the appropriate tap weights and polarities within th ⁇ ⁇ qualizing rec ⁇ iv ⁇ r 510.
  • Figure 35 illustrates a method of setting equalization coefficients in a signaling system according to the invention, hi the embodiment shown, transmit-side equalization coefficients are s ⁇ t first (541), th ⁇ n r ⁇ c ⁇ ive-side ⁇ qualization coefficients are set (551).
  • the transmit-side coefficients are set by transmitting a test signal at 543 (e.g., a pulse signal, st ⁇ p, ⁇ tc), then gen ⁇ rating a waveform trac ⁇ (545) using th ⁇ ⁇ mb ⁇ dded scoping techniques described above.
  • the transmit-side equalization coefficients including tap data sources, tap w ⁇ ights and tap polariti ⁇ s, are then set at 547 to produce a rec ⁇ iv ⁇ d waveform trace that most closely corresponds to the ideal waveform ( ⁇ .g., puls ⁇ , st ⁇ p, etc.) output by the transmitter.
  • the transmit-side equalization coefficients may be d ⁇ t ⁇ rmin ⁇ d analytically (i. ⁇ ., by computing th ⁇ coefficients based on th ⁇ wav ⁇ form trac ⁇ generated at 545) or iteratively, by rep ⁇ ating op ⁇ rations 543 and 545 for diff ⁇ rent combinations of coefficient settings until a coeffici ⁇ nt setting that provides a desired waveform is det ⁇ rmin ⁇ d.
  • the receive-sid ⁇ coefficients are set by transmitting the test signal at 553 (i.e., a pulse, step or other signal transmitted with equalization according to the coefficients set at 547), then generating a waveform trace of the received waveform (555) using the embedded scoping techniques described above.
  • the rec ⁇ iv ⁇ -side ⁇ qualization coefficients including tap data sources, tap weights and tap polarities, are th ⁇ n s ⁇ t at 557 to produce a received waveform that most closely corresponds to the ideal waveform (i.e., waveform having reduc ⁇ d high-lat ⁇ ncy distortion).
  • Th ⁇ rec ⁇ iv ⁇ -sid ⁇ ⁇ qualization coefficients may be det ⁇ rmin ⁇ d analytically as described in reference to Figures 31-33, or iterativ ⁇ ly, by repeating operations 553 and 555 for different combinations of coefficient settings until a coefficient setting that provides a desired waveform is det ⁇ rmin ⁇ d.
  • selection of tap data sources within the transmitter may include outputting test signals on neighboring signal paths simultan ⁇ ously with th ⁇ t ⁇ st signal transmission at 543 to allow determination of which transmit-side equalizer taps, if any, should be sourced by cross-talk cancellation data values (i.e., data values being transmitted on neighboring signal paths) and the corresponding tap weights.
  • the tap select logic 139 and select circuit 128 enable equalization ov ⁇ r a r ⁇ lativ ⁇ ly wid ⁇ rang ⁇ of symbol lat ⁇ ncies using a small numb ⁇ r of ⁇ qualiz ⁇ r taps.
  • the total number of equalizer taps is further reduced through symmetry in the electrical distances betwe ⁇ n signal path discontinuities.
  • Figur ⁇ 36 illustrat ⁇ s a signaling system that employs path length symmetry to reduce the total number of equalization taps need ⁇ d to comp ⁇ nsat ⁇ for refl ⁇ ction-typ ⁇ ISI.
  • Th ⁇ syst ⁇ m includes a pair of circuit boards 571 and 573 (e.g., line cards, port cards, memory modules, etc.) having integrated circuit (IC) devices 575 and 577 mounted resp ⁇ ctively thereon.
  • IC device 575 includes a transmit circuit coupled to a connector interface 581 (e.g., a connector or a terminal to be received by a connector) via signal path s ⁇ gm ⁇ nt 582
  • IC device 577 includes a receive circuit coupled to a connector interface 585 via signal path segment 586.
  • the connector interfaces 581 and 585 are coupl ⁇ d to on ⁇ anoth ⁇ r through signal path segment 592 (e.g., backplan ⁇ trace, cable, etc.) to form an overall signal path between the transmit circuit and receiv ⁇ circuit.
  • the connector interfaces 581 and 585 tend to have at least slightly different impedances than the impedance of path segments 582, 586 and 592, refl ⁇ ctions ar ⁇ produced at comiector interfaces as shown by refl ⁇ ction flight paths A T , A R , C T and C R . Mor ⁇ sp ⁇ cifically, the reflection flight path indicated by A results from the primary signal reflecting off connector interface 581, and the reflection reflecting off the output node of the transmit circuit within IC 575.
  • the reflection flight time over path A T exc ⁇ ds th ⁇ unr ⁇ fl ⁇ ct ⁇ d primary signal flight time by twice the signal propagation time between the connector int ⁇ rfac ⁇ 581 and the transmit circuit output node; i.e., the signal propagation time on path segment 582.
  • the reflection flight time over path AR reflection off rec ⁇ iver input, then off connector int ⁇ rfac ⁇ 585) ⁇ xceeds the unrefl ⁇ ct ⁇ d primary signal flight tim ⁇ by twice the signal propagation time between the connector interface 585 and the receive circuit input; the signal propagation time on path segment 586.
  • path s ⁇ gm ⁇ nts 582 and 586 ar ⁇ designed or calibrated to have equal electrical lengths (i.e., equal signal propagation delays)
  • reflections A T and A R will arrive at the input of the receive circuit of IC device 577 at substantially the same time. Consequently, a single equalization tap having a symbol latency that corresponds to the latent arrival of the coincident A T /A R reflections may be used to cancel or at least reduce both reflections.
  • refl ⁇ ction flight paths C T and CR ar ⁇ mad ⁇ equal by equalizing the electrical lengths of path segments 582 and 586, a single ⁇ qualization tap that corresponds to the latent arrival of coincident CT/C R reflections may be used to cancel or at least reduce both reflections.
  • path segm ⁇ nts 582 and 586 to hav ⁇ equal electrical lengths (which path segm ⁇ nts may optionally include an on-chip path segment betwe ⁇ n th ⁇ transmit circuit output and an IC device 575 output node and/or an on-chip path segm ⁇ nt b ⁇ tw ⁇ n th ⁇ receiv ⁇ circuit input and an IC device 577 input node), one equalization tap within eith ⁇ r the transmit circuit or rec ⁇ iv ⁇ circuit may b ⁇ us ⁇ d to cancel or reduce a distortion that would otherwis ⁇ require two or more taps.
  • path segments 582 and 586 may optionally include an on-chip path segment betwe ⁇ n th ⁇ transmit circuit output and an IC device 575 output node and/or an on-chip path segm ⁇ nt b ⁇ tw ⁇ n th ⁇ receiv ⁇ circuit input and an IC device 577 input node
  • one equalization tap within eith ⁇ r the transmit circuit or rec ⁇ iv ⁇ circuit
  • 586 are made equal (or substantially equal — as achi ⁇ vabl ⁇ through practicable manufacturing techniques) by design which may include, but is not limited to:
  • path s ⁇ gments 582 and 586 1) making the physical lengths of path s ⁇ gments 582 and 586 substantially equal, wheth ⁇ r implemented by printed traces, cables or other types of conductors; 2) including inductive or capacitive structures (e.g., vias, f ⁇ rrite materials, narrowed or widened trace regions, or any other impedance-altering structures) statically coupled in seri ⁇ s or parall ⁇ l with path s ⁇ gm ⁇ nts 582 and/or 586 to ⁇ qualize otherwis ⁇ different electrical lengths of the path segm ⁇ nts; and/or 3) including inductive and/or capacitive structures that may be run-time coupled (e.g., through pass gates or other electrically or magnetically controllable structures) in series or parallel with path s ⁇ gm ⁇ nts 582 and/or 586 to ⁇ qualiz ⁇ otherwise different electrical lengths of the path segm ⁇ nts.
  • inductive or capacitive structures e.g.
  • any technique for adjusting the electrical lengths of path segments 582 and 586 to achieve coincident arrival of two or more signal refl ⁇ ctions at th ⁇ input of an ⁇ qualizing receiv ⁇ r may b ⁇ us ⁇ d without d ⁇ parting from th ⁇ spirit and scope of the present invention.
  • impedance-altering structures may be selectively coupled to path segm ⁇ nts 582 and/or 586 through operation of a configuration circuit (e.g., volatile or non-volatile storage, or fusible or otherwis ⁇ one-time programmable circuit).
  • a configuration circuit e.g., volatile or non-volatile storage, or fusible or otherwis ⁇ one-time programmable circuit.
  • a configuration value that corresponds to the d ⁇ sired electrical length of a path segment may be programmed into the configuration circuit and used to control pass gates or other switching elements for switchably coupling the impedance-altering structures to the path segm ⁇ nt.
  • Th ⁇ d ⁇ sir ⁇ d setting of the configuration value may be determined, for exampl ⁇ , by using th ⁇ ⁇ mb ⁇ dd ⁇ d scoping technique described above in ref ⁇ renc ⁇ to Figures 27-29 to determine relative arrival times of signal refl ⁇ ctions and therefor ⁇ propagation tim ⁇ diff ⁇ rences betw ⁇ n signal r ⁇ fl ⁇ ctions.

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Abstract

L'invention concerne un égalisateur de connexion sélectionnable, un égalisateur auto-configuré, un circuit de réception possédant une fonction d'étalonnage d'égalisateur et un système possédant des caractéristiques de réflexion groupées. L'égalisation de connexion sélectionnable comprend un tampon, un circuit de sélection et un circuit d'égalisation. L'égalisateur auto-configuré comprend un circuit de délimitation, un circuit de tampon, un circuit de sélection et un circuit d'égalisation. Le circuit de réception comprend un circuit d'échantillonnage, un pilote de sortie et un générateur de signal d'horloge. Le système comprend un circuit d'émission, un circuit de réception et un parcours de signal couplé entre le circuit d'émission et le circuit de réception. Le parcours de signal comprend un premier segment couplé entre le circuit d'émission et une première interface et un second segment couplé entre le circuit de réception et une seconde interface, le second parcours de signal possédant une longueur électrique sensiblement égale à une longueur électrique du premier segment du parcours de signal.
PCT/US2003/021566 2002-07-12 2003-07-10 Egalisateur de connexion selectionnable, egalisateur auto-configure, circuit de reception possedant une fonction d'etalonnage d'egalisateur et systeme a caracteristiques de reflexion groupees WO2004008490A2 (fr)

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AU2003251839A AU2003251839A1 (en) 2002-07-12 2003-07-10 A selectable-tap equalizer, auto-configured equalizer, receiving circuit having an equalizer calibration function, and system having grouped reflection characteristics

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US19512802A 2002-07-12 2002-07-12
US10/195,129 US7292629B2 (en) 2002-07-12 2002-07-12 Selectable-tap equalizer
US10/195,128 2002-07-12
US10/195,140 US8861667B1 (en) 2002-07-12 2002-07-12 Clock data recovery circuit with equalizer clock calibration
US10/195,130 US7362800B1 (en) 2002-07-12 2002-07-12 Auto-configured equalizer
US10/195,129 2002-07-12
US10/195,130 2002-07-12
US10/195,140 2002-07-12

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US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7412016B2 (en) 2003-04-09 2008-08-12 Rambus Inc. Data-level clock recovery
US7423454B2 (en) 2003-12-17 2008-09-09 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US7715471B2 (en) 2003-12-17 2010-05-11 Rambus, Inc. Signaling system with selectively-inhibited adaptive equalization
WO2016114548A1 (fr) * 2015-01-12 2016-07-21 Samsung Electronics Co., Ltd. Procédé, système et appareil d'émission et de réception de signal basés sur un banc de filtres
US9461608B2 (en) 2007-03-05 2016-10-04 Nxp B.V. Radio frequency filter
CN113225278A (zh) * 2020-01-21 2021-08-06 默升科技集团有限公司 具有可重叠滤波器抽头的数字均衡器
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CN113364713B (zh) * 2015-07-28 2024-06-04 拉姆伯斯公司 容忍突发的决策反馈均衡
CN113225278A (zh) * 2020-01-21 2021-08-06 默升科技集团有限公司 具有可重叠滤波器抽头的数字均衡器

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