WO2003107411A2 - Dielectric film - Google Patents

Dielectric film Download PDF

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Publication number
WO2003107411A2
WO2003107411A2 PCT/GB2003/002494 GB0302494W WO03107411A2 WO 2003107411 A2 WO2003107411 A2 WO 2003107411A2 GB 0302494 W GB0302494 W GB 0302494W WO 03107411 A2 WO03107411 A2 WO 03107411A2
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Prior art keywords
film
surfaces
layer
nitrogen
formed
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PCT/GB2003/002494
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French (fr)
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WO2003107411A3 (en
Inventor
Keith Edward Buchanan
Joon-Chai Yeoh
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Trikon Technologies Limited
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Priority to GB0213708A priority Critical patent/GB0213708D0/en
Priority to GB0213708.1 priority
Priority to GB0213888.1 priority
Priority to GB0213888A priority patent/GB0213888D0/en
Priority to US60/392,057 priority
Priority to US39205702P priority
Application filed by Trikon Technologies Limited filed Critical Trikon Technologies Limited
Publication of WO2003107411A2 publication Critical patent/WO2003107411A2/en
Publication of WO2003107411A3 publication Critical patent/WO2003107411A3/en

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    • HELECTRICITY
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31633Deposition of carbon doped silicon oxide, e.g. SiOC
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31695Deposition of porous oxides or porous glassy oxides or oxide based porous glass

Abstract

A low k porous dielectric film is described wherein the exposed surface or surfaces of the film are substantially non-porous. A densification method is described for treating such exposed surfaces to render porous surfaces non-porous.

Description

Dielectric Films

This invention relates to porous dielectric films having a dielectric constant (k) of less than about 2.5. Over the past years there has been a constant drive to produce dielectric materials having low dielectric constants for use, particularly, in semiconductor devices to accommodate the ever decreasing dimensions of the device architecture. It is presently believed that to achieve k values of less than about 2.5 for a practical insulator, there is inevitably a degree of porosity in these materials. This porosity can present major problems for integration, particularly when vias or interconnects are formed through the dielectric layer, because, when etched, the side walls of the etched formations are at least rough and possibly permeable, if the pores interconnect at all and intersect the surface.

It is into these etched trenches and vias that copper is deposited, in typical present day architectures, and because copper would readily diffuse into the dielectric material it must be contained by a diffusion barrier. An ideal would be an insulator that had barrier characteristics, but present day solutions rely upon separate deposited layers.

Traditionally these barrier layers were deposited using physical vapour deposition techniques, but these techniques struggle to provide sufficient conformity of barrier coverage and so chemical vapour deposition (CVD) techniques are used e.g. Metal Organic CVD, Metal HaJlde CVD and Atomic Layer CVD. Whilst CVD techniques can give near 100% conformity, the precursors and reactants can penetrate the porous dielectric. This effect is shown in Figure 1 (Source IMEC at the ARMM 2001 Conference) and Figure 2 (Source Passemard et ai; "integration issues of low k and ULK materials and damascene structure" at CREMSI 2001 Conference), in both cases, it will be seen that the side wail appears "fuzzy" and this indicates that CVD precursors have been absorbed into the porous dielectric layer giving rise to an indistinct barrier between the dielectric and the barrier layer.

EP-A-1195801 describes processes which are in fact believed to increase the porosity of the side walls and proposes sealing pores created from the side walls by providing a protective or sealing layer. It suggests that such a sealing layer can be formed by a plasma comprising oxygen and nitrogen, but gives no substantive description of the process. The addition of extra material into high aspect ratio vias is undesirable, both because it increases the aspect ratio of the via and may increase the resistance of the copper in the via. It is not clear whether or not the sealed surface maintains the local low k values as suggested in the application.

From one aspect the present invention includes a porous dielectric film having a dielectric constant (k) of less than about 2.5 and a carbon content of not less than 10% including a via or other formation etched therein characterised in the exposed surface or surfaces of the film within the via or formation is substantially non-porous.

It will be understood that this approach is in complete contrast to EP-A- 1195801 where the processing of the dielectric increases the local porosity at the surface layer and this difficulty is only overcome by adding a further sealing layer. it should also be noted that sealing porous surfaces at the top and bottom of structures is considerably easier than sealing side walls that are parallel to the flux of the incoming reactants.

In a preferred embodiment the exposed surface or surfaces is formed by a layer which is carbon depleted with respect to the buik of the fiim. Additionally or alternatively the exposed surface or surfaces is formed by a layer which is of greater density than the bulk of the material film. In a particularly preferred embodiment the exposed surface or surfaces, may be formed by a layer which is carbon depleted with respect to the bulk of the film. Additionally or alternatively the exposed surface, or surfaces may be formed by a layer constituted substantially by Si-Si bonds and these bonds may be formed between trivalent Si molecules. Other mechanisms which are currently not understood but occur at the exposed surface or surfaces.

In each of these cases it will be understood that the layer defining the exposed surface or surfaces is formed by modifying the etched dielectric material and not by further deposition. The bulk of the film is preferably formed of an SiCOH material.

The surface forming layer or layers may be formed by nitrogen and/or hydrogen containing plasma treatment of the etched surface or surfaces, which may be at least partially coincident with another process such as resist strip.

The invention further includes a barrier layer covering the exposed surface or surfaces, in which case the barrier layer does not penetrate the exposed surface or surfaces. The barrier layer is preferably deposited by chemical vapour deposition.

From a further aspect the invention consists in a method of forming an interconnect layer in a semiconductor device including: a. depositing a low k porous dielectric film on a substrate; b. depositing a resist; c. patterning the resist to define etch apertures; d. etching vias or formations in the dielectric layer through the apertures; and e. stripping the resist characterised in that the resist is stripped with a nitrogen or a noble gas, or combination thereof, and hydrogen plasma or nitrogen or a noble gas, or a combination thereof, and oxygen plasma and the exposed surfaces of the vias or formations are simultaneously exposed to the plasma causing densification of the surface layers which define the exposed surfaces.

The method may also include the deposition of a barrier layer on the densified exposed surfaces. This barrier layer may be deposited by chemical vapour deposition.

Preferably the nitrogen or noble gas dominates the hydrogen or oxygen. Thus it is preferred that the ratio of N2:H2 is about 5:1.

The substrate may be RF bias during the stripping of the photo resist. In alternative approaches the densification may take place during the etch step and it may be created by means of a non-oxidising plasr ia process, e.g. when the low k material is organic in nature.

Although the invention has been defined above, it is to be understood it includes any inventive combination of the features set out above or in the following description.

The invention may be performed in various ways and a specific embodiment will now be described, by way of example, with reference to the following drawings, in which:

Figure 3 is a transmission electron micrograph (TEM) of a cross section of a dielectric material formed with trenches to illustrate features of the invention;

Figure 4 is an enlarged view of part of Figure 3; and Figures 5a - d are electron energy loss spectroscopy (EELS) graphically represented results taken across a line A as indicated in Figure 4.

Figure 6a is a bright field TEM of a cross section of a dielectric of the invention, barrier and copper fiiied trench.

Figure 6b and 6c are bright field TEMS iiiustrating precursor diffusion of the prior art. Figure 7 shows a bright field TEM of a 0.18 micron structure illustrating features of the invention (equivalent to figure 3, but smaller structure).

Figure 8 is an EELS scan for titanium of the structure of Figure 7 for both a) nitrogen and oxygen resist strip/treatment and b) nitrogen and hydrogen resist strip/treatment.

Figure 9 is an EELS scan for carbon of the structure of Figure 7 for both a) nitrogen and oxygen resist strip/treatment and b) nitrogen and hydrogen resist strip/treatment.

Figure 10 shows bright field TEM of a cross section of a dielectric material formed with trenches to illustrate features of the invention where a) is an overview and b), c) and d) are at higher magnification.

Figure 11 shows leakage current through structures made with the invention in 0.18 micron trenches.

Figure 12 shows leakage current through structures made with the invention in 0.25 micron trenches.

Figure 13 shows RC product through structures made with the invention. Figure 14 shows comparisons between MOCVD and sputtered (PVD) barriers upon dielectrics of the invention.

Turning to Figure 3 a test stack is illustrated to reveal a structure common in forming damascene interconnect architecture. The stack 10 is upon a base dielectric iayer 11 and consists of an etch stop layer 12, a dielectric layer 13, which has trenches 14 etched therein, a silicon carbide cap 15 on the upper surface of the dielectric layer 13 and a barrier layer 16. A silicon oxide layer 17 and a planarisation layer 18 have been added purely for the purposes of TEM sample preparation.

The dielectric layers 11 and 13 are constituted by a low k SiCOH material having more than 10% carbon, which is trade marked Orion by the Applicants. This material is porous and has a dielectric constant k of about 2.2. The planarisation layer 18 is a material which is trade marked Flowfill by the Applicants.

The dielectric layers 11 and 13 were deposited using Trikon /xP ™ tool for example as described in WO-A-01/01472, the disclosure of which is incorporated herein by reference. This material is a cold deposition of a polymer, which is then hydrogen plasma cured.

The trenches 14 were etched, without a hard mask, in a Trikon MORI ™ helicon source plasma etch tool using CF4 CH2F2 chemistry with RF wafer bias. Following the plasma etch the photo resist, which defines the etched apertures for the trenches, was stripped in situ in the MORI ™ tool (i.e. in the same chamber) using 5:1 N2:H2 chemistry again with a helicon wave mode plasma source and applied RF wafer bias. This resist stripping also removes polymer residues. As is well known in the art there may be further wet or dry processing steps to be completed between the resist strip and the subsequent MOCVD barrier deposition of the barrier layer 16, though in this case none were used.

As these processes are known to a person skilled in the art they are not detailed here.

MOCVD titanium nitride TiN (Si) was deposited in a stand alone system using TDEAT (Tetra Dϊethyl Amino Titanium) and ammonia precursors together with helium bailast. immediately after deposition, the MOCVD film was hydrogen plasma treated and then silane soaked. There were no thermal or plasma treatments prior to deposition.

It will be seen, immediately, from Figure 3 and even more clearly from Figure 4 that the interface between the barrier 16 and the trench side wall is smooth and continuous and this is in complete contrast to the prior art arrangements shown in Figures 1 and 2. Further the barrier layer itself is smooth and continuous. The micrograph further reveals that the trench side walls adjacent to the barrier layer are less porous (denser) than the regions further away from the side walls. The denser regions are darker in the bright field TEM imagining and are marked J and K in the micrograph. As the deposited film was laterally homogeneous, then densification of the etched side walls has taken place during the trench formation (plasma etch and/or subsequent resist strip). It is believed that at least the majority of the densification has taken place during the resist strip largely because during the etching of the formations there are large amounts of polymer present on the side walls (to effect anoisotrophic etching) that is removed by the subsequent strip processes.

Further evidence for side wall densification comes from Figures 5a - c. The electron energy loss spectroscopy analysis can be used to provide information about the overall thickness and composition of the sample and also the distribution of individual elements. Spatial maps can be generated in a series of such one dimensional maps were taken in the axis identified by the line A of Figure 4 and the results are shown in Figures 5a - b.

Comparisons of the maps support the existence of a densified trench side wall. The signal plotted in 5a varies with sample thickness and sample composition/density. The concave nature of the signal from the layer 13 between the twin peaks of the barrier layer 16 show that the dielectric 13 is denser or thicker near the side walls. It is not believed that the variation is due to thickness. Figure 5b shows the titanium signal and confirms that the barrier layer 16 is tightly confined, there being no detectable titanium signal from within the film 13. Figure 5c shows that the trench side waiis are depleted of carbon whereas the oxygen profile in 5d is comparatively flat. It is therefore concluded that the trench etch and/or resist strip process is densifying the trench side walls of the porous low-k layer, thereby providing a smooth surface to prevent penetration of barrier layer precursors or reactants. This enables the deposition of a continuous barrier thereby preventing copper penetration. Whilst the experiments have only so far been performed on the

Applicants' material it is believed that the same results would be obtained with at least some other ultra low k porous dielectrics particularly those of the SiCOH family, being hydrogenated carbon containing silicon dioxides that are porous. The carbon and hydrogen is in such film typically as C-H3 groups with C-Si bonds effectively tying in large amount of hydrogen and this hydrogen is considered the main cause of the low-k value for the matrix of the film together with the resultant porosity.

The precise mechanism for the densification is not yet known, but it is believed likely that the depletion of carbon from the densified layers enables the forming of Si-Si bonds between trivalent silicon atoms.

The reactive ion etch process of the BARC and porous low-k SiCOH material with a photo resist mask on 200mm wafers was:

Process gasses CF4 , and CH2F2 in the ratio 4.4:1 to 6.6:1

Pressure 1.5-2 millitorr Plasma power 1 ,25 KW to an inductive antenna

Wafer bias power 400 watts

Platen temperature -15°C

The reactive ion photo resist strip process on 200mm wafers, carried out in the same chamber was: Process gasses N2 and H2 in the ratio 5:1

Pressure 5 millitorr

Plasma power 2.5 KW to an inductive antenna Wafer bias power 200 watts

Platen temperature 0°C

The etch process was with electrostatic wafer clamping and helium back side pressurisation and wafer temperature will therefore be close to the platen temperature. A low temperature is used to retain resist integrity.

For the resist strip process the wafer was undamped to allow higher wafer temperatures, thereby improving residue removal efficiency and increasing strip rate. Peak wafer temperature was indicated as 121°C (be means of industry standard thermal stickers) at 0°C platen temperature and 104°C at -15°C platen temperature.

These experiments have used nitrogen and hydrogen, however if nitrogen is not chemically active in the densification process then alternatives may be substituted such as helium, neon, argon, xenon and krypton or any other suitable sputter etch gas. Alternatively they may be added to the nitrogen and/or hydrogen gas mix.

Further work has been performed to illustrate the effectiveness of the invention. At Figure 6(a) is shown a bright field TEM image of a completed structure consisting of dielectric of the invention with an MOCVD deposited titanium nitride barrier and completed copper trench fill consisting of a sputtered copper seed layer, electroplated copper and chemical mechanical polishing step. As can be seen there has been no diffusion of metal from either the barrier or copper into the dielectric.

Further Figure 6(a) shows an amorphous layer of 5 to 8 nanometers thickness that is modified by the plasma treatment and is of higher density compared to the bulk of the porous dielectric.

In contrast at Figures 6(b) and 6(c) are shown precursor diffusion. The image at 6(b) is from W. Besling, Proc. IITC 2002 Burlingame (CA) USA, 2002 pp 288-291. The image at 6(c) is from S. Kawamura et. al. Proc IITC 2001 San Francisco, USA, pp 195-197. As can be seen bright field TEM imagery is a well known and acceptable indication of metal diffusion into a dielectric material.

Figure 7 is TEM image of a 0.18 micron structure formed as previously described in relation to Figure 3. No metal diffusion for the barrier can be seen and this is further evidenced at Figure 8(a) and 8(b) that are EELS line scans for titanium of the structure shown at Figure 7.

Figure 8(a) illustrates the EELS scan for a nitrogen and hydrogen gas mix. At Figure 8(b) a gas mix of 200sccm of nitrogen and 10 seem of oxygen was used (a ratio of 40:1 is the best that has been established at this time ).

Oxygen is well known to remove carbon and this experiment illustrates that nitrogen can reduce the carbon removal effect of the oxygen and allow porous dielectrics to withstand a high degree the absorption of a gaseous metal precursor (though not as good as nitrogen + hydrogen). This process is in contrast to that described in EP-A-1195801 in which a nitrogen/oxygen plasma is used to form a sealing layer.

Figure 9(a) and 9(b) show EELS line scans through the structure of Figure 7 for carbon. In Figure 9(a), the EELS scan for nitrogen and oxygen shows there is greater carbon loss at the dielectric side walls than is the case for nitrogen and hydrogen as illustrated at Figure 9(b).

Figure 10 is a further illustration of an embodiment of the invention in bright field TEM images. Figure 10(a) is an overview of a structure formed as described above at Figure 3. Figure 10(d) is the result of the nitrogen and hydrogen process described in detail earlier and Figure 10(b) and 10(c) are images illustrating a nitrogen and oxygen gas mix treatment.

Figures 11 to 14 show results from electrical test structures formed with dielectric which are embodiments of the invention. The test structures were single damascene of line width/line spacing of 0.18 and 0.25 micron trenches/spacers. The interdigital comb was 100 microns by 1600 microns in size with a 44cm perimeter. Inter-line leakage was measured at 0.5 MV/cm and interline capacitance was measured at 1MHz.

The plasma treatment/resist strip processes were as follows: Nitrogen + Hydrogen (5:1 ratio)

Nitrogen 200 seem (std. cubic centilitres per minute)

Hydrogen 40 seem

Pressure 7 millitorr

Platen temperature -15°C Electrostatic chuck with 2 Torr helium back pressure

MORI™ plasma source (inductively coupled) Plasma power 2.5Kw to inductive antenna 13.56MHz Magnet power 40/60Amps inner/outer coils

Platen power (wafer bias) 200 W 13.56MHz

Nitrogen + Oxygen (20:1 ratio)

Nitrogen 200 seem

Oxygen 10 seem

Pressure 7 millitorr

Platen temperature -15°C Electrostatic chuck with 2 Torr helium back pressure

MORI™ plasma source (inductively coupled)

Plasma power 2.5Kw to inductive antenna 13.56MHz

Magnet power 60/60Amps inner/outer coils

Platen power (wafer bias) 30 W 13.56MHz This was the best nitrogen + oxygen process for densification and is in contrast to the sealing process of EP-A-1195801.

Note that in these subsequent experiments, the wafers were clamped electrostatically thereby lowering their temperature to close to the platen temperature. It was found that the processes were still effective at these lower wafer temperatures.

Figure 11 shows the results for leakage current (less is better) on 0.18 micron trenches for both nitrogen + hydrogen and nitrogen + oxygen gas mixtures. As can be seen the oxygen degrades the performance compared to the hydrogen. This is to be expected given the EELS result of Figures 9(a) and

9(b) showing increased carbon loss for the nitrogen + oxygen process. Further, a wet clean does not degrade the nitrogen + hydrogen treated dielectric, but does degrade slightly the nitrogen + oxygen treated dielectric, further indicating a degree of porosity. Such wet cleans are widely known and used in the industry to remove any residues after a dry resist strip process.

Figure 12 is a further illustration of the comparative effects of nitrogen and hydrogen or oxygen as for Figure 11 but on 0.25 micron structures. The results and conclusions are the same as for Figure 11.

Figure 13 shoes the RC product (less is better) from the test structures. As can be seen an industry standard wet clean does degrade the RC product slightly for both nitrogen + hydrogen and nitrogen + oxygen processes, with again better results for the nitrogen + hydrogen processes.

Figure 14 shows comparative results from 0.18 and 0.25 micron test electrical test structures with the barrier deposited by MOCVD and PVD (sputtering) means. The comparison shows that the leakage currents are low, and similar.

Claims

Claims
1. A porous dielectric film having a dielectric constant (k) of less than about 2.5 and a carbon content of not less than 10% including a via or other formation etched therein characterised in that the exposed surface or surfaces of the film within the via or formation is substantially non-porous.
2. A film as claimed in claim 2 wherein the exposed surface or surfaces is formed by a layer which is carbon depleted with respect to the bulk of the film.
3. A film as claimed in claim 1 or claim 2 wherein the exposed surface or surfaces is formed by a layer which is of greater density than the bulk of the material film.
4. A film as claimed in any one of the preceding claims wherein the exposed surface or surfaces is formed by a layer which is oxygen depleted with respect to the bulk of the film.
5. A film as claimed in any one of the preceding claims wherein the exposed surface or surfaces is formed of a layer constituted substantially by Si-Si bonds.
6. A film as claimed in claim 4 wherein the Si-Si bonds are formed between trivalent Si molecules.
7. A film as claimed in any one of the preceding claims wherein the matrix of the film is formed of a SiCOH material.
8. A film as claimed in any one of the preceding claims wherein the surface forming iayer is formed by a nitrogen and/or hydrogen plasma treatment of the etched surface or surfaces.
9. A film as claimed in any one of the preceding claims wherein the exposed surface or surfaces is covered by a barrier layer.
10. A film as claimed in claim 9 wherein the barrier iayer does not peneirate the exposed surface or surfaces.
11. A film as claimed in claim 9 or claim 10 wherein the barrier layer is deposited by chemical vapour deposition.
12. A method of forming an interconnect layer in a semiconductor device including: a. depositing a low-k porous dielectric film on a substrate; b. depositing resist; c. patterning the resist to define etch apertures; d. etching vias or formation in the dielectric layer through the apertures; and e. stripping the resist characterised in that the resist is stripped with a nitrogen or a noble gas, or combination thereof, and hydrogen plasma or nitrogen or a noble gas, or a combination thereof, and oxygen plasma and the exposed surfaces of the vias or formations are simultaneously exposed to the plasma ensuring densification of the surface layers which define the exposed surfaces.
13. A method as claimed in claim 12 wherein a barrier layer is deposited on the densified exposed surfaces.
14. A method as claimed in claim 13 wherein the barrier layer is deposited by chemical vapour deposition.
15. A method as claimed in any one of claims 12 to 14 wherein the ratio of
N2:H2 is about 3-7:1.
16. A method as claimed in any one of claims 12 to 14 wherein the ratio N2:O2 is at least about 15:1
17. A method as claimed in claim 16 wherein the N2:O2 ratio is about 20:1.
18. A method as claimed in any one of claims 12 to 16 wherein the substrate is RF biased during the stripping of the photo resist.
19. A method of removing resist from a porous dielectric film having a dielectric constant (k) of less than about 2.5 and a carbon content of not less than 10% using a plasma containing hydrogen and one or more of the following elements: helium, nitrogen, neon, argon, krypton, xenon or combination.
PCT/GB2003/002494 2002-06-14 2003-06-10 Dielectric film WO2003107411A2 (en)

Priority Applications (6)

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GB0213708A GB0213708D0 (en) 2002-06-14 2002-06-14 Dielectric films
GB0213708.1 2002-06-14
GB0213888.1 2002-06-18
GB0213888A GB0213888D0 (en) 2002-06-18 2002-06-18 Dielectric films
US39205702P true 2002-06-28 2002-06-28
US60/392,057 2002-06-28

Applications Claiming Priority (4)

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DE10392480T DE10392480T5 (en) 2002-06-14 2003-06-10 Dielectric films
AU2003236897A AU2003236897A1 (en) 2002-06-14 2003-06-10 Porous dielectric films with a non-porous surface
GB0419112A GB2410832A (en) 2002-06-14 2003-06-10 Porous dielectric films with a non-porous surface
GBGB0422825.0A GB0422825D0 (en) 2002-06-14 2004-10-14 Porous dielectric films with a non-porous surface

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Publication number Priority date Publication date Assignee Title
WO2004063422A2 (en) * 2003-01-13 2004-07-29 Applied Materials, Inc. Method for curing low dielectric constant film using direct current bias

Citations (5)

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Publication number Priority date Publication date Assignee Title
US6114259A (en) * 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage
US20010038889A1 (en) * 1999-01-15 2001-11-08 Suzette K. Pangrle Method and system for modifying and densifying a porous film
WO2002001621A2 (en) * 2000-06-23 2002-01-03 Honeywell International, Inc. Method to restore hydrophobicity in dielectric films and materials
US6351039B1 (en) * 1997-05-28 2002-02-26 Texas Instruments Incorporated Integrated circuit dielectric and method
EP1195801A2 (en) * 2000-09-29 2002-04-10 Applied Materials, Inc. Process for plasma treating an isolation layer with low permittivity

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US6351039B1 (en) * 1997-05-28 2002-02-26 Texas Instruments Incorporated Integrated circuit dielectric and method
US20010038889A1 (en) * 1999-01-15 2001-11-08 Suzette K. Pangrle Method and system for modifying and densifying a porous film
US6114259A (en) * 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage
WO2002001621A2 (en) * 2000-06-23 2002-01-03 Honeywell International, Inc. Method to restore hydrophobicity in dielectric films and materials
EP1195801A2 (en) * 2000-09-29 2002-04-10 Applied Materials, Inc. Process for plasma treating an isolation layer with low permittivity

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004063422A2 (en) * 2003-01-13 2004-07-29 Applied Materials, Inc. Method for curing low dielectric constant film using direct current bias
WO2004063422A3 (en) * 2003-01-13 2005-09-22 Applied Materials Inc Method for curing low dielectric constant film using direct current bias

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GB0419112D0 (en) 2004-09-29
WO2003107411A3 (en) 2004-03-04
GB0422825D0 (en) 2004-11-17
AU2003236897A1 (en) 2003-12-31
GB2410832A (en) 2005-08-10
AU2003236897A8 (en) 2003-12-31
DE10392480T5 (en) 2005-09-01

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