US20070145007A1 - Semiconductor structure - Google Patents

Semiconductor structure Download PDF

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Publication number
US20070145007A1
US20070145007A1 US11/706,201 US70620107A US2007145007A1 US 20070145007 A1 US20070145007 A1 US 20070145007A1 US 70620107 A US70620107 A US 70620107A US 2007145007 A1 US2007145007 A1 US 2007145007A1
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United States
Prior art keywords
layer
dielectric
etch stop
etch
trench
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Abandoned
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US11/706,201
Inventor
Keith Buchanan
Joon-Chai Yeoh
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Individual
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Individual
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Priority to US11/706,201 priority Critical patent/US20070145007A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Definitions

  • This invention relates to a semiconductor structure for dual damascene processing.
  • Damascene processing is becoming particularly important in the formation of semiconductor devices, because it is the method which is most suited to the deposition of copper.
  • damascene processing it is necessary to etch different, but overlapping, structures into stacked layers of dielectric by successive etch processes and this is best achieved when it is possible to detect when the etch has reached the boundary between two layers in a stack.
  • the present invention consists in a semiconductor structure suitable for dual damascene processing including upper and lower low dielectric constant (k) dielectric layers formed in a stack wherein the upper surface of the lower layer has an integral etch stop layer formed by exposing the upper surface of the layer to H 2 plasma without any prior anneal, prior to the deposition of the upper layer.
  • k low dielectric constant
  • the material of at least the lower dielectric layer may be of SiCHO type material and may for example be formed by reacting tetramethylsilane and oxygen.
  • the etch stop layer is less than 1000 ⁇ thick and is formed coincidentally with the lower dielectric layer and thus not consuming any additional process resources of time, materials or equipment over that required to fully form the dielectric layer.
  • the invention consists in a method of etching dielectric layers including utilizing a surface layer formed by H 2 plasma treatment of a SiCHO type material low k dielectric as an etch stop layer.
  • the etching may form part of a dual damascene process.
  • FIG. 1 is a scrap cross-section showing the prior art arrangement for dual damascene processing
  • FIG. 2 is an equivalent view illustrating the process of the invention
  • FIG. 3 is a view corresponding to FIG. 2 , but wherein the etch elements have become partially offset;
  • FIG. 4 is a SIM profile for a TMS and O 2 deposited film which has been set with a 5 minute H 2 plasma.
  • FIG. 1 a dual damascene structure has been etched on a semiconducting or insulating wafer.
  • a metalised via at 1 is bordered by a low dielectric constant insulating layer 2 having an etch stop layer 3 on its surface.
  • This stop layer has the function or providing a stop for a trench etch process.
  • the etch stop layer is then subsequently sputter etched removed from the top of the metal in the via to allow subsequent metal in the trench to contact it.
  • the trench has been etched in a low dielectric constant insulator 4 using a mask 5 .
  • layers 2 and 4 are essentially the same materials and are frequently bounded by other layers such as barrier layer 6 and capping layer 7 .
  • FIG. 2 One example of the invention is illustrated in FIG. 2 .
  • a via filled with metal or organic plug 1 a formed in a low dielectric constant insulating layer 8 may be present—though not necessarily so.
  • the precise sequence of when the via is etched and filled with metal is not important to the need for an etch stop layer for the formation of the overlaying trench.
  • This layer may have a barrier layer 6 a .
  • a second dielectric layer 9 is provided as in the prior art as is a mask 5 a.
  • a typical treatment to create such an etch stop layer would be a hydrogen plasma treatment consisting of a 400° C. platen, 4 torr pressure, 1000 sccm of H 2 and 1 kw applied at 13.56 MHz to an upper showerhead electrode.
  • a hydrogen plasma treatment consisting of a 400° C. platen, 4 torr pressure, 1000 sccm of H 2 and 1 kw applied at 13.56 MHz to an upper showerhead electrode.
  • pure hydrogen has been used by hydrogen mixed with inert carrier gases or hydrogen containing gases may be suitable.
  • via etching onto a trench may also be improved by a surface layer of the invention, for example if the via mask is mis-aligned as illustrated in FIG. 3 .
  • a metalised trench 12 has a via 13 etched to make a contact. If properly aligned and bordered this via etch would terminate on the trench metal completely, but if it is mis-aligned the via etch will need to terminate on a mix of trench metal and trench insulating layer 14 .
  • the via etch will be improved.
  • the surface modification of the trench insulating layer will assist in via etches tolerating mis-alignment of the via mask and thus increase wafer yields.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

This invention relates to a semiconductor structure for dual damascene processing and includes upper and lower low k dielectric layers formed in a stack when the upper surface of the lower layer has an integral etch stop layer formed by exposing the upper surfaces of the layer H2 plasma without any prior anneal prior to the deposition of the upper layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This is a divisional of application Ser. No. 10/484,168, filed Jan. 20, 2004, which is incorporated herein by reference in its entirety.
    • BACKGROUND
  • This invention relates to a semiconductor structure for dual damascene processing.
  • Damascene processing is becoming particularly important in the formation of semiconductor devices, because it is the method which is most suited to the deposition of copper. In order to perform damascene processing it is necessary to etch different, but overlapping, structures into stacked layers of dielectric by successive etch processes and this is best achieved when it is possible to detect when the etch has reached the boundary between two layers in a stack. In order for this stage to be detected, it is typical to form an etch stop layer at the boundary and this is typically done by depositing a thin layer of silicon nitride or carbide between the two dielectric layers. These materials have relatively high dielectric constants and add both to the thickness of the device and the dielectric constant of the dielectric stack.
    • SUMMARY
  • The present invention consists in a semiconductor structure suitable for dual damascene processing including upper and lower low dielectric constant (k) dielectric layers formed in a stack wherein the upper surface of the lower layer has an integral etch stop layer formed by exposing the upper surface of the layer to H2 plasma without any prior anneal, prior to the deposition of the upper layer.
  • The material of at least the lower dielectric layer may be of SiCHO type material and may for example be formed by reacting tetramethylsilane and oxygen.
  • It is preferred that the etch stop layer is less than 1000 Å thick and is formed coincidentally with the lower dielectric layer and thus not consuming any additional process resources of time, materials or equipment over that required to fully form the dielectric layer.
  • From another aspect the invention consists in a method of etching dielectric layers including utilizing a surface layer formed by H2 plasma treatment of a SiCHO type material low k dielectric as an etch stop layer.
  • The etching may form part of a dual damascene process.
  • Although the invention has been defined above it is to be understood it includes any inventive combination of the features set out above or in the following description.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention may be performed in various ways and will now be described, by way of example, with reference to the accompanying drawings, in which:
  • FIG. 1 is a scrap cross-section showing the prior art arrangement for dual damascene processing;
  • FIG. 2 is an equivalent view illustrating the process of the invention;
  • FIG. 3 is a view corresponding to FIG. 2, but wherein the etch elements have become partially offset; and
  • FIG. 4 is a SIM profile for a TMS and O2 deposited film which has been set with a 5 minute H2 plasma.
    • DETAILED DESCRIPTION
  • In FIG. 1 a dual damascene structure has been etched on a semiconducting or insulating wafer. Thus a metalised via at 1 is bordered by a low dielectric constant insulating layer 2 having an etch stop layer 3 on its surface. This stop layer has the function or providing a stop for a trench etch process. The etch stop layer is then subsequently sputter etched removed from the top of the metal in the via to allow subsequent metal in the trench to contact it. The trench has been etched in a low dielectric constant insulator 4 using a mask 5. Typically layers 2 and 4 are essentially the same materials and are frequently bounded by other layers such as barrier layer 6 and capping layer 7.
  • One example of the invention is illustrated in FIG. 2. A via filled with metal or organic plug 1 a formed in a low dielectric constant insulating layer 8 may be present—though not necessarily so. The precise sequence of when the via is etched and filled with metal is not important to the need for an etch stop layer for the formation of the overlaying trench. This layer may have a barrier layer 6 a. A second dielectric layer 9 is provided as in the prior art as is a mask 5 a.
  • In the applicants' International Patent Application WO 01/01472, which is incorporated herein by reference, a method of forming a low k dielectric material by reacting tetramethylsilane and oxygen and subsequently treating it with H2 plasma is described. In FIG. 19 of that document, which is hereby reproduced as FIG. 4, it was shown that such a film had a surface layer which was chemically different to the bulk of the layer. At the time, the applicants assumed that they would remove that layer so as to achieve a consistent dielectric material, but in any event that, for dual damascene and related processes, they would have to provide the convention etch stop layer. The applicants have now determined that this surface layer or curst can be utilized as an etch stop layer. Thus in FIG. 2 the curst portion, which is indicated at 16, FIG. 4, forms the integral etch stop layer 10 for dielectric layer 8 and can indeed constitute a capping layer 11 for the dielectric constant layer 9.
  • A typical treatment to create such an etch stop layer would be a hydrogen plasma treatment consisting of a 400° C. platen, 4 torr pressure, 1000 sccm of H2 and 1 kw applied at 13.56 MHz to an upper showerhead electrode. Typically pure hydrogen has been used by hydrogen mixed with inert carrier gases or hydrogen containing gases may be suitable.
  • Whilst trench etch has been described here, via etching onto a trench may also be improved by a surface layer of the invention, for example if the via mask is mis-aligned as illustrated in FIG. 3. In this case a metalised trench 12 has a via 13 etched to make a contact. If properly aligned and bordered this via etch would terminate on the trench metal completely, but if it is mis-aligned the via etch will need to terminate on a mix of trench metal and trench insulating layer 14. It can readily be seen that if a surface modification of the trench insulating layer upper surface 15 has been carried out to form an integral etch stop surface then the via etch will be improved. Thus the surface modification of the trench insulating layer will assist in via etches tolerating mis-alignment of the via mask and thus increase wafer yields.

Claims (2)

1. A method of etching dielectric layers comprising utilizing a surface layer formed by H2 plasma treatment of a SiCHO type material low k dielectric as an etch stop layer.
2. The method as claimed in claim 2 wherein the etching forms part of a damascene process.
US11/706,201 2001-07-19 2007-02-15 Semiconductor structure Abandoned US20070145007A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/706,201 US20070145007A1 (en) 2001-07-19 2007-02-15 Semiconductor structure

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
GB0117600.7 2001-07-19
GBGB0117600.7A GB0117600D0 (en) 2001-07-19 2001-07-19 Semiconductor structure
US10/484,168 US7199474B2 (en) 2001-07-19 2002-07-15 Damascene structure with integral etch stop layer
PCT/GB2002/003208 WO2003009341A2 (en) 2001-07-19 2002-07-15 Damascene structure with integral etch stop layer
US11/706,201 US20070145007A1 (en) 2001-07-19 2007-02-15 Semiconductor structure

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
PCT/GB2002/003208 Division WO2003009341A2 (en) 2001-07-19 2002-07-15 Damascene structure with integral etch stop layer
US10/484,168 Division US7199474B2 (en) 2001-07-19 2002-07-15 Damascene structure with integral etch stop layer

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US20070145007A1 true US20070145007A1 (en) 2007-06-28

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US10/484,168 Expired - Fee Related US7199474B2 (en) 2001-07-19 2002-07-15 Damascene structure with integral etch stop layer
US11/706,201 Abandoned US20070145007A1 (en) 2001-07-19 2007-02-15 Semiconductor structure

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US (2) US7199474B2 (en)
JP (1) JP2004522315A (en)
AU (1) AU2002319427A1 (en)
GB (2) GB0117600D0 (en)
TW (1) TW578211B (en)
WO (1) WO2003009341A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132369B2 (en) * 2002-12-31 2006-11-07 Applied Materials, Inc. Method of forming a low-K dual damascene interconnect structure
US9318378B2 (en) * 2004-08-21 2016-04-19 Globalfoundries Singapore Pte. Ltd. Slot designs in wide metal lines
US7777296B2 (en) * 2006-12-05 2010-08-17 International Business Machines Corporation Nano-fuse structural arrangements having blow protection barrier spaced from and surrounding fuse link
US7955968B2 (en) * 2009-03-06 2011-06-07 Freescale Semiconductor, Inc. Pseudo hybrid structure for low K interconnect integration
US9064850B2 (en) * 2012-11-15 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via formation with improved topography control
US10170354B2 (en) * 2015-04-12 2019-01-01 Tokyo Electron Limited Subtractive methods for creating dielectric isolation structures within open features

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283173A (en) * 1990-01-24 1994-02-01 The Research Foundation Of State University Of New York System to detect protein-protein interactions
US5583210A (en) * 1993-03-18 1996-12-10 Pioneer Hi-Bred International, Inc. Methods and compositions for controlling plant development
US5688665A (en) * 1994-01-07 1997-11-18 Fred Hutchinson Cancer Research Center Isolated nucleic acid molecules encoding the p27 KIP-1 protein
US5750862A (en) * 1990-11-29 1998-05-12 The Australian National University Control of plant cell proliferation and growth
US20020055275A1 (en) * 1999-02-26 2002-05-09 Macneil John Dielectric layer for a semiconductor device and method of producing the same
US6528432B1 (en) * 2000-12-05 2003-03-04 Advanced Micro Devices, Inc. H2-or H2/N2-plasma treatment to prevent organic ILD degradation
US6720247B2 (en) * 2000-12-14 2004-04-13 Texas Instruments Incorporated Pre-pattern surface modification for low-k dielectrics using A H2 plasma
US6962869B1 (en) * 2002-10-15 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. SiOCH low k surface protection layer formation by CxHy gas plasma treatment
US7001848B1 (en) * 1997-11-26 2006-02-21 Texas Instruments Incorporated Hydrogen plasma photoresist strip and polymeric residue cleanup process for oxygen-sensitive materials

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6340435B1 (en) 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
GB2355992B (en) * 1999-06-26 2004-06-02 Trikon Holdings Ltd Method and apparatus for forming a film on a substrate
GB0001179D0 (en) 2000-01-19 2000-03-08 Trikon Holdings Ltd Methods & apparatus for forming a film on a substrate

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283173A (en) * 1990-01-24 1994-02-01 The Research Foundation Of State University Of New York System to detect protein-protein interactions
US5750862A (en) * 1990-11-29 1998-05-12 The Australian National University Control of plant cell proliferation and growth
US5583210A (en) * 1993-03-18 1996-12-10 Pioneer Hi-Bred International, Inc. Methods and compositions for controlling plant development
US5688665A (en) * 1994-01-07 1997-11-18 Fred Hutchinson Cancer Research Center Isolated nucleic acid molecules encoding the p27 KIP-1 protein
US7001848B1 (en) * 1997-11-26 2006-02-21 Texas Instruments Incorporated Hydrogen plasma photoresist strip and polymeric residue cleanup process for oxygen-sensitive materials
US20020055275A1 (en) * 1999-02-26 2002-05-09 Macneil John Dielectric layer for a semiconductor device and method of producing the same
US6528432B1 (en) * 2000-12-05 2003-03-04 Advanced Micro Devices, Inc. H2-or H2/N2-plasma treatment to prevent organic ILD degradation
US6720247B2 (en) * 2000-12-14 2004-04-13 Texas Instruments Incorporated Pre-pattern surface modification for low-k dielectrics using A H2 plasma
US6962869B1 (en) * 2002-10-15 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. SiOCH low k surface protection layer formation by CxHy gas plasma treatment

Also Published As

Publication number Publication date
JP2004522315A (en) 2004-07-22
GB2394835A (en) 2004-05-05
GB2394835B (en) 2005-07-06
WO2003009341A2 (en) 2003-01-30
US7199474B2 (en) 2007-04-03
US20040219794A1 (en) 2004-11-04
WO2003009341A3 (en) 2003-03-27
GB0117600D0 (en) 2001-09-12
AU2002319427A1 (en) 2003-03-03
GB0400480D0 (en) 2004-02-11
TW578211B (en) 2004-03-01

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