WO2003100546A2 - Commande de redemarrage de processeur - Google Patents

Commande de redemarrage de processeur Download PDF

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Publication number
WO2003100546A2
WO2003100546A2 PCT/GB2003/002301 GB0302301W WO03100546A2 WO 2003100546 A2 WO2003100546 A2 WO 2003100546A2 GB 0302301 W GB0302301 W GB 0302301W WO 03100546 A2 WO03100546 A2 WO 03100546A2
Authority
WO
WIPO (PCT)
Prior art keywords
processor
error manager
restart
commands
handling
Prior art date
Application number
PCT/GB2003/002301
Other languages
English (en)
Other versions
WO2003100546A3 (fr
Inventor
Regis Adjamah
Original Assignee
Sendo International Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0212143.2A external-priority patent/GB0212143D0/en
Application filed by Sendo International Limited filed Critical Sendo International Limited
Priority to AU2003241016A priority Critical patent/AU2003241016A1/en
Publication of WO2003100546A2 publication Critical patent/WO2003100546A2/fr
Publication of WO2003100546A3 publication Critical patent/WO2003100546A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4405—Initialisation of multiprocessor systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/72—Mobile telephones; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selection
    • H04M1/724—User interfaces specially adapted for cordless or mobile telephones

Definitions

  • the present invention relates to a method of handling a restart of a first processor and an .error manager for carrying out the method.
  • the present invention is applicable to, but not limited to, a method of handling a restart of a first processor in a mobile communications device and an error manager there for.
  • Mobile communications devices are being provided with more and more functionality.
  • so-called ⁇ Smart Phones' are being provided with not only conventional cellular communications functionality, but also functionality resembling that of personal digital assistants (PDAs), and more.
  • PDAs personal digital assistants
  • a first processor system comprising a first processor, may be responsible for controlling communication with a network to which the mobile communications device is connected.
  • the first processor system in this manner, would handle a protocol stack and signal processing, and control components such as an RF module, baseband/audio CODEC, battery manager, subscriber identification module (SIM) card reader, etc.
  • SIM subscriber identification module
  • a second processor system comprising a second processor, may be responsible for running man-machine interface (MMI) applications and controlling a display, keypad, universal serial bus (USB) and/or IrDA interfaces, etc.
  • MMI man-machine interface
  • USB universal serial bus
  • IrDA IrDA interfaces
  • the second processor system controls at least some of the configuration of the first processor system, and instructs the first processor system to perform various tasks.
  • the first processor system is in an operational state expected by the second processor system. If, however the first processor restarts, essentially restarting all of the first processor system, when the second processor system is not expecting it, the first processor system is unlikely to be in a state expected by the second processor system following the restart operation.
  • the first processor is in an operational state expected by the second processor after a re-start operation as, for example, the MMI running on the second processor controls many of the functions of the communication software on the first processor. Furthermore, it is useful to provide to the user an indication of available communication options that the user is able to select. If the first processor is not in an expected state, the MMI software of the second processor will not know what operations can be performed by the first processor in its present state, nor determine how to change the state of the first processor (where required) in order to perform the operations.
  • the second processor may force a restart of both processors in order for both processors to be in a ⁇ fresh', and thereby aligned state.
  • a method of handling a restart of a first processor in a dual-processor system according to Claim 1.
  • a processor-controlled device including an error manager, according to Claim 4.
  • a third aspect of the present invention there is provided a method of handling a restart of a first processor in a dual-processor system, according to Claim 9.
  • a processor-controlled wireless communication device including an error manager, according to Claim 12.
  • an error manager prevents the second processor from forcing a restart of both the first and second processors by intercepting the signals and/or commands identifying the restart of the first processor and preventing them from reaching the second processor. Furthermore, the error manager of the preferred embodiment of the present invention returns the first processor to a state expected by the second processor by sending the initialisation and/or configuration signals and/or commands to the first processor.
  • FIG. 1 illustrates an example of a dual-processor device with which the preferred embodiment of the present invention may be implemented.
  • FIG. 2 illustrates a preferred process for handling commands received from a second processor according to the preferred embodiment of the present invention.
  • FIG. 3 illustrates a preferred process for an error manager to determine a first processor re-start operation and initiate an initialisation/reconfiguration process according to the preferred embodiment of the present invention.
  • the preferred embodiment of the present invention provides a method for handling a restart operation of a first processor.
  • the method comprises the steps of monitoring signals sent from the first processor to a second processor, identifying a restart of the first processor from the signals being sent from the first processor to the second processor, intercepting the signals, and preventing them from reaching the second processor.
  • FIG. 1 illustrates, a dual-processor device 100, for example a mobile communications device, in which the preferred embodiment of the present invention may be implemented.
  • the processor arrangement comprises a first processor 110, which forms a part of a first processor system (not shown) , and a second processor 120, which forms part of a second processor system (not shown) .
  • the first processor system may be responsible for controlling communication with a network to which the mobile communications device is connected, for example handling a protocol stack and signal processing. Furthermore, the first processor system preferably controls components (not shown) such as an RF module, baseband/audio CODEC, battery manager, subscriber identification module (SIM) card reader, etc.
  • components such as an RF module, baseband/audio CODEC, battery manager, subscriber identification module (SIM) card reader, etc.
  • the second processor system may be responsible for running a man-machine interface (MMI) and controlling a display, keypad, USB and/or IrDA interfaces etc.
  • MMI man-machine interface
  • the mobile communications device 100 is compatible with the Global System for Mobile Communications standards.
  • the first processor 110 has running thereon the necessary software 112 for controlling RF circuitry (not shown) etc for operating with a GSM network.
  • Such software includes layer 1 and GSM protocol software, as is well known.
  • a man-machine interface (MMI) software application 122 runs on the second processor 120.
  • MMI software applications are well known, and provide, for example, a graphical interface to a user by way of a display (not shown) or the like.
  • the MMI software application 122 also processes instructions received from the user by way of a keypad (not shown) or the like.
  • the MMI software 122 is able to send and receive commands to/from the GSM software 112 running on the first processor 110, via a radio interface layer (RIL) 124.
  • the RIL 124 converts commands passing between the two processors to/from a required format, and handles the sending and receiving of the commands.
  • an error manager 130 for implementing the method of the preferred embodiment of the present invention.
  • the error manager 130 is located in the command path between the first processor 110 and the second processor 120.
  • the error manager 130 is provided in the form of a software application running on the second processor, located 'below' the radio interface layer 124 in the command path to the first processor 110.
  • the error manager 130 is provided on or coupled to the second processor. In this manner, its operation is not halted during a re-start operation of the first processor. Furthermore, in this configuration, the error manager 130 is able to 'handle' any commands sent to the first processor from the second processor during the re-start operation of the first processor, in such a way as to keep the MMI software, etc., running smoothly.
  • the error manager 130 monitors commands passing between the first processor 110 and second processor 120, and identifies when a restart of the first processor 110 has taken place from the commands being sent from the first processor 110 to the second processor 120.
  • the error manager 130 intercepts the commands identifying the restart of the first processor 110, and prevents them from reaching the second processor. In this way, the second processor 120 is kept unaware that the first processor 110 has restarted.
  • the error manager 130 also filters out many of the error messages received from the first processor. For example, a number of error messages that may be sent by the GSM software in the first processor 110 are not serious and do not require the attention of the second processor or a reboot/re-start operation of the first processor.
  • AT commands it is meant commands defined in GSM standard 07:07 “AT command set for GSM Mobile Equipment (ME)”.
  • the error manager 130 intercepts the commands identifying a restart of the first processor 110.
  • the first processor system In order for the first processor system to be returned to a state expected by the second processor system, i.e. the state at which the first processor system was in prior to the restart of the first processor 110, it is necessary for the first processor 110 to be provided with the necessary initialisation and/or configuration commands. This is achieved by the error manager 130 retrieving the required initialisation and/or configuration commands from an area of memory 140, and providing them to the first processor 110.
  • the error manager 130 preferably obtains the required initialisation and/or configuration as described below. As well as monitoring the commands passing from the first processor 110 to the second processor 120, the error manager 130 also monitors commands passing from the second processor 120 to the first processor 110. In this regard, the error manager 130 identifies initialisation and configuration commands being sent to the first processor 110.
  • the error manager 130 stores in memory 140 any configuration and/or initialisation commands received, say from the second processor 120, before passing them on to the first processor 110.
  • the commands are stored in RAM, or another area of volatile memory that only retains information stored therein whilst power is provided thereto.
  • the error manager 130 is able to retrieve the various initialisation and/or configuration commands sent from the second processor 120 to the first processor 110 prior to the restart and resend them to the first processor 110.
  • the first processor system will be in substantially the same state as before the restart of the first processor 110, and thereby in a state expected by the second processor 120.
  • the error manager 130 blocks/buffers any commands from the second processor 120. It is envisaged that the error manager may provide a suitable response to the second processor 120. For example, in the case of the illustrated embodiment, if the second processor 120 sends a command to the first processor 110 requesting that a call be initiated, the error manager 130 blocks/buffers the command and returns a response such as 'No Service' . This allows the error manager to deceive the second processor 120 into thinking that the mobile communications device is unable to connect to the network.
  • the error manager 130 ceases blocking/buffering the commands sent from the second processor 120. If the commands were buffered, they are then forwarded to the first processor 110. The error manager 130 then resumes 'pass-through' mode, whereby it monitors the commands passing between the first processor and the second processor.
  • the commands received from the first processor 110 may also be substantially the first commands received from the first processor. Such commands would follow the switching on, or powering up, of the device in which the two processors are provided.
  • the error manager 130 is capable of differentiating between a re-start operation and a power 'on' operation.
  • the error manager 130 preferably passes on this initial restart command to the second processor 120, allowing the second processor 120 to initially configure the first processor 110 following the mobile communications device 100 being switched on. Then, any subsequent restart commands received from the first processor can be intercepted as described above.
  • the differentiation between the initial restart command from the first processor 110 may be achieved by the use of a flag located in an area of volatile memory, for example the same area of memory 140 in which the error manager 130 stores the initialisation and configuration commands received from the second processor 120. In this way, when the mobile communication device 100 is switched on, the volatile memory will be have been cleared, and the flag will be unset.
  • the first processor may advantageously be re-started using the (most) recent initialisation/ configuration settings.
  • the second processor is advantageously precluded from knowing about the first processor re-start operation.
  • the second processor will not attempt to re-start both processors, in order to align them both.
  • FIG. 2 illustrates a process 200 for the error manager to handle commands received from the second processor 120 in implementing a preferred method of the present invention.
  • step 210 when the error manager receives a command from the second processor.
  • step 220 the error manager determines whether it is operating in a pass-through mode, i.e. whether commands received from the second processor are to be passed on to the first processor.
  • the error manager is not in a pass-through mode in step 225, i.e. commands received from the second processor are not to be passed on to the first processor, the command is discarded, and the process ends.
  • the error manager may provide a response (not shown) to the second processor in order to fool the second processor into thinking that the command cannot be carried out for reasons other than because of the first processor restarting.
  • the error manager determines, in step 230 whether the command is an initialisation or configuration command. If the command is an initialisation or configuration command in step 235, the error manager stores the command in memory, in step 240, before forwarding it on to the first processor, in step 250. The process then ends. If the command is not an initialisation or configuration command, the error manager simply forwards it on to the first processor, without storing the command in memory, as shown in step 250. The process then ends.
  • the first processor may advantageously be re-started using these initialisation/ configuration settings.
  • FIG. 3 illustrates a preferred process for an error manager to determine a first processor re-start operation and initiate an initialisation/reconfiguration process in implementing a method of the preferred embodiment of the present invention.
  • step 310 when the error manager receives a command from the first processor.
  • step 320 the error manager determines whether the command indicates a restart operation of the first processor. Such a command may be in the form of the first processor requesting reconfiguration or initialisation following a restart or any other appropriate command/request . If the command does not indicate a restart of the first processor, the next step 330 is for the error manager to forward the command to the second processor 120. The process then ends.
  • next step 340 is for the error manager to exit from a pass-through mode. This prevents the error manager from forwarding commands from the second processor to the first processor.
  • the error manager retrieves the last stored initialisation/configuration command from memory.
  • the error manager sends the retrieved initialisation/configuration command to the first processor. Having sent the initialisation/configuration command to the first processor, the error manager then preferably waits, in step 370, for a response from the first processor stating that the first processor has received and executed the command.
  • the error manager does not receive such a command in step 375, it will preferably resend the command to the first processor. This may be carried out, for example, at the expiration of a specific time limit, or on receipt of an invalid response from the first processor.
  • the error manager 130 receives a valid response from the first processor, it checks in step 380 to see if all initialisation/configuration commands stored in memory have been sent to the first processor. If not all of the commands have been sent, in step 385, the error manager retrieves the next command stored in memory, in step 390, and repeats steps 360 to 380.
  • the next step 410 is for the error manager to send a command to the first processor indicating the end of the reconfiguration process. This instructs the first processor to resume normal operation.
  • step 420 the error manager resumes operating a pass-through mode, such that commands received from the second processor will be passed on to the first processor.
  • the reconfiguration process following a first processor re-start operation then ends.
  • the error manager may check a flag to see if it is set.
  • the error manager moves on to step 330, in FIG. 3 and forwards the command on to the second processor whilst preferably setting the flag.
  • the error manager moves on to step 340 in FIG.3, and exits from pass-through mode.
  • the method of handling a restart of a first processor in a dual-processor system and/or processor-controlled device including an error manager may be adapted and/or varied in any suitable way from the preferred embodiment herein described without narrowing the scope of the invention.
  • the specific features herein described are only by way of example in implementing the method, and should not be taken to be limitations.
  • a method of handling a restart of a first processor in a dual-processor system and a processor-controlled device including an error manager are provided that alleviate firstly the problem of reconfiguring the first processor following a restart, and secondly the problem of preventing the second processor from realising that the first processor has restarted and forcing a restart of both the first and second processors.

Abstract

L'invention concerne un procédé (300) de commande de redémarrage d'un premier processeur (110) dans un système biprocesseur, ce système comprenant un premier processeur (110) exécutant un premier ensemble de fonctions couplé fonctionnel à un second processeur (120) exécutant un second ensemble de fonctions. Le procédé comprend les étapes consistant à stocker (240) une ou plusieurs commandes d'initialisation et/ou de configuration dans un élément de mémoire, ces commandes étant envoyées par le second processeur (120) à un premier processeur (110) en vue de régler une fonction de ce premier processeur. Un message (310) provenant du premier processeur (110) indique une opération de réinitialisation du premier processeur, en réponse à laquelle une ou plusieurs commandes de démarrage ou de configuration sont extraites (350) de l'élément de mémoire (140). Le premier processeur (110) est ensuite redémarré avec, de préférence, les réglages de démarrage ou de configuration les plus récents de sorte que l'état de fonctionnement du premier processeur (110), après redémarrage, soit tel que prévu par le second processeur (120).
PCT/GB2003/002301 2002-05-27 2003-05-27 Commande de redemarrage de processeur WO2003100546A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003241016A AU2003241016A1 (en) 2002-05-27 2003-05-27 Processor re-start control

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GBGB0212143.2A GB0212143D0 (en) 2002-05-27 2002-05-27 Processor Monitor
GB0212143.2 2002-05-27
GB0214194.3 2002-06-19
GB0214194A GB2384333B (en) 2002-05-27 2002-06-19 Processor re-start control

Publications (2)

Publication Number Publication Date
WO2003100546A2 true WO2003100546A2 (fr) 2003-12-04
WO2003100546A3 WO2003100546A3 (fr) 2004-09-16

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WO (1) WO2003100546A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007081218A1 (fr) * 2006-01-10 2007-07-19 Cupp Computing As Système informatique double mode à économie d'énergie
US8615647B2 (en) 2008-02-29 2013-12-24 Intel Corporation Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3795800A (en) * 1972-09-13 1974-03-05 Honeywell Inf Systems Watchdog reload initializer
EP0397471A2 (fr) * 1989-05-09 1990-11-14 Fujitsu Limited Système et méthodes d'initialisation pour unités de traitement d' entrée/sortie
EP0421615A2 (fr) * 1989-10-03 1991-04-10 International Business Machines Corporation Méthode de traitement de données et appareil pour vérifier les choix dans une description de fichier d'un adapteur
US5748880A (en) * 1994-03-15 1998-05-05 Fujitsu Limited Computer-supervising system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3795800A (en) * 1972-09-13 1974-03-05 Honeywell Inf Systems Watchdog reload initializer
EP0397471A2 (fr) * 1989-05-09 1990-11-14 Fujitsu Limited Système et méthodes d'initialisation pour unités de traitement d' entrée/sortie
EP0421615A2 (fr) * 1989-10-03 1991-04-10 International Business Machines Corporation Méthode de traitement de données et appareil pour vérifier les choix dans une description de fichier d'un adapteur
US5748880A (en) * 1994-03-15 1998-05-05 Fujitsu Limited Computer-supervising system

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007081218A1 (fr) * 2006-01-10 2007-07-19 Cupp Computing As Système informatique double mode à économie d'énergie
US8065536B2 (en) 2006-01-10 2011-11-22 Cupp Computing As Dual mode power-saving computing system
US8615647B2 (en) 2008-02-29 2013-12-24 Intel Corporation Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state
US8930722B2 (en) 2008-02-29 2015-01-06 Intel Corporation Distribution of tasks among asymmetric processing elements
US9753530B2 (en) 2008-02-29 2017-09-05 Intel Corporation Distribution of tasks among asymmetric processing elements
US9760162B2 (en) 2008-02-29 2017-09-12 Intel Corporation Distribution of tasks among asymmetric processing elements
US9829965B2 (en) 2008-02-29 2017-11-28 Intel Corporation Distribution of tasks among asymmetric processing elements
US9870046B2 (en) 2008-02-29 2018-01-16 Intel Corporation Distribution of tasks among asymmetric processing elements
US9874926B2 (en) 2008-02-29 2018-01-23 Intel Corporation Distribution of tasks among asymmetric processing elements
US9910483B2 (en) 2008-02-29 2018-03-06 Intel Corporation Distribution of tasks among asymmetric processing elements
US9939882B2 (en) 2008-02-29 2018-04-10 Intel Corporation Systems and methods for migrating processes among asymmetrical processing cores
US10386915B2 (en) 2008-02-29 2019-08-20 Intel Corporation Distribution of tasks among asymmetric processing elements
US10409360B2 (en) 2008-02-29 2019-09-10 Intel Corporation Distribution of tasks among asymmetric processing elements
US10437320B2 (en) 2008-02-29 2019-10-08 Intel Corporation Distribution of tasks among asymmetric processing elements
US11054890B2 (en) 2008-02-29 2021-07-06 Intel Corporation Distribution of tasks among asymmetric processing elements
US11366511B2 (en) 2008-02-29 2022-06-21 Intel Corporation Distribution of tasks among asymmetric processing elements

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Publication number Publication date
AU2003241016A1 (en) 2003-12-12
AU2003241016A8 (en) 2003-12-12
WO2003100546A3 (fr) 2004-09-16

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