WO2003094208A3 - Method of isolating adjacent components of a semiconductor device - Google Patents

Method of isolating adjacent components of a semiconductor device Download PDF

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Publication number
WO2003094208A3
WO2003094208A3 PCT/GB2003/001863 GB0301863W WO03094208A3 WO 2003094208 A3 WO2003094208 A3 WO 2003094208A3 GB 0301863 W GB0301863 W GB 0301863W WO 03094208 A3 WO03094208 A3 WO 03094208A3
Authority
WO
WIPO (PCT)
Prior art keywords
strained silicon
layer
channel
semiconductor device
germanium
Prior art date
Application number
PCT/GB2003/001863
Other languages
French (fr)
Other versions
WO2003094208A2 (en
Inventor
Anthony Gerard O'neill
Original Assignee
Univ Newcastle
Anthony Gerard O'neill
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Newcastle, Anthony Gerard O'neill filed Critical Univ Newcastle
Priority to AU2003233867A priority Critical patent/AU2003233867A1/en
Publication of WO2003094208A2 publication Critical patent/WO2003094208A2/en
Publication of WO2003094208A3 publication Critical patent/WO2003094208A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Abstract

A method of isolating adjacent transistors in CMOS devices having strained silicon (12) and silicon germanium alloy (11) layers is disclosed. A semiconductor device combines in a single CMOS device the advantages of surface n-channel strained silicon MOSFETs with those of buried p-channel compressively strained silicon-germanium MOSFETs, without the need to compromise the performance of either type of transistor. By forming electrically insulating barrier regions (8) before formation of the strained silicon layer (12), this avoids the problem of high temperature processing steps causing germanium to diffuse from layer (11) into the channels of transistors in layer (12) and thereby degrading the performance of the n-channel transistors formed by the method.
PCT/GB2003/001863 2002-04-29 2003-04-28 Method of isolating adjacent components of a semiconductor device WO2003094208A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003233867A AU2003233867A1 (en) 2002-04-29 2003-04-28 Method of isolating adjacent components of a semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0209737A GB0209737D0 (en) 2002-04-29 2002-04-29 Method of isolating adjacent components of a semiconductor device
GB0209737.6 2002-04-29

Publications (2)

Publication Number Publication Date
WO2003094208A2 WO2003094208A2 (en) 2003-11-13
WO2003094208A3 true WO2003094208A3 (en) 2004-02-26

Family

ID=9935691

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2003/001863 WO2003094208A2 (en) 2002-04-29 2003-04-28 Method of isolating adjacent components of a semiconductor device

Country Status (3)

Country Link
AU (1) AU2003233867A1 (en)
GB (1) GB0209737D0 (en)
WO (1) WO2003094208A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7462549B2 (en) * 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
US8957476B2 (en) * 2012-12-20 2015-02-17 Intel Corporation Conversion of thin transistor elements from silicon to silicon germanium
GB2549911A (en) * 2013-06-26 2017-11-01 Intel Corp Conversion of thin transistor elements from silicon to silicon germanium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212110A (en) * 1992-05-26 1993-05-18 Motorola, Inc. Method for forming isolation regions in a semiconductor device
US5371035A (en) * 1993-02-01 1994-12-06 Motorola Inc. Method for forming electrical isolation in an integrated circuit device
US6249031B1 (en) * 1998-02-09 2001-06-19 Chartered Semiconductor Manufacturing Ltd. High gain lateral PNP and NPN bipolar transistor and process compatible with CMOS for making BiCMOS circuits
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212110A (en) * 1992-05-26 1993-05-18 Motorola, Inc. Method for forming isolation regions in a semiconductor device
US5371035A (en) * 1993-02-01 1994-12-06 Motorola Inc. Method for forming electrical isolation in an integrated circuit device
US6249031B1 (en) * 1998-02-09 2001-06-19 Chartered Semiconductor Manufacturing Ltd. High gain lateral PNP and NPN bipolar transistor and process compatible with CMOS for making BiCMOS circuits
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TAKAGI S ET AL: "Device structure and electrical characteristics of strained-Si-on-insulator (strained-SOI) MOSFETs", E-MRS 2001 SPRING MEETING, SYMPOSIUM D: SECOND INTERNATIONAL CONFERENCE ON SILICON EPITAXY AND HETEROSTRUCTURES, STRASBOURG, FRANCE, 4-8 JUNE 2001, vol. B89, no. 1-3, Materials Science & Engineering B (Solid-State Materials for Advanced Technology), 14 Feb. 2002, Elsevier, Switzerland, pages 426 - 434, XP002262654, ISSN: 0921-5107 *

Also Published As

Publication number Publication date
WO2003094208A2 (en) 2003-11-13
GB0209737D0 (en) 2002-06-05
AU2003233867A1 (en) 2003-11-17
AU2003233867A8 (en) 2003-11-17

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