AU2003233867A1 - Method of isolating adjacent components of a semiconductor device - Google Patents

Method of isolating adjacent components of a semiconductor device

Info

Publication number
AU2003233867A1
AU2003233867A1 AU2003233867A AU2003233867A AU2003233867A1 AU 2003233867 A1 AU2003233867 A1 AU 2003233867A1 AU 2003233867 A AU2003233867 A AU 2003233867A AU 2003233867 A AU2003233867 A AU 2003233867A AU 2003233867 A1 AU2003233867 A1 AU 2003233867A1
Authority
AU
Australia
Prior art keywords
semiconductor device
adjacent components
isolating adjacent
isolating
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003233867A
Other versions
AU2003233867A8 (en
Inventor
Anthony Gerard O'Neill
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Newcastle University of Upon Tyne
Original Assignee
University of Newcastle, The
Newcastle University of Upon Tyne
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Newcastle, The, Newcastle University of Upon Tyne filed Critical University of Newcastle, The
Publication of AU2003233867A8 publication Critical patent/AU2003233867A8/en
Publication of AU2003233867A1 publication Critical patent/AU2003233867A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
AU2003233867A 2002-04-29 2003-04-28 Method of isolating adjacent components of a semiconductor device Abandoned AU2003233867A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0209737.6 2002-04-29
GB0209737A GB0209737D0 (en) 2002-04-29 2002-04-29 Method of isolating adjacent components of a semiconductor device
PCT/GB2003/001863 WO2003094208A2 (en) 2002-04-29 2003-04-28 Method of isolating adjacent components of a semiconductor device

Publications (2)

Publication Number Publication Date
AU2003233867A8 AU2003233867A8 (en) 2003-11-17
AU2003233867A1 true AU2003233867A1 (en) 2003-11-17

Family

ID=9935691

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003233867A Abandoned AU2003233867A1 (en) 2002-04-29 2003-04-28 Method of isolating adjacent components of a semiconductor device

Country Status (3)

Country Link
AU (1) AU2003233867A1 (en)
GB (1) GB0209737D0 (en)
WO (1) WO2003094208A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7462549B2 (en) 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
US8957476B2 (en) * 2012-12-20 2015-02-17 Intel Corporation Conversion of thin transistor elements from silicon to silicon germanium
GB2549911A (en) * 2013-06-26 2017-11-01 Intel Corp Conversion of thin transistor elements from silicon to silicon germanium

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212110A (en) * 1992-05-26 1993-05-18 Motorola, Inc. Method for forming isolation regions in a semiconductor device
US5371035A (en) * 1993-02-01 1994-12-06 Motorola Inc. Method for forming electrical isolation in an integrated circuit device
US6093613A (en) * 1998-02-09 2000-07-25 Chartered Semiconductor Manufacturing, Ltd Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth

Also Published As

Publication number Publication date
WO2003094208A3 (en) 2004-02-26
WO2003094208A2 (en) 2003-11-13
AU2003233867A8 (en) 2003-11-17
GB0209737D0 (en) 2002-06-05

Similar Documents

Publication Publication Date Title
EP1416529B8 (en) Manufacturing method of semiconductor device
EP1350588A3 (en) Method of manufacturing semiconductor device
AU2003275614A1 (en) Semiconductor device and method for manufacturing semiconductor device
AU2003275615A1 (en) Semiconductor device and method for manufacturing semiconductor device
EP1579497A3 (en) Method for forming a semiconductor device and structure thereof
AU2003303012A1 (en) Method of manufacturing a trench-gate semiconductor device
AU2003261078A1 (en) A semiconductor device and method of fabricating a semiconductor device
AU2002320060A1 (en) Method for isolating semiconductor devices
AU2002307578A1 (en) A method of wafer/substrate bonding
AU2003212931A1 (en) Semiconductor device and method of isolating circuit regions
AU2002348835A1 (en) Method of manufacturing a semiconductor device
GB0425941D0 (en) Method for increasing efficiency of thermotunnel devices
AU2003286625A1 (en) Method of forming semiconductor devices through epitaxy
AU2003244352A1 (en) Method of producing organic semiconductor device
AU2003257063A1 (en) Semiconductor device and method for forming
AU2003281009A1 (en) Organic semiconductor device and method for manufacturing same
EP1566830A4 (en) Method for manufacturing soi wafer
AU2003297117A1 (en) Method of fabrication of a support structure for a semiconductor device
AU2003291315A1 (en) Split manufacturing method for semiconductor circuits
AU2003214524A1 (en) Method of manufacturing an electronic device
AU2003301120A1 (en) Method for passivating semiconductor devices
AU2002348636A1 (en) Method for ashing
AU2003262125A1 (en) Improved method for etching vias
TWI309074B (en) Method of forming semiconductor device
AU2003227223A1 (en) Method of etching

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase