WO2003090361A1 - A memory management algorithm for trellis decoders - Google Patents
A memory management algorithm for trellis decoders Download PDFInfo
- Publication number
- WO2003090361A1 WO2003090361A1 PCT/US2003/007166 US0307166W WO03090361A1 WO 2003090361 A1 WO2003090361 A1 WO 2003090361A1 US 0307166 W US0307166 W US 0307166W WO 03090361 A1 WO03090361 A1 WO 03090361A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- trellis
- pointer
- epoch
- data
- path
- Prior art date
Links
- 238000012545 processing Methods 0.000 claims abstract description 18
- 230000007704 transition Effects 0.000 claims 9
- 230000004044 response Effects 0.000 claims 7
- 239000002131 composite material Substances 0.000 claims 4
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 28
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000013459 approach Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 230000002860 competitive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3944—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes for block codes, especially trellis or lattice decoding thereof
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3961—Arrangements of methods for branch or transition metric calculation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
- H03M13/6505—Memory efficient implementations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
- H04N21/2383—Channel coding or modulation of digital bit-stream, e.g. QPSK modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
- H04N21/4382—Demodulation or channel decoding, e.g. QPSK demodulation
Definitions
- the forward trace will process data up to data D3 (data in epoch 3) in order to permit decoding of the data associated with D1 , the decoded data being data DD1 (decoded data from epoch 1), which will occur during epoch 4. Therefore, three epochs are fully processed (epochs 2 and 3 by the forward trace and epoch 1 by the traceback) before the first epoch decoded data DD1 is generated as an output signal.
- the device is attributable to a one epoch delay (T/2 samples) in the buffer memory, plus a two epoch delay (T samples) in the decoded sequence memory.
- the total latency is thus a three epoch delay, or 3/2 * T samples.
- Figure 2 is a timing diagram of a prior art APTFT system depicted in Figure 1 ;
- the forward trace pointer, P points to the minimum trellis path and provides the trellis state associated with the minimum path existing q epochs earlier, rather than two epochs earlier.
- the generalized design requires q internal pointers per trellis state in the forward trace, rather than two internal pointers, offset in time by intervals of one epoch.
- each internal pointer P1 , P2, ...Pq points to the beginning state of the corresponding epoch and trellis state path, and all internal pointers contribute to create the main pointer P.
- the forward trace pointer, P points to the minimum path and provides the trellis state associated with the minimum path existing q - 1 epochs earlier, rather than one epoch earlier.
- the generalized design requires q internal pointers per trellis state in the forward trace unit, rather than two internal pointers, offset in time by intervals of one epoch.
- each internal pointer P1 , P2, ...Pq points to the beginning state of the corresponding epoch and state path, and all internal pointers contribute to create the main pointer P. All internal pointers except P1 are updated only at the end of an epoch, and their value remains unchanged during the following epoch. Pointer P1 is reset at the beginning of each epoch and is continuously updated throughout the forward trace.
- the memory size will consist of T/q * N in the buffer memory plus (q - 1)/q * T * N in the decoded sequence memory, corresponding to a total memory size of T * N.
- the generalized improved APTFT algorithm needs a total of (q + 1) * N + 1 state pointers (N in the traceback unit and q * N + 1 in the forward trace unit).
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Multimedia (AREA)
- Artificial Intelligence (AREA)
- Error Detection And Correction (AREA)
Abstract
Description
Claims
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003218034A AU2003218034A1 (en) | 2002-04-17 | 2003-03-10 | A memory management algorithm for trellis decoders |
US10/511,655 US7149952B2 (en) | 2002-04-17 | 2003-03-10 | Memory management algorithm for trellis decoders |
JP2003587013A JP4191053B2 (en) | 2002-04-17 | 2003-03-10 | Memory management algorithm for trellis decoder |
EP03714015A EP1495547A4 (en) | 2002-04-17 | 2003-03-10 | A memory management algorithm for trellis decoders |
KR1020047016609A KR101010784B1 (en) | 2002-04-17 | 2003-03-10 | A memory management algorithm for trellis decoders |
CN038086786A CN1647391B (en) | 2002-04-17 | 2003-03-10 | Equipment and method for providing grid decoding data |
MXPA04010142A MXPA04010142A (en) | 2002-04-17 | 2003-03-10 | A memory management algorithm for trellis decoders. |
BR0309218-6A BR0309218A (en) | 2002-04-17 | 2003-03-10 | Memory Management Algorithm for Truss Decoders |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US37324602P | 2002-04-17 | 2002-04-17 | |
US60/373,246 | 2002-04-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003090361A1 true WO2003090361A1 (en) | 2003-10-30 |
Family
ID=29251004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/007166 WO2003090361A1 (en) | 2002-04-17 | 2003-03-10 | A memory management algorithm for trellis decoders |
Country Status (9)
Country | Link |
---|---|
US (1) | US7149952B2 (en) |
EP (1) | EP1495547A4 (en) |
JP (1) | JP4191053B2 (en) |
KR (1) | KR101010784B1 (en) |
CN (1) | CN1647391B (en) |
AU (1) | AU2003218034A1 (en) |
BR (1) | BR0309218A (en) |
MX (1) | MXPA04010142A (en) |
WO (1) | WO2003090361A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8140947B2 (en) * | 2005-09-30 | 2012-03-20 | Agere Systems Inc. | Method and apparatus for storing survivor paths in a Viterbi detector using systematic pointer exchange |
US20080123210A1 (en) * | 2006-11-06 | 2008-05-29 | Wei Zeng | Handling synchronization errors potentially experienced by a storage device |
KR100864722B1 (en) * | 2006-12-04 | 2008-10-23 | 삼성전자주식회사 | Trellis encoder and trellis encoding device comprising the trellis encoder |
US8433004B2 (en) | 2010-02-26 | 2013-04-30 | Research In Motion Limited | Low-latency viterbi survivor memory architecture and method using register exchange, trace-back, and trace-forward |
US8402342B2 (en) * | 2010-02-26 | 2013-03-19 | Research In Motion Limited | Method and system for cyclic redundancy check |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5841478A (en) * | 1996-04-09 | 1998-11-24 | Thomson Multimedia, S.A. | Code sequence detection in a trellis decoder |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3789360A (en) * | 1972-10-13 | 1974-01-29 | Harris Intertype Corp | Convolutional decoder |
KR0135796B1 (en) * | 1994-11-14 | 1998-04-27 | 김광호 | Traceback processing apparatus in viterbi decorder |
CN1136731A (en) * | 1995-05-16 | 1996-11-27 | 林茂昭 | Multi-layer net coding system |
JP3280834B2 (en) * | 1995-09-04 | 2002-05-13 | 沖電気工業株式会社 | Signal judging device and receiving device in coded communication system, signal judging method, and channel state estimating method |
KR970063964A (en) * | 1996-02-28 | 1997-09-12 | 김광호 | A survival memory management method for a Viterbi decoder and a survival memory device therefor |
US6094739A (en) * | 1997-09-24 | 2000-07-25 | Lucent Technologies, Inc. | Trellis decoder for real-time video rate decoding and de-interleaving |
KR100237490B1 (en) * | 1997-11-29 | 2000-01-15 | 전주범 | An apparatus for tracebacking survivor path of trellis code data |
US6775334B1 (en) * | 1998-11-03 | 2004-08-10 | Broadcom Corporation | Equalization and decision-directed loops with trellis demodulation in high definition TV |
ATE259999T1 (en) * | 1999-08-31 | 2004-03-15 | Broadcom Corp | MEMORY EXECUTION OF REGISTER-EXCHANGE TRACEBACK FOR GIGABIT ETHERNET TRANSMITTER-RECEIVER |
EP1091579B1 (en) * | 1999-09-07 | 2006-02-15 | Thomson Licensing | Trellis demapper for Trellis decoder |
US6560749B1 (en) * | 2000-01-28 | 2003-05-06 | Nec Electronics, Inc. | Apparatus and method for implementing a decoder for convolutionally encoded symbols |
MXPA04010139A (en) * | 2002-04-16 | 2005-06-08 | Thomson Licensing Sa | Hdtv trellis decoder architecture. |
-
2003
- 2003-03-10 WO PCT/US2003/007166 patent/WO2003090361A1/en active Application Filing
- 2003-03-10 BR BR0309218-6A patent/BR0309218A/en not_active IP Right Cessation
- 2003-03-10 AU AU2003218034A patent/AU2003218034A1/en not_active Abandoned
- 2003-03-10 CN CN038086786A patent/CN1647391B/en not_active Expired - Lifetime
- 2003-03-10 EP EP03714015A patent/EP1495547A4/en not_active Ceased
- 2003-03-10 JP JP2003587013A patent/JP4191053B2/en not_active Expired - Lifetime
- 2003-03-10 MX MXPA04010142A patent/MXPA04010142A/en active IP Right Grant
- 2003-03-10 US US10/511,655 patent/US7149952B2/en not_active Expired - Lifetime
- 2003-03-10 KR KR1020047016609A patent/KR101010784B1/en active IP Right Grant
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5841478A (en) * | 1996-04-09 | 1998-11-24 | Thomson Multimedia, S.A. | Code sequence detection in a trellis decoder |
Non-Patent Citations (3)
Title |
---|
HU ET AL.: "A viterbi decoder memory management system using forward traceback and all-path traceback", INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, 1999. ICCE, 24 June 1999 (1999-06-24), pages 68 - 69, XP010346540 * |
MONTSE BOO ET AL.: "High-Performance VLSI Architecture for the Viterby Algorithm", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 45, no. 2, February 1997 (1997-02-01), pages 168 - 176 |
See also references of EP1495547A4 |
Also Published As
Publication number | Publication date |
---|---|
US20050257123A1 (en) | 2005-11-17 |
EP1495547A1 (en) | 2005-01-12 |
BR0309218A (en) | 2005-02-09 |
CN1647391A (en) | 2005-07-27 |
KR101010784B1 (en) | 2011-01-25 |
EP1495547A4 (en) | 2006-11-08 |
KR20040099452A (en) | 2004-11-26 |
JP2006511977A (en) | 2006-04-06 |
AU2003218034A1 (en) | 2003-11-03 |
MXPA04010142A (en) | 2005-01-25 |
US7149952B2 (en) | 2006-12-12 |
JP4191053B2 (en) | 2008-12-03 |
CN1647391B (en) | 2011-05-11 |
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