WO2003090355A3 - Integrated circuit with clock signal duty cycle control - Google Patents

Integrated circuit with clock signal duty cycle control Download PDF

Info

Publication number
WO2003090355A3
WO2003090355A3 PCT/IB2003/001268 IB0301268W WO03090355A3 WO 2003090355 A3 WO2003090355 A3 WO 2003090355A3 IB 0301268 W IB0301268 W IB 0301268W WO 03090355 A3 WO03090355 A3 WO 03090355A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock
duty cycle
distribution network
clock signal
integrated circuit
Prior art date
Application number
PCT/IB2003/001268
Other languages
French (fr)
Other versions
WO2003090355A2 (en
Inventor
Kiran B R Rao
Manish Garg
Hendricus J M Veendrick
Original Assignee
Koninkl Philips Electronics Nv
Kiran B R Rao
Manish Garg
Hendricus J M Veendrick
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Kiran B R Rao, Manish Garg, Hendricus J M Veendrick filed Critical Koninkl Philips Electronics Nv
Priority to AU2003215863A priority Critical patent/AU2003215863A1/en
Publication of WO2003090355A2 publication Critical patent/WO2003090355A2/en
Publication of WO2003090355A3 publication Critical patent/WO2003090355A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)

Abstract

An integrated circuit (100) has a clock signal distribution network (140) for distributing a parent clock pulse signal that is provided through a conductor (102). At the inputs, the clock distribution network (140) is coupled to a clock signal modifying circuit (120) and on the outputs the clock distribution network (140) is coupled to a reference generating circuit (160). The reference generating circuit (160) is arranged to provide the clock signal modifying circuit (120) with a direct current voltage that is proportional to the duty cycle of the clock pulse signal that is distributed through the clock distribution network (140). The clock signal modifying circuit (120) is arranged to alter the duty cycle of the incoming parent clock pulse signal responsive to the direct current voltage. The arrangement implements a feedback mechanism for reducing deviations from a 50% duty cycle of a clock pulse signal distributed through the clock distribution network (140).
PCT/IB2003/001268 2002-04-22 2003-04-01 Integrated circuit with clock signal duty cycle control WO2003090355A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003215863A AU2003215863A1 (en) 2002-04-22 2003-04-01 Integrated circuit with clock signal duty cycle control

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02076557.4 2002-04-22
EP02076557 2002-04-22

Publications (2)

Publication Number Publication Date
WO2003090355A2 WO2003090355A2 (en) 2003-10-30
WO2003090355A3 true WO2003090355A3 (en) 2004-04-08

Family

ID=29225694

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/001268 WO2003090355A2 (en) 2002-04-22 2003-04-01 Integrated circuit with clock signal duty cycle control

Country Status (3)

Country Link
AU (1) AU2003215863A1 (en)
TW (1) TW200401506A (en)
WO (1) WO2003090355A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005028173B4 (en) * 2005-06-17 2007-03-08 Texas Instruments Deutschland Gmbh Integrated CMOS duty cycle correction circuit for a clock signal
US20100066450A1 (en) * 2007-02-12 2010-03-18 Rambus Inc. High-Speed Low-Power Differential Receiver
US8519763B2 (en) * 2010-06-11 2013-08-27 Altera Corporation Integrated circuits with dual-edge clocking
CN113484565B (en) * 2021-07-14 2024-02-13 国网新疆电力有限公司电力科学研究院 DC signal generating device for calibrating low-frequency AC signal and calibration method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6320438B1 (en) * 2000-08-17 2001-11-20 Pericom Semiconductor Corp. Duty-cycle correction driver with dual-filter feedback loop

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6320438B1 (en) * 2000-08-17 2001-11-20 Pericom Semiconductor Corp. Duty-cycle correction driver with dual-filter feedback loop

Also Published As

Publication number Publication date
AU2003215863A8 (en) 2003-11-03
TW200401506A (en) 2004-01-16
AU2003215863A1 (en) 2003-11-03
WO2003090355A2 (en) 2003-10-30

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