WO2003084059A1

WO2003084059A1 - Semiconductor integrated circuit

Info

Publication number: WO2003084059A1
Application number: PCT/JP2003/003343
Authority: WO
Inventors: Tatsuo Tsujita
Original assignee: Thine Electronics, Inc.
Priority date: 2002-03-28
Filing date: 2003-03-19
Publication date: 2003-10-09
Also published as: JPWO2003084059A1

Abstract

A semiconductor integrated circuit including an amplifier circuit inserted in a stage preceding an image ADC, wherein the frequency band or amplification factor of the amplifier circuit can be changed without additionally providing any passive elements, such as resistors, capacitors and the like, and wherein when the frequency band is narrowed, the power consumption of the amplifier circuit is reduced. This semiconductor integrated circuit includes a plurality of amplifiers (A1-AN) with their input and output terminals connected in parallel, and also includes selector circuits (SW1-SWN) for activating selected ones of the amplifiers in accordance with control signals.

Description

Description Semiconductor integrated circuit technology

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor integrated circuit including an analog amplifier circuit, and more particularly to an image placed before an image ADC (Analog to Digital Converter) for converting an analog image signal into a digital image signal. The present invention relates to a semiconductor integrated circuit including an amplifier circuit. Background art

In general, an amplifier circuit with a variable amplification factor is inserted before the image ADC that converts an analog image signal into a digital image signal so that the level of the analog image signal is optimized for ADC. Adjustments are being made.

In addition, when converting an analog signal to a digital signal, if an analog signal having a frequency higher than half the sampling frequency is input to the ADC, aliasing noise is generated. Therefore, it is necessary to insert an LPF (low-pass filter) before ADC in order to remove unnecessary high-frequency components from the analog signal. However, as analog image signals, UXG A (resolution: 1,600 lines x 1,200 lines) and QXGA (resolution: 2,048 lines) from narrow frequency band signals such as NTSC television signals XI 5 3 6). In order to cope with such analog image signals having different frequency bands, the cutoff frequency of LPF must be made variable.

From the above, an amplifier circuit with a variable amplification factor is placed before the image ADC. And an LPF with a variable cutoff frequency is inserted ₍ or an amplifier circuit with a variable frequency band and variable amplification factor is used).

First, an example of a conventional amplification circuit that operates as an LPF whose cutoff frequency is variable will be described.

FIGS. 4A and 4B are circuit diagrams showing a single-stage differential amplifier circuit using CMOS transistors. This differential amplifier circuit is configured by using a differential pair of P-channel transistors, as shown in FIG. 4A. Figure 4B shows this symbolized. Here, the transconductance g _m of the P-channel transistors forming the differential pair. Is expressed by the following equation using a constant K _P.

In order to realize an amplifier circuit with a variable frequency band using this differential amplifier circuit, as shown in Fig. 5, the series resistance R or the load capacitance CL is made variable, or as shown in Fig. 4A. a bias current I _B Ru it is considered to be variable.

However, when the series resistance R or the load capacitance CL is made variable, it is necessary to add a passive element that occupies a relatively large area in the semiconductor integrated circuit, and there is a problem that the chip area increases. Further, even if the values of the series resistance R and the load capacitance CL are increased in order to narrow the frequency band, the current consumed in the amplifier circuit cannot be reduced.

- How, bias current I when the variable a _B, transconductance decrease the bias current I _B to narrow to order the frequency band g _m. And Reduces the, it is possible to reduce the current consumed in the amplifier circuit, however, when the bias current I _B in the variable, the current value flowing constantly in the individual transistors changes, amplifier circuit operates best Electric The pressure range changes greatly.

Next, an example of a conventional amplifier circuit in which the frequency band and the amplification factor are variable will be described.

6A and 6B are circuit diagrams showing a two-stage amplification circuit using CMOS transistors. As shown in FIG. 6A, in this amplifier circuit, the first stage is a differential amplifier circuit, and the second stage is a common-source amplifier circuit. Figure 6B shows this symbolized. The frequency band of this amplifier circuit is g _m , using the capacitance C _c for phase compensation. It is represented by Ri by the ZC _c.

FIG. 7 shows an example in which the two-stage amplifier circuit shown in FIGS. 6A and 6B is used to configure an amplifier circuit having a variable cutoff frequency and amplification factor. As shown in FIG. 7, an arbitrary gain can be obtained by adding the resistors R11 and R12 as a negative feedback circuit. The series resistance R and load capacitance CJ make up a CR-type LPF. By varying the series resistance R or the load capacitance C to vary the cutoff frequency of the LPF, the frequency band of the wide circuit can be changed. Alternatively, such as by the bias current I _B to the variable may be changed frequency band of the amplifier circuit.

However, also in the amplifier circuit shown in FIG. 7, when the series resistance R and the load capacitance _CL are made variable, it is necessary to add a passive element, and the chip area increases. Even if the values of the series resistance R and the load capacitance C ^ are increased to narrow the frequency band, the current consumed in the amplifier circuit cannot be reduced.

Meanwhile, mutual reduces the bias current I _B in order to narrow the frequency band conductance g _m. When the value is reduced, the current consumed in the wide circuit can be reduced. However, bias current I _B If this is changed, the current value that constantly flows through each transistor changes, and the voltage range in which the amplifier circuit operates optimally changes greatly. Disclosure of the invention

In view of the above, the present invention provides a semiconductor integrated circuit including an amplifier circuit inserted in a stage preceding an image ADC, without adding a passive element such as a resistor / capacitor. The purpose is to make the rate variable and to reduce the power consumption of the amplifier circuit when narrowing the frequency band.

In order to solve the above problems, a semiconductor integrated circuit according to a first embodiment of the present invention includes a plurality of amplifier circuits whose inputs and outputs are connected in parallel, and a plurality of amplifier circuits based on a control signal. And a selection circuit for activating the selected amplification circuit.

Further, the semiconductor integrated circuit according to the second embodiment of the present invention includes a plurality of first amplifier circuits whose inputs and outputs are connected in parallel, and a second amplifier which amplifies output signals of the plurality of first amplifier circuits. And a selection circuit that activates an amplification circuit selected from the plurality of first amplification circuits according to a control signal. According to the present invention, a plurality of differential amplifier circuits are arranged in parallel, and the bias supplied to each differential amplifier circuit is switched by the selection circuit, so that a passive element such as a resistance capacitor is not added. The frequency band or the amplification factor of the amplifier circuit can be made variable. Further, when the frequency band is narrowed, the power consumed in the amplifier circuit can be reduced. BRIEF DESCRIPTION OF THE FIGURES

Advantages and features of the present invention will become apparent from consideration of the following detailed description and drawings. In these drawings, the same reference numbers have the same structure. Refers to components.

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of the variable resistor shown in FIG.

FIGS. 4A and 4B are circuit diagrams showing a single-stage differential amplifier circuit using CMOS transistors.

FIG. 5 is a circuit diagram showing a conventional amplifier circuit whose frequency band is variable. FIGS. 6A and 6B are circuit diagrams showing a two-stage amplification circuit using CMOS transistors.

FIG. 7 is a circuit diagram showing a conventional amplifier circuit in which a frequency band and a bandwidth ratio are variable. BEST MODE FOR CARRYING OUT THE INVENTION

First, a first embodiment of the present invention will be described.

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. The frequency band of the amplifier circuit included in the semiconductor integrated circuit is variable.

As shown in FIG. 1, the semiconductor integrated circuit includes a variable band amplifier circuit 1, a load capacitance ^, a control circuit 2, and an image ADC 3. The variable band amplifier circuit 1 is composed of a plurality (N) of differential amplifier circuits A 1, A 2,..., AN connected in parallel, and these differential amplifier circuits A 1, A 2, ..., and a plurality of switches SW 1, SW2, which are connected to the aN, ..., and SWN, and load capacity flicking, and a bias voltage source for generating a bias potential V _B. The bias voltage source is the differential amplifier circuit A1, A2, ..., A Supply bias potential V _B to selected ones of N. Here, the load capacitance C doctor is mainly a differential amplifier circuit A l, A 2, ·· ' , a sum of the output capacity of the AN, the load capacitance C ₂ is connected to the output of the variable bandpass amplifier 1 This is the sum of the input capacitance and wiring capacitance of the circuit to be used.

The switches SW 1, SW 2,..., SWN are connected to the bias potential V _B generated by the bias voltage source and the ground potential in accordance with the control signals C l, C 2,. Is connected to each differential width circuit. As a result, a selected one of the differential width circuits A 1, A 2,..., AN is activated. Current output from the activated differential amplifier circuit are added, _c output voltage Output voltage at the output of the variable bandpass amplifier 1 is generated, is input to the image for AD C 3.

In the variable bandpass amplifier 1, N pieces of differential amplifier A 1, A 2, · · ·, when the number of differential amplifier circuits operating within the AN and i pieces, the mutual conductance g _m Is represented by the following equation.

g _m = g _m0 (i ZN)

Where g _m . Represents the transconductance of the entire differential amplifier circuit when all the differential amplifier circuits are operating.

As described above, when the transconductance g _m of the variable bandwidth / width circuit 1 changes, the frequency band determined by the transconductance g _m and the load capacitance CL i + CL ₂ changes. Its frequency band is proportional to g _m / ( _{CL 1} + _{CL 2} ). On the other hand, the gain is almost constant because negative feedback is applied to each differential amplifier circuit.

Here, since the bias potential V _B is set so that a bias current suitable for each transistor of the differential amplifier circuits A 1, A 2,..., AN flows, the switches SW 1, SW 2,. · Even if the bias current is switched on or off by SWN, the operating differential amplifier circuit always Operated by bias current. Also, the operating differential amplifier circuit is not affected by the non-operational differential amplifier circuit. Furthermore, since the current consumed in each of the differential amplifier circuits A1, A2,..., AN is proportional to the frequency band, when the frequency band of the differential amplifier circuit is narrowed, the current consumption is reduced. Reduced. In addition, since it is not necessary to add a passive element occupying a large area on the semiconductor integrated circuit such as a resistor and a capacitor to make the frequency band variable, the chip area can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. The amplifier circuit included in the semiconductor integrated circuit according to the present embodiment has a variable frequency band and a wide bandwidth ratio.

As shown in FIG. 2, the semiconductor integrated circuit includes a variable amplification factor variable band amplification circuit 4, a control circuit 2, and an image ADC 3. Variable amplification factor The variable band amplification circuit 4 includes a plurality (N) of differential amplification circuits A1, A2,..., AN connected in parallel, and these differential amplification circuits A1, A2,.増幅 Amplifies the output signals of the multiple switches SW1, SW2, ..., SWN connected to AN, 2,-', and AN, and the differential amplifier circuits A1, A2, ..., AN And a common-source amplifier circuit B 1.

The variable增幅rate variable bandwidth amplifier circuit 4 includes a variable resistor R 1及Pi R 2 to form a negative feedback circuit, and a bias voltage source for generating a bias potential V _B. The variable resistor can be composed of, for example, a plurality of resistors R _A , R _B , R _c and a plurality of switches SW _B , SW _{C as shown} in FIG. That is, the total resistance value is changed by switching the number of resistors connected in parallel with the switch. Referring again to FIG. 2, the bias voltage source supplies the bias potential V _B to a selected one of the differential amplifier circuits A 1, A 2,. B 1 Supplying a bias potential V _B.

As in the first embodiment, the switches SW1, SW2,..., SWN are connected to a bias voltage source according to control signals C1, C2,. There connecting one of the bias potential V _B and the ground potential generated in each of the differential amplifier circuit. As a result, a selected one of the differential amplifier circuits A1, A2,..., AN is activated. The current output from the activated differential amplifier circuit is added, and an output voltage is generated. This output voltage is input to the common source amplifier circuit B1.

In the variable amplification factor variable band amplifier circuit 4, assuming that the number of operating differential amplifier circuits among the N differential amplifier circuits A1, A2,..., AN is i, the mutual conductance g _m is given by the following equation.

gm = gm O (i) g _ml

Where g _m . Represents the transconductance of the entire differential amplifier circuit when all the differential amplifier circuits are operating, and g _ml represents the transconductance of the common-source amplifier circuit.

The good sea urchin, the transconductance g _m of the variable amplification factor variable bandwidth amplifier circuit 4 is changed, so that the frequency band is determined by the capacitance C _c of the transconductance g _m and the phase compensation capacitor is changed. On the other hand, the amplification factor is determined by the values of the variable resistors R1 and R2 of the negative feedback circuit. These values are controlled by the control circuit 2.

As shown in Fig. 2, when elements that flow current such as variable resistors R1 and R2 are connected as output loads, the band setting is applied to the common-source amplifier B1 in the output stage. always giving a constant bias potential V _B regardless, bias conditions output stage should not vary. Here, the mutual conductance g _ml of the output stage hardly affects the product of the frequency band and the gain (gain / bandwidth product). On the other hand, as in the first embodiment, If the output load is only a capacitive load, the common-source amplifier circuit B1 can be omitted and the outputs of the differential amplifier circuits A1, A2,..., AN can be connected to the capacitive load.

As described above, according to the present invention, the frequency band or the amplification factor of the amplifier circuit can be made variable without adding a passive element such as a resistor or a capacitor. As a result, it is possible to suppress an increase in the chip area and to increase the degree of integration of the semiconductor integrated circuit. Further, when the frequency band is narrowed, the power consumed in the amplifier circuit can be reduced. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention can be used in an image device or a computer that transmits image data and audio data.

Claims

The scope of the claims

1. A plurality of amplifier circuits (A1 to AN) whose input and output are connected in parallel, and a selected width circuit of the plurality of amplifier circuits (A1 to AN) is activated according to a control signal. Selection circuits (SW1 to SWN),

A semiconductor integrated circuit comprising:

2. The semiconductor integrated circuit according to claim 1, wherein each of the plurality of amplifier circuits (A1 to AN) is a differential amplifier to which negative feedback is applied.

3. The semiconductor integrated circuit according to claim 1, further comprising a control circuit (2) for controlling the selection circuits (SW1 to SWN).

4. The semiconductor integrated circuit according to claim 1, further comprising an analog / digital conversion circuit (3) to which output signals of the plurality of amplifier circuits are supplied.

5. A plurality of first amplifier circuits (A 1 to AN) whose inputs and outputs are connected in parallel, and a second amplifier circuit for amplifying output signals of the plurality of first amplifier circuits (A 1 to AN) (B 1)

A selection circuit (SW1 to SWN) for activating a selected amplification circuit among the plurality of first amplification circuits (A1 to AN) in accordance with a control signal.

6. The semiconductor integrated circuit according to claim 5, wherein said second amplifier circuit (B1) is an inverting amplifier circuit.

7. The apparatus further comprises a capacitance (C _c ) connected between outputs of the plurality of first width circuits (A 1 to AN) and outputs of the second width circuits (B 1). A semiconductor integrated circuit as described in the above.

8. A negative feedback circuit (Rl, R2) for applying negative feedback from the output of the second amplifier circuit (B1) to the plurality of first amplifier circuits (A1 to AN). Item 6. The semiconductor integrated circuit according to item 5.

9. The semiconductor integrated circuit according to claim 5, further comprising a control circuit (2) for controlling the selection circuits (SW1 to SWN).

10. The semiconductor integrated circuit according to claim 9, wherein the control circuit controls the amount of feedback in the negative feedback circuit.

1 1. The semiconductor integrated circuit according to claim 5, further comprising an analog-to-digital conversion circuit (3) to which an output signal of the second amplifier circuit (B1) is supplied.