Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
  • G06F21/31—User authentication
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
  • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
  • G06F21/575—Secure boot
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F2221/2129—Authenticate client device independently of the user

Definitions

• the invention comprises systems and methods for identifying electronic components and enabling a primary electronic system to make use of only those components which are identified as having the same brand as the primary system.
• FIGURE 1 a flow diagram illustrating a method in accordance with a basic embodiment of the present invention is shown.
• the method has three basic steps: connection of a first component to a second component; retrieval of identifiers stored in memories in each of the components; comparison of the identifiers; and operation of the second component, either with or without the first component, depending upon the results of the comparison of their identifiers.
• FIGURE 2 a functional block diagram illustrating the components of a system in accordance with a basic embodiment of the present invention is shown.
• a primary system 11 includes a memory 12 to store an identifier associated with it.
• a component 13 is configured to be coupled to primary system 11 and operated in conjunction with the primary system.
• a module is coupled to a device, or primary system.
• the primary system may, for example, be a device such as a storage router, while the module may be a Fibre Channel interface module, an LVD SCSI interface module, an HVD SCSI module, an iSCSI interface module, or any other module that may be connected to the device.
• the primary system is powered down prior to connecting the module to it. (As noted above, provisions may be made for connection of the module while the primary system is powered up in other embodiments.) When the primary system is powered up, it executes a boot-up routine.
• the components are, in this embodiment, coupled together by two separate buses.
• the first bus 24 is a PCI bus which is coupled to the functional block (41, 42, 43) of each of the components. This is the pathway over which data is transferred between the components during normal operation of the system. As indicated above, however, each of components 22 and 23 must be configured by system 21 to enable them to communicate with the system via PCI bus 24.
• I 2 C bus 25 is a very simple serial bus which is designed to enable very basic communications between the modules without having to first configure the modules for operation with the system.
• I 2 C bus 25 is operable.
• I 2 C bus 25 is coupled to each of the components so that their respective non-volatile memories (31-33), and the OEM identifiers stored therein, can be accessed.
• Figure 4 also shows comparator 51 coupled to I 2 C bus 25.
• Comparator 51 comprises a data processor. This processor may be the same processor which also provides some or all of the functionality of functional block 41. Comparator 51 is configured to compare the identifiers retrieved from memories 31-33 and to determine which of components 22 and 23 is authorized for use with component 21. Based upon this determination, the system is configured to enable the authorized components.

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• Engineering & Computer Science (AREA)
• Computer Security & Cryptography (AREA)
• Theoretical Computer Science (AREA)
• Computer Hardware Design (AREA)
• Software Systems (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Small-Scale Networks (AREA)

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Applications Claiming Priority (2)

Publications (1)

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Citations (1)

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• 2001
  • 2001-12-28 US US09/683,428 patent/US20030126423A1/en not_active Abandoned
• 2002
  • 2002-06-27 WO PCT/US2002/020634 patent/WO2003058459A1/en not_active Ceased
  • 2002-06-27 JP JP2003558702A patent/JP2005514700A/ja active Pending
  • 2002-06-27 AU AU2002345990A patent/AU2002345990A1/en not_active Abandoned
  • 2002-06-27 EP EP02744739A patent/EP1468364A4/en not_active Withdrawn

Patent Citations (1)

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