WO2003046988A3 - Elektronische anordnung - Google Patents

Elektronische anordnung Download PDF

Info

Publication number
WO2003046988A3
WO2003046988A3 PCT/DE2002/003883 DE0203883W WO03046988A3 WO 2003046988 A3 WO2003046988 A3 WO 2003046988A3 DE 0203883 W DE0203883 W DE 0203883W WO 03046988 A3 WO03046988 A3 WO 03046988A3
Authority
WO
WIPO (PCT)
Prior art keywords
electronic assembly
conductor layer
strip conductor
sandwich
supports
Prior art date
Application number
PCT/DE2002/003883
Other languages
English (en)
French (fr)
Other versions
WO2003046988A2 (de
Inventor
Rainer Topp
Dirk Balszunat
Christoph Ruf
Andreas Fischer
Original Assignee
Bosch Gmbh Robert
Rainer Topp
Dirk Balszunat
Christoph Ruf
Andreas Fischer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert, Rainer Topp, Dirk Balszunat, Christoph Ruf, Andreas Fischer filed Critical Bosch Gmbh Robert
Priority to US10/495,233 priority Critical patent/US7138708B2/en
Priority to EP02779160A priority patent/EP1449252A2/de
Priority to JP2003548308A priority patent/JP2005510877A/ja
Publication of WO2003046988A2 publication Critical patent/WO2003046988A2/de
Publication of WO2003046988A3 publication Critical patent/WO2003046988A3/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49572Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092Integral conductive tabs, i.e. conductive parts partly detached from the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Battery Mounting, Suspending (AREA)
  • Credit Cards Or The Like (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

Es wird eine elektronische Anordnung in Sandwich-Bauweise mit zwei Trägern (10, 11) vorgeschlagen, wobei jeder Träger eine Leiterbahnschicht (8, 13, 14) aufweist, wobei die obere Leiterbahnschicht (13, 14) in verschiedenen Ebenen verläuft.
PCT/DE2002/003883 1999-09-24 2002-10-15 Elektronische anordnung WO2003046988A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/495,233 US7138708B2 (en) 1999-09-24 2002-10-15 Electronic system for fixing power and signal semiconductor chips
EP02779160A EP1449252A2 (de) 2001-11-17 2002-10-15 Elektronische anordnung
JP2003548308A JP2005510877A (ja) 2001-11-17 2002-10-15 電子装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10156626A DE10156626A1 (de) 2001-11-17 2001-11-17 Elektronische Anordnung
DE10156626.3 2001-11-17

Publications (2)

Publication Number Publication Date
WO2003046988A2 WO2003046988A2 (de) 2003-06-05
WO2003046988A3 true WO2003046988A3 (de) 2003-08-21

Family

ID=7706161

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/003883 WO2003046988A2 (de) 1999-09-24 2002-10-15 Elektronische anordnung

Country Status (4)

Country Link
EP (1) EP1449252A2 (de)
JP (1) JP2005510877A (de)
DE (1) DE10156626A1 (de)
WO (1) WO2003046988A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004031592A1 (de) * 2004-06-30 2006-02-09 Robert Bosch Gmbh Elektronikmodulanordnung und entsprechendes Herstellungsverfahren
US8018056B2 (en) 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
JP5414644B2 (ja) 2010-09-29 2014-02-12 三菱電機株式会社 半導体装置
DE102022207848A1 (de) 2022-07-29 2023-11-16 Vitesco Technologies Germany Gmbh Kontaktierungselement für Leistungshalbleitermodule, Leistungshalbleitermodul und Inverter mit einem Kontaktierungselement

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4047197A (en) * 1975-04-19 1977-09-06 Semikron Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Housing and lead structure for a series connected semiconductor rectifier arrangement
DE3201296A1 (de) * 1982-01-18 1983-07-28 Institut elektrodinamiki Akademii Nauk Ukrainskoj SSR, Kiev Transistoranordnung
GB2146174A (en) * 1983-09-06 1985-04-11 Gen Electric Hermetic power chip packages
US5006921A (en) * 1988-03-31 1991-04-09 Kabushiki Kaisha Toshiba Power semiconductor switching apparatus with heat sinks
US6125039A (en) * 1996-07-31 2000-09-26 Taiyo Yuden Co., Ltd. Hybrid module

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59713027D1 (de) * 1996-09-30 2010-03-25 Infineon Technologies Ag Mikroelektronisches bauteil in sandwich-bauweise
WO2001024260A1 (en) * 1999-09-24 2001-04-05 Virginia Tech Intellectual Properties, Inc. Low cost 3d flip-chip packaging technology for integrated power electronics modules

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4047197A (en) * 1975-04-19 1977-09-06 Semikron Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Housing and lead structure for a series connected semiconductor rectifier arrangement
US4047197B1 (de) * 1975-04-19 1985-03-26
DE3201296A1 (de) * 1982-01-18 1983-07-28 Institut elektrodinamiki Akademii Nauk Ukrainskoj SSR, Kiev Transistoranordnung
GB2146174A (en) * 1983-09-06 1985-04-11 Gen Electric Hermetic power chip packages
US5006921A (en) * 1988-03-31 1991-04-09 Kabushiki Kaisha Toshiba Power semiconductor switching apparatus with heat sinks
US6125039A (en) * 1996-07-31 2000-09-26 Taiyo Yuden Co., Ltd. Hybrid module

Also Published As

Publication number Publication date
JP2005510877A (ja) 2005-04-21
EP1449252A2 (de) 2004-08-25
DE10156626A1 (de) 2003-06-05
WO2003046988A2 (de) 2003-06-05

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