WO2003041149A1 - Appareil integre de traitement par voies seche et humide et procede l'utilisant d'elimination de materiaux sur des tranches de semi-conducteurs - Google Patents

Appareil integre de traitement par voies seche et humide et procede l'utilisant d'elimination de materiaux sur des tranches de semi-conducteurs Download PDF

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Publication number
WO2003041149A1
WO2003041149A1 PCT/US2002/035680 US0235680W WO03041149A1 WO 2003041149 A1 WO2003041149 A1 WO 2003041149A1 US 0235680 W US0235680 W US 0235680W WO 03041149 A1 WO03041149 A1 WO 03041149A1
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WO
WIPO (PCT)
Prior art keywords
wet
processing
unit
objects
wafer
Prior art date
Application number
PCT/US2002/035680
Other languages
English (en)
Inventor
Bae Kim Yong
Original Assignee
Bae Kim Yong
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/219,967 external-priority patent/US20040062874A1/en
Application filed by Bae Kim Yong filed Critical Bae Kim Yong
Priority to AU2002350152A priority Critical patent/AU2002350152A1/en
Priority to KR10-2004-7006740A priority patent/KR20040063920A/ko
Publication of WO2003041149A1 publication Critical patent/WO2003041149A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67173—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring

Definitions

  • the invention relates generally to semiconductor fabrication processing, and more particularly to removing material on semiconductor wafers using both dry and wet processes.
  • Removal of patterned photoresist generally includes removing the bulk of the photoresist material using plasma gas treatment (referred herein as “plasma ashing process”) and then removing residual photoresist material using wet-chemical treatment (referred herein as “wet- chemical cleaning process”.
  • plasma ashing process involves applying plasma gas onto the patterned photoresist on the surface of a semiconductor wafer to selectively oxidize the photoresist material.
  • wet-chemical cleaning process involves applying one or more chemical solutions onto the surface of a semiconductor wafer to dissolve the residual photoresist material that was not removed by the plasma ashing process.
  • the semiconductor wafer may be inspected by measuring a feature profile, such as line width and hole diameter, and the thickness of the semiconductor wafer, which includes various layers formed on the semiconductor wafer.
  • a feature profile such as line width and hole diameter
  • the thickness of the semiconductor wafer which includes various layers formed on the semiconductor wafer.
  • Single-wafer spin-type cleaning techniques involve dispensing one or more cleaning fluids, such as de-ionized water, standard clean 1 (SC1) solution and standard clean 2 (SC2) solution, onto a surface of a spinning semiconductor wafer in an enclosed environment.
  • cleaning fluids such as de-ionized water, standard clean 1 (SC1) solution and standard clean 2 (SC2) solution
  • SC1 standard clean 1
  • SC2 standard clean 2
  • semiconductor wafers are individually cleaned so that the potential for cross-contamination and residual contamination is minimized.
  • Commercially available wafer fabrication tools for photoresist removal are built for either the plasma ashing process or the wet-chemical cleaning process. Thus, two separate tools are needed to perform both the plasma ashing and wet-chemical cleaning processes. In addition, a third separate wafer fabrication tool is needed if the semiconductor wafers are to be inspected as well.
  • a dry stripper unit i.e., a plasma ashing unit
  • a wet stripping bath tank unit a first rinsing tank
  • a second rinsing tank containing an ultrasonic vibrator
  • a cleaning and spin dry unit U.S. Patent No. 5,952,245 issued to Torii et al. describes a sample processing apparatus that includes a buffer chamber for plasma etching and post-processing plasma ashing, a wet-processing chamber for wet-chemical cleaning and a dry-processing chamber for drying using a heater.
  • a concern with the apparatuses of Takami et al. and Torii et al. is that the described apparatuses require large footprints due to their arrangement of various processing stations. Another concern is that the configuration of the described apparatuses does not allow for the plasma ashing process to be performed after the wet-chemical cleaning process, which may be preferred for some applications. Furthermore, the described apparatuses does not allow either the plasma ashing process or the wet- chemical cleaning process to be easily repeated after a semiconductor wafer has been subjected to both processes, which may also be preferred for some applications.
  • An apparatus and method for removing materials, such as photoresist, on surfaces of objects, such as semiconductor wafers utilizes one or more integrated dry-wet processing modules to selectively perform plasma ashing and wet-chemical cleaning processes.
  • a customized combination of plasma ashing and wet-chemical cleaning processes can be performed on a single platform to achieve desired processing results on the objects, which increases throughput and reduces the possibility of contamination.
  • Each of the integrated dry-wet processing modules includes a plasma ashing unit and a wet-chemical cleaning unit, which may be vertically positioned to minimize the footprint of the apparatus.
  • An apparatus in accordance with an embodiment of the invention includes an object loading/unloading unit configured to load objects into and unload the objects from the apparatus, a first processing unit configured to perform a plasma ashing process, a second processing unit configured to perform a wet-chemical cleaning process, and an object transfer system configured to selectively transfer the objects from the object loading/unloading unit to the first processing unit or the second processing unit.
  • the apparatus may also include a critical dimension inspection unit to inspect the objects that are being processed by the apparatus.
  • the first and second processing units of the apparatus may be integrated into a single dry-wet processing module.
  • the first and second processing units may be vertically positioned on the dry-wet processing module such that one unit of the first and second processing units is positioned above the other unit of the first and second processing units.
  • the first processing unit of the apparatus may include a maintenance window located on a side of a processing chamber.
  • the first processing unit may also include an exhaust outlet connected to the processing chamber. The exhaust outlet may be configured to lead from the processing chamber to a side of the unit.
  • a method of removing material on surfaces of objects in accordance with an embodiment of the invention includes providing an object to be processed at an apparatus, selectively performing a first process on the object at a first processing unit of the apparatus, and selectively performing a second process on the object at a second processing unit of the apparatus at a second processing unit of the apparatus.
  • Each of the first and second processes can be either a plasma ashing process or a wet-chemical cleaning process.
  • the method may further include selectively performing a third process on the object.
  • the third process may be a plasma ashing process, a wet-chemical cleaning process or a critical dimension inspection process.
  • Fig. 1 is a diagram of an apparatus for removing undesired material, such as photoresist, on semiconductor wafers using both dry and wet processes in accordance with an exemplary embodiment of the present invention.
  • Fig. 2A is a front view of an integrated dry-wet processing module included in the apparatus of Fig. 1.
  • Fig. 2B is a side view of the integrated dry-wet processing module of Fig. 2A.
  • Fig. 3 is a diagram of the apparatus of Fig. 1 that includes three additional integrated dry-wet processing modules.
  • Fig. 4 is a cross-sectional diagram of a wet-chemical cleaning unit of the integrated dry-wet processing module of Figs. 2A and 2B.
  • FIG. 5 is a perspective diagram of a plasma ashing unit of the integrated dry-wet processing module of Figs. 2A and 2B.
  • Fig. 6 is a cross-sectional diagram of the plasma ashing unit of the integrated dry-wet processing module of Figs. 2A and 2B, as viewed from the front of the plasma ashing unit.
  • Fig. 7 is a cross-sectional diagram of the plasma ashing unit of the integrated dry-wet processing module of Figs. 2A and 2B, as viewed from the side of the plasma ashing unit.
  • FIG. 8 is another cross-sectional diagram of the plasma ashing unit of the integrated dry-wet processing module of Figs. 2A and 2B, as viewed from the side of the plasma ashing unit, which shows the chuck assembly of the plasma ashing unit being removed.
  • Fig. 9 is a rear view of the plasma ashing unit of the integrated dry-wet processing module of Figs. 2A and 2B.
  • Fig. 10 is a process flow diagram of the overall operation of the apparatus of Fig. 1.
  • Fig. 11 is a diagram of an apparatus for removing undesired material, such as photoresist, on semiconductor wafers using both dry and wet processes in accordance with a modified exemplary embodiment of the present invention.
  • Fig. 12 is a diagram of the apparatus of Fig. 11 that includes three additional integrated dry-wet processing modules.
  • Fig. 13 is a process flow diagram of a method of removing undesired material, such as photoresist, on semiconductor wafers in accordance with an embodiment of the invention.
  • an apparatus 100 for removing undesired material, such as photoresist, on semiconductor wafers in accordance with an exemplary embodiment of the invention is shown.
  • the apparatus utilizes one or more integrated dry-wet processing modules 102A, 102B and 102C to perform both a plasma ashing process and a wet-chemical cleaning process in a closed environment, which is provided by a housing 104.
  • the apparatus integrates two traditionally separate wafer fabrication processes into a single platform.
  • the configuration of the apparatus is such that the order of the plasma ashing and wet-chemical cleaning processes per ormed by the apparatus can be customized. In addition, one or both of these processes can be repeated in any order as needed.
  • the wet-chemical cleaning process can be performed before and after the plasma ashing process, which may be preferred for some applications.
  • the integration of traditionally separate wafer fabrication processes into a single platform significantly improves equipment utilization and reduces total equipment manufacturing cost. Furthermore, the integration reduces total defect density of the resulting semiconductor devices since semiconductor wafers are not exposed to external environment between the wafer fabrication processes.
  • the apparatus includes a cassette unit 106, the integrated dry-wet processing modules 102A, 102B and 102C, a wafer transfer system 108, a control module 110, and a user interface unit 112.
  • the integrated dry-wet processing modules and the wafer transfer system are contained within the closed environment provided by the housing 104. Consequently, semiconductor wafers being processed by the apparatus are not exposed to the external environment, i.e., the cleanroom, between plasma ashing and wet-chemical cleaning processes, which significantly reduces the possibility of contamination.
  • the cassette unit 106 of the apparatus 100 is used to load semiconductor wafers to be processed into the apparatus. Furthermore, the cassette unit is used to unload processed semiconductor wafers from the apparatus.
  • the cassette unit may be configured to receive one or more wafer carriers 114A, 114B and 114C, which may be wafer cassettes, SMIF ("Standard Machine lnterface")-Pods or FOUPs ("Front-Opening Unified Pods").
  • the wafer carriers are used to transport semiconductor wafers into and out of the apparatus.
  • Semiconductor wafers to be processed are loaded into the apparatus by inserting one or more wafer carriers containing the wafers into the cassette unit so that the wafers can be selectively transferred to the integrated dry-wet processing modules 102A, 102B and 102C for processing.
  • the semiconductor wafers After being processed by one or more integrated dry-wet processing modules, the semiconductor wafers are returned to the original wafer carriers or to different wafer carriers at the cassette unit.
  • the wafer carriers containing the processed semiconductor wafers can then be removed from the cassette unit and may be transferred to another wafer fabrication apparatus for further processing.
  • the wafer transfer system 108 of the apparatus 100 operates to transfer semiconductor wafers between the cassette unit 106 and the integrated dry-wet processing units 102A, 102B and 102C.
  • the wafer transfer system includes two wafer transfer mechanisms 116 and 118 and an optional wafer buffer station 120.
  • the wafer transfer mechanism 116 is designed to transfer semiconductor wafers to be processed from the wafer carriers 114A, 114B and 114C in the cassette unit 112 to the wafer buffer station 120, while the wafer transfer mechanism 118 is configured to selectively transfer the wafers from the wafer buffer station to the integrated dry-wet processing modules and to selectively transfer the wafers between the integrated dry- wet processing modules.
  • the wafer transfer mechanisms are configured to directly relay semiconductor wafers between themselves to selectively transfer the wafers from the cassette unit to the integrated dry-wet processing modules.
  • each integrated dry-wet processing module includes a plasma ashing unit 202 and a wet-chemical cleaning unit 204, as shown in Figs. 2A and 2B.
  • semiconductor wafers need to be transferred between the plasma ashing unit and the wet-chemical cleaning unit of each integrated dry-wet processing module to perform both plasma ashing and wet-chemical cleaning.
  • the transfer of semiconductor wafers between the plasma ashing unit and the wet- chemical cleaning unit of an integrated dry-wet processing module is performed by the wafer transfer mechanism 118. Since the wafer transfer mechanism 118 can also transfer semiconductor wafers between the integrated dry-wet processing modules, the wafer transfer mechanism 118 can selectively transfer a semiconductor wafer from any unit of the integrated dry-wet processing modules to any other unit of the processing modules.
  • the wafer transfer mechanism 116 includes a multi-axis robot
  • the wafer transfer mechanism 118 includes a multi-axis robot 126 on a track 128 that extends across the front of the integrated dry-wet processing modules 102A, 102B and 102C.
  • the multi-axis robots 122 and 126 are designed to travel linearly along the respective tracks 124 and 128 and to manipulate one or more semiconductor wafers in various directions, such as radial, rotational, vertical and lateral directions.
  • the multi-axis robot 122 is configured to move along the track 124 to selectively pick up semiconductor wafers from the wafer carriers 114A, 114B and 114C in the cassette unit 106 and to transfer the wafers to the wafer buffer station 120 or the multi-axis robot 126.
  • the multi-axis robot 126 is configured to move along the track 128 to selectively transfer semiconductor wafers from the wafer buffer station 120 or the multi-axis robot 122 to the integrated dry- wet processing modules.
  • one or both of the wafer transfer mechanisms may include a pre-aligner for wafer alignment.
  • the pre-aligner operates to optically scan the edge of a semiconductor wafer and to adjust the wafer using rotation and/or translation to correct for any discrepancies in the center location and angular orientation of the wafer.
  • the apparatus may include just one wafer transfer mechanism configured to perform the functions of the wafer transfer mechanisms 116 and 118, or may include additional wafer transfer mechanisms or multi-axis robots to divide one or more functions of the wafer transfer mechanisms 116 and 118.
  • the wafer transfer mechanisms 116 and 118 may be constructed in accordance with principles already well known with commercially available components, such as those manufactured by Newport Corporation.
  • the integrated dry-wet processing modules 102A, 102B and 102C of the apparatus 100 can perform both plasma ashing and wet- chemical cleaning processes to remove undesired material, e.g., photoresist, on semiconductor wafers.
  • the apparatus is shown to include three integrated dry-wet processing modules that are situated on the same side of the track 128 of the wafer transfer mechanism 118.
  • the apparatus may include fewer or more integrated dry-wet processing modules.
  • the apparatus may include three additional integrated dry-wet processing modules 102D, 102E and 102F on the other side of the track 128 of the wafer transfer mechanism 118, as illustrated in Fig. 3.
  • the integrated dry-wet processing modules 102A, 102B and 102C are described using the processing module 102A as an example.
  • Figs. 2A and 2B are front and side views of the integrated dry-wet processing module 102A, respectively.
  • the integrated dry-wet processing module 102A includes a plasma ashing unit 202 and a wet-chemical cleaning unit 204, which are connected to a frame 206, as shown in Figs. 2A and 2B.
  • the frame may include a base 208 that can be attached to the housing 104 of the apparatus 100 to affix the integrated dry-wet processing module to the housing. Alternatively, the frame may be configured to be attached directly to the housing.
  • the plasma ashing and wet-chemical cleaning units are vertically positioned such that the plasma ashing unit is situated above the wet-chemical cleaning unit.
  • the vertical arrangement of the plasma ashing and wet-chemical cleaning units allows the footprint of the apparatus to be reduced.
  • the wet-chemical cleaning unit may be positioned above the plasma ashing unit, or the plasma ashing and wet-chemical cleaning units may be positioned side- by-side.
  • the plasma ashing unit 202 and the wet-chemical cleaning unit 204 are connected to the frame 206 such that a upper utility space 210 exists between two units and a lower utility space 212 exists below the wet-chemical cleaning unit.
  • the utility space 210 may be used to route one or more fluid supply lines (not shown) to the wet-chemical cleaning unit.
  • the utility space 212 may be used to route drain conduits and/or exhaust outlets from the wet-chemical cleaning unit.
  • the utility spaces 210 and 212 may also be used to route wires, lines and/or conduits to the plasma ashing and wet-chemical cleaning units, as needed.
  • FIG. 4 is a cross-sectional diagram of the cleaning unit.
  • the wet- chemical cleaning unit is a spin-type, single-wafer, wet-chemical cleaning unit.
  • the wet-chemical cleaning unit is configured to clean a single semiconductor wafer by applying one or more cleaning fluids onto the wafer, as the wafer is rotated, in a suitable atmosphere.
  • the wet-chemical cleaning unit includes an upper enclosure structure 402 and a lower enclosure structure 404, which provide an enclosed cleaning chamber 406 when the upper and lower structures are closed.
  • the upper enclosure structure is designed to be raised by a lifting mechanism (not shown) so that the wet-chemical cleaning unit can be opened to receive a semiconductor wafer to be cleaned.
  • the wet- chemical cleaning unit further includes a wafer support structure 408, a fluid supply line 410, a backside fluid supply structure 412 with a fluid supply conduit 414, and an environmental gas supply assembly 416 connected to a gas supply line 418.
  • the wafer support structure 408 is configured to securely hold a single semiconductor wafer for cleaning.
  • the wafer support structure is connected to a motor (not shown), which rotates the wafer support structure. Consequently, the semiconductor wafer on the support structure is also rotated by the rotation of the wafer support structure.
  • the wafer support structure can be any wafer support structure that can securely hold a semiconductor wafer and rotate the wafer, such as conventional wafer supports structures that are currently used in commercially available single-wafer wet cleaning systems.
  • the fluid supply line 410 is used to supply one or more cleaning fluids onto the surface of a semiconductor wafer being cleaned.
  • cleaning fluids may include the following fluids: de-ionized water, diluted HF, mixture of NH 4 OH and H 2 O, standard clean 1 or "SC1" (mixture of NH 4 OH, H 2 O 2 and H 2 O), standard clean 2 or "SC2" (mixture of HCI, H 2 O 2 and H 2 O), ozonated water (de-ionized water with dissolved ozone), modified SC1 (mixture of NH 4 OH and H 2 O with ozone), modified SC2 (mixture of HCI and H 2 O with ozone), known cleaning solvents (e.g., a hydroxyl amine based solvent EKC265, available from EKC technology, Inc.), or any constituent of these fluids.
  • EKC265 hydroxyl amine based solvent
  • the backside fluid supply structure 412 is used to supply fluid, such as deionized water, to the backside of the semiconductor wafer being cleaned to ensure that the backside of the semiconductor wafer does not become contaminated during the cleaning process.
  • the backside fluid supply structure receives the fluid through the fluid supply conduit 414.
  • the environmental gas supply assembly 416 which is attached to the upper enclosure structure 402, provides clean environmental gas, such as N 2 or air, into the enclosed chamber 406 of the wet-chemical cleaning unit.
  • the environmental gas is received at the environmental gas supply assembly through the gas supply line 418.
  • the fluid supply line 410, the fluid supply conduit 414 and the gas supply line 418 are connected to a supply of cleaning fluids and gases (not shown).
  • a semiconductor wafer to be cleaned is transferred into the cleaning chamber 406 of the wet- chemical cleaning unit and placed on the wafer support structure 408 by the multi-axis robot 126 of the wafer transfer mechanism 118.
  • the semiconductor wafer may be transferred from the wafer buffer station 120, the multi-axis robot 122 or any plasma ashing or wet-chemical cleaning unit of the integrated dry-wet processing modules 102A, 102B and 102C.
  • the semiconductor wafer is then rotated and cleaning fluids are applied to one or both surfaces of the wafer, i.e., the upper surface and the backside surface of the wafer.
  • the cleaning fluids are supplied through the fluid supply line 410 and the fluid supply conduit 414. Meanwhile, clean environmental gas is introduced into the cleaning chamber 406 through the environmental gas supply assembly 416. The environmental gas is supplied to the assembly through the gas supply line 418.
  • the sequence of cleaning fluids applied to the semiconductor wafer can vary, depending on the particular wafer cleaning technique being performed. As an example, if RCA wafer cleaning technique is being performed, the sequence of cleaning fluids may be as follows: SC1, diluted HF and SC2.
  • the cleaning process may further include rinsing and then spin-drying.
  • the wet-chemical cleaning unit 204 may further include a residue detection system, which comprises a UV-illuminating device 420 and a UV detector 422 to perform in-situ residue detection.
  • the UV-illuminating device 420 illuminates the upper surface of a semiconductor wafer being cleaned with UV light 424.
  • Photoresist residue which is typically composed of organic material, on the semiconductor wafer will generate fluorescent light 426 in response to the UV light, which will be detected by the UV detector 422.
  • photoresist residue remaining on a semiconductor wafer can be detected by the residue detection system, as the wafer is being cleaned.
  • the plasma ashing unit 202 of the integrated dry-wet processing module 102A is described with reference to Figs. 5, 6, 7, 8 and 9.
  • Fig. 5 is a perspective view of the plasma ashing unit. Figs.
  • the plasma ashing unit includes a chamber structure 502, a wafer door 504 located at the front of the chamber structure, a shower head assembly 506 located at the top of the chamber structure, a plasma gas inlet 508 and a vacuum and exhaust outlet 510.
  • the chamber structure 502 provides an ashing chamber 512, shown in Figs. 6, 7 and 8, for plasma ashing a semiconductor wafer.
  • the semiconductor wafer to be processed is loaded into the chamber through the wafer door 504.
  • the shower head assembly 506 includes a shower head 602 to evenly distribute plasma gas received through the plasma gas inlet 508, as shown in Figs. 6, 7 and 8.
  • the plasma gas may be composed of CF , O 2 , N 2 , NF 3 , NH 3 , H 2 N 2 , H 2 and/or Ar.
  • the plasma gas inlet is connected to a plasma gas generator, which generates the plasma gas using a microwave generator.
  • the vacuum and exhaust outlet 510 is used to remove products of a plasma ashing process.
  • the plasma ashing unit 202 also includes a chuck assembly 604, which is attached to the back of the chamber structure 502, as shown in Figs.
  • the chuck assembly can be removed from the back of the chamber structure so that a maintenance window 802 can be exposed for chamber maintenance, as illustrated in Fig. 8.
  • the chuck assembly includes a chuck 702 and a backboard structure 704, which are connected via a connecting member 706.
  • the chuck 702 serves as a platform for a semiconductor wafer to be placed during plasma ashing.
  • the backboard structure 704 is designed to fit into the maintenance window 802.
  • the backboard structure 704 is designed to be removed from the maintenance window. Consequently, the backboard structure includes handles 708 on the back of the structure so that the entire chuck assembly 604 can be removed for chamber maintenance.
  • the chuck assembly further includes a lift-pin mechanism for lifting a semiconductor wafer during loading of the wafer onto the chuck or unloading of the wafer from the chuck.
  • the lift-pin mechanism comprises lift-pins 710 and a lift-pin driving motor 712.
  • the lift-pins 710 are configured to be raised and lowered by the lift-pin driving motor 712 to provide clearance for the multi- axis robot 126, so that a semiconductor wafer can be placed onto or removed from the chuck by the multi-axis robot.
  • the configuration of the plasma ashing unit 202 differs from conventional plasma ashing units in that the maintenance window is located on the rear of the unit. In conventional plasma ashing units, the maintenance window is located on the top and/or the bottom of the unit.
  • the rear location of the maintenance window 802 allows for easy access to the ashing chamber 512 of the plasma ashing unit. Furthermore, as illustrated in Figs. 5 and 6, the vacuum and exhaust outlet 510 of the plasma ashing unit 202 exits out the side of the unit, rather than exiting out of the bottom of the unit, as is the case in conventional plasma ashing units.
  • the configuration of the plasma ashing unit 202 reduces the amount of wires, lines and/or conduits located below the plasma ashing unit, i.e., the upper utility space 210 between the plasma ashing unit and the wet-chemical cleaning unit 204, and provides enough clearance to access the wet-chemical cleaning unit through the upper utility space for maintenance.
  • the plasma ashing process performed by the plasma ashing unit 202 is now described. A semiconductor wafer to be cleaned is transferred into the ashing chamber 512 of the plasma ashing unit through the wafer door 504 and placed on the chuck 702 by the multi-axis robot 126 of the wafer transfer mechanism 118.
  • the semiconductor wafer may be transferred from the wafer buffer station 120, the multi-axis robot 122 or any plasma ashing or wet-chemical cleaning unit of the integrated dry-wet processing modules 102A, 102B and 102C.
  • plasma gas is evenly applied onto the surface of the wafer.
  • the plasma gas is supplied through the shower head assembly 506 via the plasma gas inlet 508.
  • the plasma ashing unit 202 may also include an endpoint detection system (not shown) to detect the endpoint during a plasma ashing process.
  • the endpoint is defined as the point in time when an overlying layer of material, e.g., photoresist, is completely removed, and thus exposing the underlying layer.
  • the plasma ashing unit may utilize many components commonly found in conventional plasma ashing devices, such as those commercially available from ULVAC Technology Inc. or Novellus Systems Inc. Although the plasma ashing unit 202 has been described as a downstream plasma asher, the plasma ashing unit may be configured to generate the plasma gas within the ashing chamber 512.
  • the control module 110 of the apparatus 100 controls all operational aspect of the apparatus.
  • the control module is configured to control the components of the apparatus.
  • the control module is configured to process various data derived from the components of the apparatus, such as the UV detector 422 of the wet-chemical cleaning unit 204.
  • the control module may be designed to interface with other wafer processing apparatuses or a host computer that controls the entire wafer fabrication facility.
  • the control module is connected to the user interface unit 112, which allows an operator to access the control module and to input information and/or commands.
  • the user interface may include buttons, dials, levers, switches, graphic user interface and/or other input means.
  • one or more wafer carriers 114A, 114B and 114C containing semiconductor wafers to be processed are loaded into the cassette unit 106.
  • an appropriate wafer processing recipe is selected by an operator using the user interface unit 112.
  • a wafer processing recipe includes the sequence of processes that are to be performed by the apparatus and parameters related to the processes. Unlike conventional wafer processing apparatuses that perform a set number of processes in a prescribed order, the apparatus 100 can selectively perform a desired number of processes in a customized order. That is, semiconductor wafers can be selectively processed at different processing units of the apparatus without a limit on the number of processes that can be performed for each semiconductor wafer. Consequently, the apparatus can process semiconductor wafers according to various wafer processing recipes.
  • a selected semiconductor wafer in one of the wafer carriers is transferred from the cassette unit to the wafer buffer station 120 by the multi-axis robot 122 of the wafer transfer mechanism 116.
  • the semiconductor wafer is then selectively transferred from the wafer buffer station to a processing unit, which may be any plasma ashing or wet- chemical cleaning unit of the integrated dry-wet processing modules 102A, 102B and 102C, by the multi-axis robot 126 of the wafer transfer mechanism 118.
  • the selected semiconductor wafer is directly transferred from the multi-axis robot 122 to the multi-axis robot 126.
  • the next semiconductor wafer to be processed is transferred from one of the wafer carriers 114A, 114B and 114C in the cassette unit 106 to the wafer buffer station 120 or the multi-axis robot 126 by the multi-axis robot 122.
  • This semiconductor wafer can then be selectively transferred to an unoccupied processing unit of the integrated dry-wet processing modules 102A, 102B and 102C.
  • the selected semiconductor wafer is processed at the processing unit, which may involve plasma ashing or wet-chemical cleaning.
  • step1008 at which the semiconductor wafer is transferred to another processing unit, which may be any plasma ashing or wet-chemical cleaning unit of the integrated dry- wet processing modules 102A, 102B and 102C, by the multi-axis robot 126 of the wafer transfer mechanism 118. If the semiconductor wafer does not need further processing, the operation proceeds to step 1012, at which the semiconductor wafer is transferred from the current processing unit to the wafer buffer station 120 or the multi-axis robot 122 by the multi- axis robot 126.
  • another processing unit which may be any plasma ashing or wet-chemical cleaning unit of the integrated dry- wet processing modules 102A, 102B and 102C
  • the semiconductor wafer is transferred from the wafer buffer station or the multi-axis robot 126 back to the same or different wafer carrier 114A, 114B or 114C at the cassette unit 106 by the multi-axis robot 122.
  • Steps 1008-1014 are also performed for subsequent semiconductor wafers in a staggered fashion such that one semiconductor wafer can be processed at one processing unit while another semiconductor wafer is processed at a different processing unit.
  • the throughput of the apparatus 100 is significantly greater than if the semiconductor wafers are sequentially processed one wafer at a time.
  • an apparatus 1100 for removing undesired material, such as photoresist, on semiconductor wafers in accordance with a modified exemplary embodiment of the invention is shown.
  • the apparatus 1100 includes all the components of the apparatus 100 of Fig. 1 and further includes a wafer inspection module 1102.
  • the apparatus 1100 includes three integrated dry-wet processing modules 102A, 102B and 102C and the wafer inspection module 1102.
  • the wafer inspection module 1102 is shown to be positioned on the opposite side of the track 128 of the wafer transfer mechanism 118 with respect to the integrated dry-wet processing modules 102A, 102B and 102C.
  • the wafer inspection module may be positioned on the same side of the track 128 as the integrated dry-wet processing modules.
  • the wafer inspection module may be positioned at the end of the track 128 such that the wafer transfer mechanism 118 is located between the cassette unit 106 and the wafer inspection module, as shown in Fig. 12.
  • the apparatus 1100 of the modified exemplary embodiment may include fewer or more integrated dry-wet processing modules.
  • the apparatus 1100 is shown in Fig. 12 to include six integrated dry-wet processing modules 102A, 102B, 102C, 102D, 102E and 102F.
  • the wafer inspection module 1102 of the apparatus 1100 operates to measure critical dimensions of a semiconductor wafer, which include feature profiles, such as line width and hole diameter, and thickness of the semiconductor wafers.
  • the wafer inspection module may also operate to detect organic residue, e.g., photoresist.
  • the wafer inspection module may include a residue detection system, which was described above in reference to the wet-chemical cleaning unit 204.
  • the wafer inspection module may be fabricated using commercially available components, such as those manufactured by Ocean Optics, Inc.
  • the wafer inspection module allows semiconductor wafers to be inspected after being processed by one or more processing units of the integrated dry-wet processing modules 102A, 102B and 102C to ensure that the processed wafers are within prescribed specification.
  • the processed semiconductor wafers that do not meet the prescribed specification can be further processed at one or more processing units of the integrated dry- wet processing modules.
  • the wafer inspection module 1102 may be configured to perform feature profile measurements using electron-beam imaging, a scanning force microscopy, a surface contact mechanical probe technique or an optical technique, such as scatterometry or focus laser imaging.
  • Scanning force microscopy (SFM) which can provide high-resolution topographical information, utilizes a very small mechanical probe to sense minute atomic forces that are interacting very close to the surface of a semiconductor wafer to measure the feature profile of the wafer.
  • the surface contact mechanical probe technique which is used by such devices as surface profilometers, involves scanning a mechanical probe across the surface of a semiconductor wafer to measure the feature profile of the wafer.
  • Scatterometry involves illuminating the surface of a semiconductor wafer using a light beam, e.g., laser beam, and then using the angular distribution of elastically scattered light to characterize periodic topographic structures on the wafer surface.
  • a light beam e.g., laser beam
  • NA numerical aperture
  • the operation of the apparatus 1100 is similar to the operation of the apparatus 100 of Figs. 1 and 2. However, due to the wafer inspection module 1102, the apparatus 1100 can perform critical dimension inspection, as well as plasma ashing and wet-chemical cleaning processes. Thus, the apparatus 1100 can perform any combination of plasma ashing process, wet-chemical cleaning process and critical dimension inspection in any customized sequence, which may include repeating one or more of these processes.
  • the described apparatuses 100 and 1100 may be modified to include other single-wafer processing units, such as CVD (Chemical Vapor Deposition), plasma etching, ion implantation, oxidation and annealing units.
  • the apparatuses can perform other single-wafer fabrication processes in a single platform.
  • a method of removing undesired material, such as photoresist, on semiconductor wafers in accordance with an embodiment of the invention is described with reference to Fig. 13.
  • a semiconductor wafer to be processed is provided.
  • a first process is selectively performed on the semiconductor wafer at a first processing unit of a wafer processing apparatus.
  • the first processing unit may be a wafer inspection module, or a plasma ashing or wet-chemical cleaning unit of an integrated wet-chemical processing module of the apparatus.
  • the first process performed by the first processing unit may be a plasma ashing process, a wet-chemical cleaning process or a critical dimension inspection process.
  • a second process is selectively performed on the semiconductor wafer at a second processing unit of the apparatus, which may also be a wafer inspection module, or a plasma ashing or wet-chemical cleaning unit of an integrated wet-chemical processing modules of the apparatus. Similar to the first process, the second process performed by the second processing unit may be a plasma ashing process, a wet-chemical cleaning process or a critical dimension inspection process.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

L'invention porte sur un appareil (100) et un procédé d'élimination de certains matériaux tels que les photorésines de la surface d'objets tels que des tranches de semi-conducteurs. On utilise à cet effet un ou plusieurs modules (102A, 102B, 102C) intégrés de traitement par voies sèche et humide assurant sélectivement la calcination au plasma et le nettoyage chimique par voie humide. Une combinaison de ces deux techniques peut s'exécuter sur une même plate-forme pour atteindre le résultat recherché. Dans une exécution, l'appareil peut également comprendre une unité d'examen des dimensions critiques des objets en cours de traitement.
PCT/US2002/035680 2001-11-07 2002-11-06 Appareil integre de traitement par voies seche et humide et procede l'utilisant d'elimination de materiaux sur des tranches de semi-conducteurs WO2003041149A1 (fr)

Priority Applications (2)

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AU2002350152A AU2002350152A1 (en) 2001-11-07 2002-11-06 Integrated dry-wet processing apparatus and method for removing material on semiconductor wafers using dry-wet processes
KR10-2004-7006740A KR20040063920A (ko) 2001-11-07 2002-11-06 건식-습식 처리를 이용한 반도체 웨이퍼 상에서 재료를제거하기 위한 집적 전식-습식 처리장치 및 방법

Applications Claiming Priority (4)

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US34600001P 2001-11-07 2001-11-07
US60/346,000 2001-11-07
US10/219,967 US20040062874A1 (en) 2002-08-14 2002-08-14 Nozzle assembly, system and method for wet processing a semiconductor wafer
US10/219,967 2002-08-14

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US9064807B2 (en) 2013-02-27 2015-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated platform for improved wafer manufacturing quality
DE102017118084A1 (de) * 2017-05-31 2018-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung, Werkzeug und Verfahren zum Herstellen

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KR100849366B1 (ko) 2006-08-24 2008-07-31 세메스 주식회사 기판을 처리하는 장치 및 방법
KR100809590B1 (ko) * 2006-08-24 2008-03-04 세메스 주식회사 기판 처리 장치 및 이를 이용한 기판 처리 방법
KR100780353B1 (ko) * 2006-11-27 2007-11-30 삼성전자주식회사 기판의 건식 세정공정

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US9064807B2 (en) 2013-02-27 2015-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated platform for improved wafer manufacturing quality
US10497557B2 (en) 2013-02-27 2019-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated platform for improved wafer manufacturing quality
DE102017118084A1 (de) * 2017-05-31 2018-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung, Werkzeug und Verfahren zum Herstellen
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KR20040063920A (ko) 2004-07-14

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