WO2003040902A1 - Semiconductor integrated circuit device, system and signal transmission method - Google Patents

Semiconductor integrated circuit device, system and signal transmission method Download PDF

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Publication number
WO2003040902A1
WO2003040902A1 PCT/JP2001/009731 JP0109731W WO03040902A1 WO 2003040902 A1 WO2003040902 A1 WO 2003040902A1 JP 0109731 W JP0109731 W JP 0109731W WO 03040902 A1 WO03040902 A1 WO 03040902A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
integrated circuit
signal transmission
semiconductor integrated
transmission method
Prior art date
Application number
PCT/JP2001/009731
Other languages
French (fr)
Japanese (ja)
Inventor
Takashi Sato
Peter Lee
Goichi Yokomizo
Toshio Shinmi
Shigenori Otake
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2001/009731 priority Critical patent/WO2003040902A1/en
Priority to JP2003542465A priority patent/JPWO2003040902A1/en
Priority to TW091104185A priority patent/TW589792B/en
Publication of WO2003040902A1 publication Critical patent/WO2003040902A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

At the input terminal of a second circuit, there is provided a time constant circuit which can be so adjusted that the period (Tnoise) of a noise to occur on the power supply line of a first circuit may correspond to either the periods (Te1 to Te8) of clock signals or their integral multiples when a signal of a plurality of bits to be transmitted in synchronism with the clock signal is output from the output circuit of the first circuit and captured by the input circuit of the second circuit.
PCT/JP2001/009731 2001-11-07 2001-11-07 Semiconductor integrated circuit device, system and signal transmission method WO2003040902A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2001/009731 WO2003040902A1 (en) 2001-11-07 2001-11-07 Semiconductor integrated circuit device, system and signal transmission method
JP2003542465A JPWO2003040902A1 (en) 2001-11-07 2001-11-07 Semiconductor integrated circuit device and system, and signal transmission method
TW091104185A TW589792B (en) 2001-11-07 2002-03-06 Semiconductor integrated circuit device and system, and signal transmission method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/009731 WO2003040902A1 (en) 2001-11-07 2001-11-07 Semiconductor integrated circuit device, system and signal transmission method

Publications (1)

Publication Number Publication Date
WO2003040902A1 true WO2003040902A1 (en) 2003-05-15

Family

ID=11737915

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/009731 WO2003040902A1 (en) 2001-11-07 2001-11-07 Semiconductor integrated circuit device, system and signal transmission method

Country Status (3)

Country Link
JP (1) JPWO2003040902A1 (en)
TW (1) TW589792B (en)
WO (1) WO2003040902A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE202005021861U1 (en) 2004-02-27 2010-09-23 Neuhofer Jun., Franz Device for bridging a height difference between two floor surfaces

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8014476B2 (en) 2005-11-07 2011-09-06 Qualcomm, Incorporated Wireless device with a non-compensated crystal oscillator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443711A (en) * 1990-06-08 1992-02-13 Nec Corp Iput buffer circuit
JPH10126453A (en) * 1996-10-15 1998-05-15 Hitachi Ltd Interface circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443711A (en) * 1990-06-08 1992-02-13 Nec Corp Iput buffer circuit
JPH10126453A (en) * 1996-10-15 1998-05-15 Hitachi Ltd Interface circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE202005021861U1 (en) 2004-02-27 2010-09-23 Neuhofer Jun., Franz Device for bridging a height difference between two floor surfaces

Also Published As

Publication number Publication date
JPWO2003040902A1 (en) 2005-06-09
TW589792B (en) 2004-06-01

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