JPH0443711A - Iput buffer circuit - Google Patents

Abstract

PURPOSE:To attain stable operation of the circuit against power noise by comparing outputs of inverters with a different logical threshold level so as to detect power noise thereby adjusting the logic threshold level of the inverters. CONSTITUTION:A 1st detection means 110 outputs a high level when a common level SS is a 1st prescribed value or over or a power voltage CC is a 2nd prescribed level or below, and outputs a low level when the common level is decreased or the power voltage is increased. A 2nd detection means 120 outputs a low level when the common level SS is a 1st prescribed value or below or the power voltage CC is a 2nd prescribed level or over, and outputs a high level when the common level rises or the power voltage is decreased. A 2nd one conduction enhancement transistor (TR) QP1 receives an output of the 1st detection means 110 to its gate and a 2nd other conduction enhancement TR QN7 receives an output of the 2nd detection means 120 to its gate to prevent fluctuation of the logic threshold level against power noise. Thus, the circuit acts stably against power noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to an input buffer circuit of a semiconductor device whose main component is an insulated gate field effect transistor. In particular, the present invention relates to a high-power buffer circuit that requires measures against power supply noise during reading.

〔overview〕

The present invention provides separate inverters with different logic thresholds (different noise margins) in the input buffer circuit, compares their output values to detect the occurrence of power supply noise with high sensitivity, and based on the detection results. By adjusting the logic threshold of the inverter, it is possible to increase the noise margin and ensure stable operation against power supply noise.

[Conventional technology]

FIG. 3 is a block diagram of a conventional input buffer circuit.

Conventionally, input buffer circuits classify external input signals into two levels, low level or high level, according to their voltage values and convert them into C
This is a circuit that outputs at MOS level. As a specific example,
The output voltage value V when the input signal is at TTL level, for example, the low level input voltage value VIL is 0.8v. υ is the common potential value V55 level, and the high level input voltage value V
Output voltage value V when IB is 2.2v. 07 are each amplified to the power supply voltage value VCC level.

Here, the logical threshold value VLA of the inverter 101 in the first stage of the input buffer circuit is designed to satisfy V r t < V L 7 < VI H.

Generally, the logic threshold value V,a is designed to be an intermediate voltage between the low level input voltage value VIL and the high level input voltage value Vr□, for example, around (0.8V + 2.2V)/2 = 1.5V. Ru.

[Problem to be solved by the invention]

However, in such conventional input buffer circuits, there have been many reports of malfunctions of internal circuits due to power supply noise generated during data output. This power supply noise is generated when charging and discharging the output load capacitance. In order to achieve high-speed access, the output load capacitance is also charged and discharged at high speed, making it impossible to reduce power supply noise.

Therefore, in the conventional input buffer circuit, malfunctions due to power supply noise occur as shown below.

Table 3 is a diagram showing variations in the reference voltage and each logic threshold of the conventional input buffer circuit. FIG. 4 is a table showing truth values of a conventional input buffer circuit.

(Hereinafter, this page margin) Taking as an example the case where the common potential SS fluctuates during data output, Table 3 shows an example of voltage fluctuation, and Table 4 shows a truth table.

Here, the common potential value VSS fluctuates, and the common potential value v3,
1, the logical threshold V L T of the design value of the inverter 101 becomes the logical threshold V L T l
descend to As a result, if VLTI < VIL, the large power buffer circuit 100 cannot output a low level. Therefore, if the input level is low, the output will fluctuate to high level.

On the other hand, the common potential VSS fluctuates, and the common potential value V 5 S
2, the logical threshold VLT of the design value of the inverter 101 also increases to the logical threshold V21.2. rise to

As a result, if VLT2 > V 1s, the address buffer circuit cannot output a high level. Therefore, if the input level is high, the output will fluctuate to low level.

Note that the amplitude of input voltage IN (VIHVLa) or (V
It is obvious that the smaller LT-V□, ) is, the more likely the input buffer circuit will malfunction.

As described above, the conventional address buffer circuit has a small input voltage amplitude, and the inverter 101 due to power supply noise.
The disadvantage is that malfunctions are likely to occur due to fluctuations in the logic threshold voltage LT.

The present invention solves the above-mentioned drawbacks, and aims to provide a high-power buffer circuit that can increase the noise margin and operates stably against power supply noise.

[Means to solve the problem]

The present invention includes a first inverter that inputs an input voltage and outputs a low level value or a high level value based on a logic threshold, the first inverter having a gate connected to the input voltage and a source a first one-conducting enhancement type transistor connected to a power supply voltage, and a second opposite-conducting enhancement type transistor having a gate connected to said input voltage, a source connected to a common potential, and a drain connected to the drain of said transistor. An input buffer circuit comprising: outputs a high level value when the common potential is above a first predetermined value or when the power supply voltage is below a second predetermined value; and outputs a high level value when the common potential decreases or the power supply voltage is a first detection means that outputs a low level value when the common potential rises; and a first detection means that outputs a low level value when the common potential is below a first predetermined value or the power supply voltage is above a second predetermined value; a second detection means that outputs a high level value when the power supply voltage rises or the power supply voltage decreases; a second one-conductivity enhancement type transistor whose drain or source is connected to the output of the first inverter; a second one-conductivity enhancement transistor whose gate receives the output value of the second detection means; whose source or drain is connected to the common potential; or a second opposite conductivity enhancement type transistor whose source is connected to the output of the first inverter.

Further, in the present invention, the first detecting means includes a second inverter which is configured identically to the first inverter and has the same logical threshold value, and a second inverter which is configured identically to the first inverter and has the same logical threshold value. detects whether the output values of the second and third inverters are in phase or out of phase, and outputs a high level value when they are in phase. and a first control circuit that outputs a low level value when the phase is reversed; an inverter, a fifth inverter which is configured identically to the first inverter and has a logic threshold value higher than that, and whether the output values of the fourth and fifth inverters are in phase or out of phase. and a second control circuit that detects and outputs a low-level value when the phase is in-phase and outputs a high-level value when the phase is opposite.

[Effect]

The first detection means outputs a high level value when the common potential is above a first predetermined value or the power supply voltage is below a second predetermined value, and outputs a low level value when the common potential drops or the power supply voltage rises. Output the level value. The second detection means outputs a low level value when the common potential is below a first predetermined value and the power supply voltage is above a second predetermined value, and outputs a high level value when the common potential increases or the power supply voltage decreases. Output. The second one-conductivity enhancement type transistor inputs the output value of the first detection means to its gate,
The second opposite conductivity enhancement type transistor inputs the output value of the second detection means to its gate to prevent fluctuations in the logic threshold due to power supply noise.

In addition, the first detection means detects whether the output values of the second and third inverters are in phase or in phase with each other in the first control circuit, and outputs a high level value when the output values are in phase, and a low level value when the output values are in phase. A value of , when the phase is reversed, a high level value is applied to the gate of the second opposite conductivity enhancement type transistor to detect power supply noise with high sensitivity.

As described above, the noise margin can be increased and stable operation can be achieved against power supply noise.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of an input buffer circuit according to an embodiment of the present invention. In FIG. 1, the input buffer circuit includes an inverter 101 as a first inverter that inputs an input voltage IN and outputs a low level value or a high level value based on a logic threshold, and the inverter 101 has a gate. A P-channel enhancement type transistor QP1 as a first one-conductivity enhancement type transistor connected to the input voltage IN and whose source is connected to the power supply voltage CC.
and an N-channel enhancement type transistor QN as a second common potential enhancement type transistor whose gate is connected to the input voltage IN, whose source is connected to the common potential SS, and whose drain is connected to the drain of the P-channel enhancement type transistor QP. including. An output voltage OUT is output from the operation of inverter 101 via inverter 108.

Here, the feature of the present invention is that the detection circuit 110 is used as a first detection means that outputs a high level value as the control signal SI when the common potential SS is equal to or higher than a predetermined value, and outputs a low level value as the control signal SI when the common potential SS decreases. A detection circuit 120 serves as a second detection means that outputs a high level value as the control signal S2 when the common potential SS is below a predetermined value, and a low level value when it rises, and an output value of the detection circuit 110. A P-channel enhancement type transistor Q P 7 is used as a second monoconductive enhancement type transistor having a gate inputted with the control signal S1, a source connected to the power supply voltage CC, and a drain connected to the output of the inverter 101 , and the output of the detection means 120 . An N-channel enhancement type transistor Q N q is provided as a second opposite conductivity enhancement type transistor whose gate receives a control signal S2 as a value, whose source is connected to the common potential SS, and whose drain is connected to the output of the inverter. be.

The detection circuit 110 also includes an inverter 102 as a second inverter that is configured identically to the inverter 101 and has the same logical threshold channel as that of the inverter 101;
Inverter 103 is configured as a third inverter having a logic threshold value lower than that of the third inverter, and detects whether the output values of inverter 102103 are in phase or in opposite phase, and outputs a high level when they are in phase. The detection circuit 120 includes a control circuit 108 as a first control circuit that outputs a level value and a low level value when the phase is reversed as a control signal S1. inverter 104 as a fourth inverter having the same value as that of inverter 104, inverter 105 as a fifth inverter configured identically to inverter 101 and having a logic threshold value higher than that, and inverter 104.1.
A control circuit 10 serves as a second control circuit that detects whether the output values of 05 are in phase or out of phase, and outputs a low level value when they are in phase, and a high level value when they are out of phase, as a control signal S2.
9.

The operation of the address buffer circuit having such a configuration will be explained. Table 1 is a table showing variations in the reference voltage and each logic threshold of the address buffer circuit of the present invention. Table 2 is a table showing truth values of the address buffer circuit of the present invention.

(The following is the margin of this page) -6: In FIG. 1, the dimensions (gate width) of a transistor are shown as a design example. Dimension ratio WP/ of P-channel transistor and N-channel transistor
By W, , the logical threshold voltage of the inverter can be arbitrarily designed.

First, the operation of the detection circuit 110 will be explained.

The inverter 102 has the same configuration as the inverter 101 in the first stage of the address buffer circuit, and has a designed logical threshold value VLT of, for example, 1.5V.

On the other hand, the inverter 103 is designed to have lower logical threshold values V and T than the inverter 102, for example, 1.2V.

Here, a case will be described in which the low-level input voltage value v)L is set to 1.1v and the common potential value VSS drops to the common potential value v3,1.

The logic threshold value VLT of the inverter when the reference voltage SS drops to the common potential value V SS l is the inverter 10
2 The logic threshold VLjl (= 1.3v) 2. In the inverter 103, the logic threshold VLT, (= 1.
OV).

As a result, 1, OV<VrL=1. IV<1.3V, and the output (expected high level) of the inverter 103 changes to a low level. That is, the logical threshold value V of the inverter
The lower the value of 14, the smaller the operating margin with respect to the low-level input voltage value VIL, and the more likely malfunctions will occur. (The inverter 103 detects power supply noise with higher sensitivity than the inverter 102.) Note that the common potential SS is the common potential value V
If it returns to sS, the inverter's logical threshold voltage L
T also returns to the logic threshold VLT, and inverter 102.
103 outputs the expected value high level. (Vrt
= 1. lv<1.2V<1.5V) Next, the operation of the detection circuit 120 will be similarly described.

Inverter 105 is designed to have a higher logical threshold VLT than inverter 104, for example, 1.8V.

Here, a case is shown in which the high level input voltage value V+)I is set to 1.9V and the common potential SS rises to the common potential value V5g,2.

In the inverter 104, the logical threshold V L 72 when the common potential S-8 rises to the common potential value v3,2 is 1.
In 7■, the inverter 105 performs 2. Suppose that the temperature rises to Ov. As a result, 1.7V<VIM=1.9V<2.0V, and the output (expected low level) of the inverter 105 changes to a high level. That is, the logical threshold value V of the inverter
The higher L7 is, the smaller the operating margin is with respect to the high level input voltage value VB, and malfunctions are more likely to occur. (The inverter 105 detects power supply noise with higher sensitivity than the inverter 104.) Note that the common potential SS is the common potential value V
When it returns to SS, the logic threshold voltage of the inverter also returns to the logic threshold V,A, and both inverters 104 and 105 output the expected low level. (1,5V<1
．． 8V<VIH=1.9V) Next, the control circuits 10g and 109 will be explained by classifying them into items (1) to (2) as follows.

■Input voltage IN is at a low level and common potential SS does not fluctuate when Vrt=1. Ov<1.2V).

Output signals D0+, DO2, D of detection circuits 110 and 120
o3 is all at a high level. At this time, by setting the control signal Sl to high level and the control signal S2 to low level, P channel transistors Q P7 and N
Both channel transistors QN become non-conductive.

As a result, the logical threshold channel voltage LT of the inverter 101 becomes 1.5V, and VIL=1. Since IV< 1.5V, the address buffer circuit has the expected value! Output the level.

■ Input voltage IN is high level and common potential SS does not fluctuate (1.8V<VIL<1.9V).

Output signal. 1, DO2, and DO3 are all at a low level. At this time, by setting the control signal S1 to a high level and the control signal S2 to a low level, the inverter 10
The logic threshold voltage LT of 1 is 1.5V, and since l,5V<VTR=1.9V, the address buffer circuit outputs the expected high level.

■ When the input voltage IN is low level and the common potential SS fluctuates (
), the logical threshold voltage LT of the inverter also changes as described above, for example, 1, OV(inverter 1103)<V, L=1. IV<
1.3V (Inverter IOL 102) <1.6V
(Inverter 105), the output signal will be the same. 1.D
O3 outputs a high level signal. 2 is a low level.

At this time, if both the control signals St and S2 are set low and the Berni setting is performed, the P-channel enhancement type transistor QP becomes conductive, and the N-channel enhancement type transistor QN
7 becomes non-conductive.

As a result, as the common potential SS falls, the logical threshold voltage of the inverter, which has dropped to 1.3V, rises and is set to, for example, 1.5V.

That is, even if the common potential SS drops to the common potential value V s s +, the logical threshold value V,a of the inverter ]0].

can be set to a desired value, it is possible to realize an input huffer circuit with a large noise margin.

In addition, VIL=1.1V<1.5V The output of a larger power buffer circuit is stable at a lower level.

■ When the input voltage IN is at a high level and the common potential SS rises, the logic threshold voltage LT of the inverter changes, and 1.4 V (inverter 103) < 1.7 V (inverter 101, 102). <V+o=1.9V
<2. If it becomes OV (ear/'-ta 105), the output signal will be output. 1.D0□ is low and Benobe output signal. 3 is a high level.

At this time, if control signals s, , and S2 are both set to a high level, the P-channel enhancement type transistor Q P q becomes non-conductive, and the N-channel enhancement type transistor Q N7 passes 11 through 6 degrees.As a result, the common potential SS As the voltage increases, the logic threshold voltage LT of the inverter 101, which has increased to 1.7V, decreases and is set to, for example, 1.5V.

That is, even if the common potential SS rises to the common potential value v8,2, the logical threshold value V L 72 of the inverter 101
Since can be set to a desired value, a high-power buffer circuit with a large noise margin can be realized.

In addition, 1.5V<Vrs=1.9V Therefore, the output of the input buffer circuit is stabilized at a high level.

For the sake of explanation, power supply noise has been limited to fluctuations in the common potential above, but the same meaning can be obtained even if this is replaced with fluctuations in the power supply voltage.

FIG. 2 is a block diagram of a feedback inverter including a high-power buffer circuit according to the present invention. In FIG. 2, the same parts as in FIG. 1 are indicated using the same reference numerals and will be explained. The feedback inverter 200 uses the voltage of the digit line as the gate input voltage, but since the amplitude of the voltage of the digit line is minute, the conventional phytoback inverter is likely to malfunction due to power supply noise.

Therefore, in this embodiment as well, the above-mentioned detection circuit 11
The control signals S, ,S created by 0.120.

This allows the logic threshold of the feedback inverter 200 to be made variable, thereby providing a circuit with a large noise margin.

In the above example, the P-channel enforcement transistor is replaced with an N-channel enforcement transistor, the N-channel enforcement transistor is replaced with a P-channel enforcement transistor, and the N source polarity is reversed. By doing so, the present invention can be implemented in the same manner.

〔Effect of the invention〕

As described above, the present invention has the excellent effect of increasing the noise margin and operating stably against power supply noise.

Lock configuration diagram.

FIG. 2 is a block diagram of a feedback inverter including the input buffer circuit of the present invention.

FIG. 3 is a block diagram of a conventional address buffer circuit.

101-106... Inverter, 108, 109.
...Control circuit, 110.120...Detection circuit, 200
...Feedback inverter, CC...power supply voltage, Do% DOI, DQ2, DO3-...output signal, QN, QN+ ~QNq-N channel enhancement type transistor, QPSQP, ~Q
P,...P-channel enhancement type transistor, S, ,S2...control signal, SS...common potential,
IN...Input voltage, OUT...Output voltage.

Claims (1)

[Claims] 1. A first inverter that inputs an input voltage and outputs a low-level value or a high-level value based on a logic threshold, the first inverter having a gate that receives the input voltage. a first one-conducting enhancement-type transistor connected to said input voltage and whose source is connected to the supply voltage, and a second opposite whose gate is connected to said input voltage and whose source is connected to a common potential and whose drain is connected to the drain of said transistor. In an input buffer circuit including a second opposite conductivity enhancement type transistor connected to the drain of the conductivity enhancement transistor, when the common potential is equal to or higher than a first predetermined value or the power supply voltage is equal to or lower than a second predetermined value, the input buffer circuit has a high level value. a first detection means that outputs a low level value when the common potential decreases or the power supply voltage increases; a second detection means that outputs a low level value when the common potential is higher than a predetermined value and outputs a high level value when the common potential increases or the power supply voltage decreases; and an output value of the first detection means. a second one-conductivity enhancement type transistor whose source or drain is connected to the power supply voltage and whose drain or source is connected to the output of the first inverter; and a second opposite conductivity enhancement type transistor having a gate input thereto, a source or drain connected to the common potential, and a drain or source connected to the output of the first inverter. 2. The first detection means includes a second inverter that is configured identically to the first inverter and has a logical threshold value that is the same as that of the first inverter, and a second inverter that is configured identically to the first inverter and has a logical threshold value that is the same as that of the first inverter. detects whether the output values of the second and third inverters are in phase or out of phase, outputs a high level value when they are in phase, and outputs a high level value when the output values of the second and third inverters are in phase. a first control circuit that outputs a low level value when the second detecting means is configured to have the same logic threshold as the first inverter; Detects whether the output values of the fourth and fifth inverters are in phase or out of phase with a fifth inverter that is configured identically to the first inverter and has a logic threshold value higher than that, and when they are in phase. 2. The input buffer circuit according to claim 1, further comprising a second control circuit that outputs a low level value and outputs a high level value when the phase is reversed.