WO2003034498A1 - Stacked switchable element and diode combination - Google Patents

Stacked switchable element and diode combination Download PDF

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Publication number
WO2003034498A1
WO2003034498A1 PCT/US2001/032380 US0132380W WO03034498A1 WO 2003034498 A1 WO2003034498 A1 WO 2003034498A1 US 0132380 W US0132380 W US 0132380W WO 03034498 A1 WO03034498 A1 WO 03034498A1
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WO
WIPO (PCT)
Prior art keywords
switchable element
diode
layer
switchable
stop layer
Prior art date
Application number
PCT/US2001/032380
Other languages
French (fr)
Inventor
Howard M. Branz
Qi Wang
Original Assignee
Midwest Research Institute
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Filing date
Publication date
Application filed by Midwest Research Institute filed Critical Midwest Research Institute
Priority to US10/240,838 priority Critical patent/US7067850B2/en
Priority to PCT/US2001/032380 priority patent/WO2003034498A1/en
Priority to JP2003537122A priority patent/JP2005506703A/en
Publication of WO2003034498A1 publication Critical patent/WO2003034498A1/en
Priority to US10/555,766 priority patent/US8203154B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8615—Hi-lo semiconductor devices, e.g. memory devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of the switching material, e.g. post-treatment, doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Definitions

  • This invention relates to integrated circuit devices in general and more specifically to a switchable element and diode combination embodied in a stacked structure.
  • Background Art Semiconductor devices are well-known in the art and have been used for decades in electronic systems to perform a wide variety of tasks. While many different types of semiconductor devices exist and are being used, most involve the transport of charge carriers (e.g., electrons) across one or more junctions or interfaces formed within the semiconductor material. The junctions typically involve an interface between two different types of semiconductor material, such as p-type and n-type material, although other types of semiconductor materials may also be used.
  • charge carriers e.g., electrons
  • semiconductor devices such as diodes, transistors, and silicon controlled rectifiers, having a wide range of functions and operating characteristics may be formed from semiconducting materials.
  • semiconductor materials include, but are not limited to, silicon, gallium arsenide, aluminum gallium arsenide, and gallium arsenide indium phosphide. Because of the wide range of devices, functions, and operating characteristics that may be created with such semiconducting materials, new devices and uses for semiconducting materials are still being developed, even today. Often, such newly developed devices prove to be significant improvements over earlier devices, either in terms of performance, size, or some combination of the two.
  • a device may comprise a semiconductor diode and a switchable element positioned in stacked adjacent relationship so that the semiconductor diode and the switchable element are electrically connected in series with one another.
  • the switchable element is initially in a low-conductance or "OFF” state and may be switched to a high-conductance or "ON” state in response to the application of a forming current to the switchable element.
  • Also disclosed is a method of forming a device that comprises the steps of: Forming a diode device from semiconducting material; forming an intermediate layer in stacked adjacent relationship with the diode device; and depositing a metallic layer on the intermediate layer, the intermediate layer and the metallic layer forming a switchable element that is initially in a low-conductance or "OFF" state and that may be switched to a high-conductance or "ON” state in response to the application of a forming current to the switchable element, the switchable element being in electrical series with the diode device.
  • Figure 1 is a schematic sectional view of a first embodiment of a device according to the present invention
  • Figure 2 illustrates current density/voltage curves of an unformed device and a formed device
  • FIG 3 is a schematic sectional view of a second embodiment of a device according to the present invention. Best Modes for Carrying Out the Invention
  • a device 10 according to one embodiment of the invention is shown in Figure 1 and may comprise a semiconductor diode device 12 and a switchable element 14 positioned in stacked adjacent relationship so that the semiconductor diode 12 and switchable element 14 are electrically connected in series.
  • the switchable element 14 is initially in the low-conductance or "OFF' state and may be switched to a high-conductance or "ON" state in response to the application of a forming current to the switchable element 14.
  • the forming current may be used to "close” (i.e., place in the high-conductance or ON state) the switchable element 14.
  • the series combination of the semiconductor diode 12 and switchable element 14 allows the state (e.g., high- or low- conductance) of device 10 to be conveniently “written” and “sensed” or “read,” thereby allowing the device 10 to be used in electronic memory systems.
  • one embodiment 10 of the device may comprise a semiconductor diode device 12 in contact with an electrical contact 16.
  • the diode device 12 may comprise any of a wide range of structures and operating characteristics for semiconductor diodes that are now known in the art or that may be developed in the future.
  • the semiconductor diode device 12 may comprise an n + -i-p device having a highly doped n-type (i.e., n + ) layer 18, an intrinsic or lightly doped layer 20, and a p-type (i.e., p) layer 22. All three layers 18, 20, and 22 may be fabricated from microcrystalline silicon, although amorphous silicon may also be used.
  • the contact 16 may comprise stainless steel, although other materials may also be used, as will be described in greater detail below.
  • the switchable element 14 may comprise a metal layer 24 and an intermediate layer 26 in positioned stacked adjacent relationship with the diode device 12. The arrangement is such that the switchable element 14 is electrically connected in series with the diode device 12. Stated another way, the diode device 12 and switchable element 14 comprise a monolithic, series-connected stack.
  • the metal layer 24 of switchable element 14 may comprise silver, although other metals may be used.
  • the intermediate layer 26 may comprise either an intrinsic semiconducting layer, a p-type semiconducting layer, or some combination of intrinsic and p-type semiconducting material. Alternatively, the intermediate layer 26 may comprise an insulator, such as a polymer material, as will be described in greater detail below.
  • the intermediate layer 26 comprises p-type amorphous silicon passivated with hydrogen (i.e., p-a-Si:H), although other materials may also be used.
  • a stop layer 28 be formed or positioned between the semiconductor diode device 12 and the switchable element 14.
  • the stop layer 28 helps to prevent the diode device 12 from being damaged (e.g., shorted) during the application of the forming current to the switchable element 14.
  • the stop layer 28 may comprise a metallic or an extremely thin insulating layer.
  • the stop layer 28 may comprise an appropriately doped and passivated amorphous silicon material. Still other materials may also be used for the stop layer 28, as will be described in greater detail below.
  • the diode portion 12, switchable element portion 14, and optional stop layer 28 of device 10 may be fabricated in accordance with any of a wide variety of processes that are well-known in the art or that may be developed in the future that are or would be suitable for fabricating the various layers comprising each portion 12, 14, and 28. Consequently, the present invention should not be regarded as limited to any particular fabrication processes or techniques to fabricate the device 10.
  • the various layers of the device may be fabricated by chemical vapor deposition (CVD), for example, hot-wire CVD or plasma-enhanced CVD.
  • CVD chemical vapor deposition
  • the switchable element 14 is initially in the low-conductance or OFF state, but may be placed in the high-conductance or ON state in response to the application to the switchable element 14 of a forming current. Consequently, the switchable element 14 functions like an "anti-fuse" in that it closes or becomes more conductive after the application of the forming current. This is in contrast to a conventional fuse which opens in response to the application to the fuse of an excessive current.
  • the impedance of the switchable element is relatively high (e.g., typically on the order of tens to hundreds of megaohms (M ⁇ ) in one embodiment.
  • M ⁇ megaohms
  • the impedance of the semiconductor switch 14 is several orders of magnitude lower than the impedance of the switchable element in the low-conductance state.
  • the impedance of the switchable element 14 is on the order of hundreds to thousands of ohms ( ⁇ ).
  • the absolute impedance of the switchable element 14 in either state is less important than is the magnitude of the impedance difference between the two states. That is, the difference in the impedances between the high- and low -conductance states should be sufficient to allow for the reliable determination of the state of the device 10.
  • the switchable element 14 When the switchable element 14 is first formed or fabricated it is in the low-conductance or OFF state. That is, the switchable element 14 has a relatively high impedance and passes very little current.
  • the state of the switchable element 14 may be changed to the high-conductance or ON state by applying a forming current across the switchable element 14.
  • the switchable element 14 may be changed from the low-conductance or OFF state to the high-conductance or ON state by applying a forming current of sufficient magnitude and for sufficient time in the manner that will be described below.
  • the filament growth theory is supported by observations that if the forming current and time of application are not carefully controlled, the diode element 12 will become shorted. It is believed that such diode shorting is the result of continued filament growth through the diode element 12. Accordingly, it is generally preferred, although not required, to provide the stop layer 28 between the switchable element 14 and the diode element 12. The stop layer 28 reduces the likelihood that the diode element 12 will become shorted during the forming process.
  • the device 10 may be written to as follows. Assuming that the device 10 has been fabricated in the manner briefly described above, the switchable element 14 will be in the low-conductance or OFF state. That is, the device 10 will act electrically in a manner akin to an open circuit, with little current flowing in response to the application of a potential voltage across the series combination of the diode 12 and switch 14. That is, the device 10 will have a current-voltage characteristic substantially as shown by curve 32 in Figure 2. Of course, the device 10 may be utilized in this state, if desired. For example, if the device 10 comprises an individual cell or element of an electronic memory array, the low-conductance state may be made to correspond to a selected binary state (e.g.,
  • a forming current can be applied across the series combination of the diode 12 and switch element 14.
  • the polarity of the forming current is such that the diode element 12 of device 10 is biased in the forward direction.
  • the application of the forming current causes the switchable element 14 of the device 10 to change to the high- conductance or ON state.
  • the device 10 In the high-conductance state, the device 10 will have a current-voltage characteristic substantially as shown by curve 34 in Figure 2.
  • the curve 34 is similar to the electrical characteristics of the diode element 12, since the switchable element 14 is relatively conductive. Accordingly, the state of the device 10 can be detected or "read” by forward biasing the diode element 12. If the diode element 12 conducts (i.e., passes current) then the switchable element
  • the high-conductance state may correspond to the other binary state (e.g., a 1 or a 0).
  • a significant advantage of the device 10 according to the present invention is that it provides a series combination of an electronic switch and diode in a stacked arrangement. Accordingly, the device 10 of the present invention eliminates the need to provide a lateral conduction path between the two devices, as would be required if the two devices were fabricated in side-by-side (as opposed to the stacked) relationship. As a result, the device 10 would readily lend itself to the simplified manufacture of high density memory arrays, since the lithography steps required to form a separate conductive path between the diode and switch may be eliminated.
  • the device 10 is shown and described herein as it may be used in a semiconductor memory array to store binary (i.e., two state) data, it is not limited to use in such applications. Indeed, since the device of the present invention is functionally similar to a switch and diode connected in series, the present invention may be used in any of a wide range of applications wherein such functionality is desired. Accordingly, the device of the present invention should not be regarded as limited to the particular applications shown and described herein.
  • a first embodiment 10 of a device is illustrated in Figure 1 and may comprise a semiconductor diode 12 and a switchable element 14 positioned in stacked adjacent relationship so that the semiconductor diode 12 and switchable element 14 form a monolithic, series-connected stack.
  • the various elements i.e., the semiconductor diode 12 and switchable element 14
  • the present invention should not be regarded as limited to a device 10 comprising any particular configuration or shape.
  • the device 10 is fabricated so that it has a generally square shape or configuration, with each side of the square having a length of about 10 micrometers ( ⁇ m).
  • the semiconductor diode element 12 of the device 10 may comprise any of a wide range of diode types having any of a wide range of structures suitable for producing a diode device 12 having any of a wide range of electrical characteristics that would be required or desired for any particular application.
  • diode structures and types that may be used with the present invention include, but are not limited to, diodes comprising n-i-p structures or p-i-n structures, diode structures involving conventional n-p or p-n structures can also be used, provided such diodes are fabricated from crystalline silicon or other crystal materials.
  • the diodes may be of any of a wide range of types, such as, for example, "conventional" rectifying diodes, Schottky diodes, tunnel diodes, or even light emitting diodes. Consequently, the present invention should not be regarded as limited to any particular diode structure having any particular electrical characteristics.
  • the semiconductor diode device 12 comprises an n + -i-p device having a highly doped n-type layer 18, an intrinsic (or a very lightly doped) layer 20, and a p-type layer 22. All three layers 18, 20, and 22 are fabricated from microcrystalline silicon, although amorphous silicon may also be used.
  • the thicknesses of the various layers 18, 20, and 22 comprising diode device 12 are not particularly critical and may comprise any of a wide range of thicknesses depending on the electrical characteristics and other performance parameters that may be required or desired in any particular application.
  • the n + layer 18 may have a thickness of about 60 nano-meters (nm)
  • the thicknesses of the intrinsic layer 20 and the p-layer 22 may be about 260 nm and 60 nm, respectively.
  • the layers 18, 20, and 22 comprising diode device 12 may be formed by any of a wide range of processes that are now known in the art or that may be developed in the future that are or would be suitable for forming the layers 18, 20, and 22 to produce the diode device 12. Accordingly, the present invention should not be regarded as limited to any particular process for forming the various layers of the diode device 12. However, by way of example, in one preferred embodiment, the various layers 18, 20, and 22 of diode device 12 are formed by chemical vapor deposition.
  • the diode device 12 may be provided with a suitable electrical contact, such as contact 16, to allow one of the electrodes (i.e., either the anode or the cathode, as the case may be) of the diode device 12 to be electrically connected to an external circuit and/or device.
  • a suitable electrical contact such as contact 16 to allow one of the electrodes (i.e., either the anode or the cathode, as the case may be) of the diode device 12 to be electrically connected to an external circuit and/or device.
  • the contact 16 contacts the cathode (i.e., n + layer 18) of diode device 12.
  • the contact 16 may comprise any of a wide range of materials (e.g. , metals or doped semiconductors) that would be suitable for the intended application.
  • any of a wide range of interface layers may be positioned between the diode 12 and the contact 16 if required or desired for the particular application. Consequently, the present invention should not be regarded as limited to contacts comprising any particular material or to the presence or absence of any interface layers or material between the diode 12 and the contact 16.
  • the contact 16 comprises stainless steel.
  • other materials, such as aluminum, may also be used, as would be obvious to persons having ordinary skill in the art after having become familiar with the teachings of the present invention.
  • the particular process used to form the diode device 12, as well as the exact compositions and structural characteristics of each of the various layers (e.g., 18, 20, and 22) of the diode device 12 are not particularly critical and may comprise any of a wide range of forming processes, compositions and structural characteristics that would be suitable for producing a diode device having any of a wide range of desired electrical characteristics.
  • certain electrical characteristics of diode devices that are dependent on such fabrication parameters include, but are not limited to forward turn-on voltage, forward series resistance, forward breakdown current, reverse breakdown voltage, reverse shunt resistance, and lateral resistance between elements.
  • Thecontact 16 maycomprise the substrate itself which supports the device 10.
  • the contact 16 may be supported by a separate, preferably insulating, substrate 36, such as glass, ceramic, or plastic. See Figure 1.
  • any of a wide range of interface layers may be positioned between the contact 16 and the substrate 36, as may be required or desired in the particular application.
  • an interface layer or material between the contact 16 and the substrate 36 may be desirable to provide for improve adhesion of the contact 16 to the substrate 36.
  • the use of an insulating substrate 36 is advantageous if the device 10 comprises an individual cell or element in an array of cells, such as may be provided for in an electronic memory circuit.
  • an insulating substrate 36 provides a means for electrically insulating a contact 16 associated with a single "row” or “column” of cells (i.e., devices 10) from the contacts associated with adjacent rows or columns of cells.
  • the switchable element 14 may comprise any of a wide range of structures that are well- known in the art or that may be developed in the future capable of being switched between a non- conductive or "OFF' state and a conductive or “ON” state.
  • the switchable element 14 may comprise any of the structures and devices disclosed in U.S. Patent No. 4,684,972 issued on August 4, 1987, and entitled "Non- Volatile Amorphous Semiconductor Memory Device Utilizing a
  • the switchable element 14 may comprise a metal layer 24 and an intermediate layer 26 positioned in stacked adjacent relationship.
  • the switchable element 14 may be positioned in stacked adjacent relationship with the diode device 12 so that the diode device 12 and switchable element 14 are electrically connected in series.
  • the mechanism or mechanisms by which the switchable element 14 may be switched between at least two states are not well understood at this time.
  • the application of the forming current results in the formation or growth through the intermediate layer 26 of one or more filaments (represented schematically in Figure 1 at 30) from the metal layer 24. This theory is supported by experimental evidence which indicates that certain metals for the metal contact 24 work better than others in causing the switchable element 14 to operate in either the conductive state or the non-conductive state.
  • Ag and V appear to diffuse easily through a semiconducting intermediate layer 26 comprising hydrogenated (i.e., passivated) amorphous silicon (a-Si:H), whereas Cr appears to be less likely to diffuse through such a semiconducting intermediate layer 26. Consequently, it is generally preferable to fabricate the metal layer 24 from either Ag or V, especially where the intermediate layer 26 comprises a-Si:H.
  • the thickness of the metal layer 24 is not particularly critical, but should be sufficient to provide the required mechanical strength and durability that may be required or desired for the particular application. Consequently, the present invention should not be regarded as limited to a metal layer 24 having any particular thickness. However, by way of example, in one preferred embodiment, the metal layer 24 may have a thickness of about 60 nm.
  • the metal layer 24 may be deposited by any of a wide variety of processes that are well-known in the art or that may be developed in the future that would be suitable for forming such metallic layers. By way of example, in one preferred embodiment, the metal layer 24 is formed by evaporation, although other processes (e.g., sputter deposition) may also be used.
  • the intermediate layer 26 may be deposited directly on the diode device 12 and may comprise either a semiconducting material or an insulating material. It will normally be best if the filament 30 grows through the layer 26 more readily than through the diode device 12. Alternatively, and as will be described in greater detail below a supplemental layer, such as a stop layer 28, may be formed between the intermediate layer 26 and the diode device 12.
  • the intermediate layer 26 may comprise any of a wide range of semiconducting materials, such as amorphous silicon passivated with hydrogen (a-Si:H) and may be either doped or undoped. In the embodiment shown and described herein, the intermediate layer 26 comprises p-type passivated amorphous silicon.
  • the intermediate layer 26 may comprise intrinsic a-Si:H or even a p-i, p-i-n, or n-i-p structure of a-Si:H or of microcrystalline silicon.
  • other materials such as those described in U.S. Patent Nos. 4,684,972 and 5,360,981, may also be used.
  • the intermediate layer 26 may comprise an insulating material (e.g., any of a wide range of polymers or other organic materials). Insulating materials that may be used include, but are not limited to alloys of hydrogen-passivated amorphous silicon with carbon or with germanium. Alternatively, microcrystalline silicon may also be used.
  • the intermediate layer may also be formed from conventional photoresist films.
  • the intermediate layer 26 may be deposited by any of a wide variety of processes that are well-known in the art or that may be developed in the future that would be suitable for forming an intermediate layer 26 comprising the desired material.
  • the semiconducting intermediate layer 26 is formed by chemical vapor deposition, although other processes may also be used.
  • the thickness of the intermediate layer 26 may be important depending on whether a supplemental layer, such as stop layer 28, is positioned between the switchable element 14 and the semiconductor diode device 12. Generally speaking, the thickness of intermediate layer 26 should be sufficient to prevent unintentional diffusion of the metal layer 24 through the intermediate layer 26. Such unintentional diffusion may cause the switchable element 14 to change from the low- conductance to the high-conductance state. However, the thickness of the intermediate layer 26 should not be so great that it is difficult to intentionally change the state of the switchable element 14 in response to the forming current. In accordance with the foregoing considerations, we have found that a semiconducting intermediate layer 26 having a thickness in the range of about 10 nm to about 500 nm (100 nm preferred) provides good results.
  • a stop layer 28 between the intermediate layer 26 of switchable element 14 and the diode 12.
  • the stop layer 28 reduces the likelihood that the diode device 12 will be shorted during the application of the forming current to the switchable element 14. That is, in accordance with the theory that the switchable element 14 is made conductive due to the growth of one or more conductive filaments 30 through the intermediate layer 26, the presence of the stop layer 28 retards the growth of the filament 30 by an amount sufficient to allow the forming current to be removed before the filament contacts or grows through the diode device 12. Alternatively, and as will be described below, careful control of the forming current may allow the device 10 to be operated satisfactorily in the absence of a supplemental or stop layer 28.
  • the stop layer 28 comprises a highly doped n-type semiconducting material, such as hydrogen passivated amorphous silicon.
  • n-type semiconducting material such as hydrogen passivated amorphous silicon.
  • other materials such as metals or thin insulating layers (e.g., silicon oxide or silicon nitride), may also be used in the manner that will be described in greater detail below.
  • the stop layer 28 may be deposited by any of a wide variety of processes that are well-known in the art or that may be developed in the future that would be suitable for forming such semiconducting layers.
  • the stop layer 28 is formed by chemical vapor deposition, although other processes may also be used. If the stop layer 28 comprises an insulating or undoped semiconducting material then the thickness of the stop layer should be carefully controlled. For example, thin stop layers 28 may reduce the ability to reliably stop filament growth (e.g, by removing the forming current) before the filament 30 shorts the diode device 12. On the other hand, excessive thickness of an insulating stop layer 28 may impede the flow of current between the switchable element 14andthediode 12, thereby making it difficult to read the state of the switch device 14.
  • the growth of the filament 30 should be terminated at a position within an insulating stop layer 28 that will allow electrons to "tunnel" through the remaining thickness of the stop layer 28.
  • Such a phenomenon is known in the art as "electron tunneling.”
  • the stop layer 28 comprises an insulator, it should have a thickness between about 0.5 nm and about 2 nm (1 nm preferred).
  • other thicknesses may be used provided they allow the switchable element 14 to be reliably written without shorting the diode 12 while also allowing sufficient current flow through the junction from the switchable element 14 and to determine whether the switch device 12 is in the ON state or the OFF state.
  • the stop layer 28 may also comprise a relatively "stable" metal (i.e., a metal having low diffusivity through the adjacent layers 22 and 26) such as Cr.
  • a stop layer 28 comprising a metallic material functions in a manner similar to the semiconducting stop layer in that it allows the filament growth to be more easily terminated before the filament 30 contacts the diode device 12.
  • Such a metallic stop layer may be fabricated in accordance with any of a wide range of processes that are now known in the art or that may be developed in the future that are or would be suitable for depositing metallic layers. Consequently, the present invention should not be regarded as limited to any particular fabrication process.
  • a metallic stop layer 28 may be formed by evaporation. Alternatively, other processes, such as sputter deposition, may also be used.
  • a metallic stop layer 28 is highly electrically conductive, it removes the concern of providing a low resistance path (such as by electron tunneling in the case of an insulating stop layer 28) between the filament 30 and the diode device 12. Consequently, a stop layer 28 fabricated from metal may be made thicker, if desired (compared with an insulating stop layer), in order to provide an enhanced margin against diode shorting by filament impingement.
  • a metallic stop layer 28 would need to be patterned (e.g., by means of lithography) if the device 10 is to comprise an individual cell or element of an array of devices 10. A patterned metallic stop layer 28 is required in such an application in order to prevent the metallic stop layer 28 from shorting out other memory cells in the array.
  • a stop layer 28 comprising a semiconducting material, such as thin n + -a-Si:H or an insulating stop layer, such as SiN x , will not usually need to be patterned in such an application. That is, the higher electrical resistance of a semiconducting stop layer is usually sufficient to prevent shorting and/or unacceptable cross-talk between adjacent memory cells.
  • the stop layer 28 from a semiconducting material (e.g., n + -a-Si:H) or an insulating material if the device 10 is to be used in an electronic memory array.
  • a semiconducting material e.g., n + -a-Si:H
  • the switchable element 14 When the device 10 is first formed or fabricated, the switchable element 14 is in the low- conductance or OFF state and will have a current-voltage characteristic substantially as shown by curve 32 in Figure 2. That is, the switchable element 14 has a relatively high impedance and passes very little current, much like an open switch. If it is desired to change the state of the device 10, a forming current can be applied across the series combination of the diode 12 and switchable element 14. The polarity of the forming current is such that the diode element 12 of device 10 is biased in the forward direction. The application of the forming current causes the switchable element 14 to change to the high-conductance or ON state. In the ON state, the device 10 will have a current- voltage characteristic substantially as shown by curve 34 in Figure 2.
  • the curve 34 corresponding to the high-conductance or ON state of switchable element 14 is similar to the electrical characteristics of the diode element 12 by itself.
  • the magnitude and duration of the forming current required to change the state of the switchable element 14 may vary depending on the particular materials used to form the device 10. Consequently, the present invention should not be regarded as limited to forming currents of any particular magnitudes, voltages, and durations.
  • the forming current may have a magnitude in the range of about 0.1 micro-amperes ( ⁇ A) to about 10 ⁇ A (1 ⁇ A preferred).
  • the forming current may be applied for durations in the range of about 1 nano-second (ns) to about 1 second, with faster times being preferable.
  • the forming processes may correspond to those disclosed in U.S. Patent Nos.4,684,972 and 5,360,981 if the switchable element 14 is fabricated in accordance with the teachings contained therein.
  • External electronic circuitry (not shown) connected to the device 10 can be made to recognize or differentiate between the changed current-voltage characteristics (i.e., I-V curves 32 and 34) of the device 10, thus determine whether the switchable element 14 is in the ON or OFF state.
  • the device 10 comprises one element in an array of such elements, such as may be the case if the device 10 comprises a portion of an electronic memory array, any element (e.g., device 10) in the array may be "read” by forward biasing the diode device 12 associated with desired element while reverse biasing the diodes associated with the other elements in the array.
  • the element conducts i .e., passes current
  • the element is in the high-conductance or ON state. This may be made to correspond to one of the states (e.g., "0" or "1") in a binary system.
  • a second embodiment 110 of a device according to the present invention is illustrated in
  • the second embodiment 110 is similar to the first embodiment 10 described above except that the positions of the diode device 112 and the switchable element 114 are reversed. That is, the switchable element 114 is positioned adjacent a supporting substrate 136 with the diode device 112 in stacked adjacent relationship with the switchable element 112 so that the two devices form a monolithic, series-connected stack.
  • the diode device 112 of the second embodiment 110 may comprise any of a wide range of structures and materials to provide any required or desired diode characteristic.
  • the diode device 112 comprises a p-i-n + device having a p-type layer 122, an intrinsic layer 120, and a highly doped n-type layer 118. All three layers 18, 20, and 22 are fabricated from microcrystalline silicon, although amorphous silicon may also be used.
  • a contact 116 may be formed adjacent to the n + layer 118.
  • the switchable element 114 may comprise any of the materials recited above for the switchable element 14 for the first embodiment 10 and may be fabricated in accordance with the methods and considerations discussed herein.
  • the switchable element 114 may comprise a metal layer 124 and an intermediate layer 126 positioned in stacked adjacent relationship.
  • the metal layer 124 may be fabricated on the support substrate 136.
  • the device 110 may be provided with a stop layer 128 or the stop layer 128 may be omitted if the formation of the filament 130 can be reliably controlled in the manner already described to avoid shorting the diode element 112.
  • a stop layer 128 may comprise either a semiconducting material (e.g., n + -a-Si:H), an insulating material, or a metallic material, whichever may be more advantageous for the intended application.

Abstract

A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship so that the semiconductor diode (12) and the switchable element (14) are electrically connected in series with one another. The switchable element (14) is switchable from a low-conductance state to a high-conductance state in response to the application of a forming voltage to the switchable element (14).

Description

STACKED SWITCHABLE ELEMENT AND DIODE COMBINATION
Contractual Origin of the Invention
The United States Government has rights in this invention pursuant to Contract No. DE-AC36- 99GO10337 between the U.S. Department of Energy and the Midwest Research Institute.
Technical Field
This invention relates to integrated circuit devices in general and more specifically to a switchable element and diode combination embodied in a stacked structure. Background Art Semiconductor devices are well-known in the art and have been used for decades in electronic systems to perform a wide variety of tasks. While many different types of semiconductor devices exist and are being used, most involve the transport of charge carriers (e.g., electrons) across one or more junctions or interfaces formed within the semiconductor material. The junctions typically involve an interface between two different types of semiconductor material, such as p-type and n-type material, although other types of semiconductor materials may also be used. In this manner, a wide range of semiconductor devices, such as diodes, transistors, and silicon controlled rectifiers, having a wide range of functions and operating characteristics may be formed from semiconducting materials. Commonly used semiconductor materials include, but are not limited to, silicon, gallium arsenide, aluminum gallium arsenide, and gallium arsenide indium phosphide. Because of the wide range of devices, functions, and operating characteristics that may be created with such semiconducting materials, new devices and uses for semiconducting materials are still being developed, even today. Often, such newly developed devices prove to be significant improvements over earlier devices, either in terms of performance, size, or some combination of the two. Unfortunately, however, such new devices often carry certain disadvantages, such as requiring additional manufacturing steps, or requiring enhanced lithography or forming techniques. As a result, such newly developed semiconductor devices often involve a balance between improved performance and increased difficulty of manufacture. Accordingly, any semiconductor device having improved performance and/or reduced size while at the same time involving simplified or reduced- cost manufacturing will represent a significant improvement in the state of the art. Disclosure of Invention
A device according to the present invention may comprise a semiconductor diode and a switchable element positioned in stacked adjacent relationship so that the semiconductor diode and the switchable element are electrically connected in series with one another. The switchable element is initially in a low-conductance or "OFF" state and may be switched to a high-conductance or "ON" state in response to the application of a forming current to the switchable element.
Also disclosed is a method of forming a device that comprises the steps of: Forming a diode device from semiconducting material; forming an intermediate layer in stacked adjacent relationship with the diode device; and depositing a metallic layer on the intermediate layer, the intermediate layer and the metallic layer forming a switchable element that is initially in a low-conductance or "OFF" state and that may be switched to a high-conductance or "ON" state in response to the application of a forming current to the switchable element, the switchable element being in electrical series with the diode device. Brief Description of the Drawings
Illustrative and presently preferred embodiments of the invention are shown in the accompanying drawings in which:
Figure 1 is a schematic sectional view of a first embodiment of a device according to the present invention; Figure 2 illustrates current density/voltage curves of an unformed device and a formed device; and
Figure 3 is a schematic sectional view of a second embodiment of a device according to the present invention. Best Modes for Carrying Out the Invention A device 10 according to one embodiment of the invention is shown in Figure 1 and may comprise a semiconductor diode device 12 and a switchable element 14 positioned in stacked adjacent relationship so that the semiconductor diode 12 and switchable element 14 are electrically connected in series. As will be described in greater detail below, the switchable element 14 is initially in the low-conductance or "OFF' state and may be switched to a high-conductance or "ON" state in response to the application of a forming current to the switchable element 14. Stated another way, the forming current may be used to "close" (i.e., place in the high-conductance or ON state) the switchable element 14. The series combination of the semiconductor diode 12 and switchable element 14 allows the state (e.g., high- or low- conductance) of device 10 to be conveniently "written" and "sensed" or "read," thereby allowing the device 10 to be used in electronic memory systems.
With reference now specifically to Figure 1, one embodiment 10 of the device according to the present invention may comprise a semiconductor diode device 12 in contact with an electrical contact 16. As will be discussed in greater detail below, the diode device 12 may comprise any of a wide range of structures and operating characteristics for semiconductor diodes that are now known in the art or that may be developed in the future. By way of example, in the embodiment shown and described in Figure 1 the semiconductor diode device 12 may comprise an n+-i-p device having a highly doped n-type (i.e., n+) layer 18, an intrinsic or lightly doped layer 20, and a p-type (i.e., p) layer 22. All three layers 18, 20, and 22 may be fabricated from microcrystalline silicon, although amorphous silicon may also be used. The contact 16 may comprise stainless steel, although other materials may also be used, as will be described in greater detail below.
The switchable element 14 may comprise a metal layer 24 and an intermediate layer 26 in positioned stacked adjacent relationship with the diode device 12. The arrangement is such that the switchable element 14 is electrically connected in series with the diode device 12. Stated another way, the diode device 12 and switchable element 14 comprise a monolithic, series-connected stack. The metal layer 24 of switchable element 14 may comprise silver, although other metals may be used. The intermediate layer 26 may comprise either an intrinsic semiconducting layer, a p-type semiconducting layer, or some combination of intrinsic and p-type semiconducting material. Alternatively, the intermediate layer 26 may comprise an insulator, such as a polymer material, as will be described in greater detail below. In one preferred embodiment, the intermediate layer 26 comprises p-type amorphous silicon passivated with hydrogen (i.e., p-a-Si:H), although other materials may also be used. As will be described in greater detail below, it is generally preferred, but not required, that a stop layer 28 be formed or positioned between the semiconductor diode device 12 and the switchable element 14. The stop layer 28 helps to prevent the diode device 12 from being damaged (e.g., shorted) during the application of the forming current to the switchable element 14. In one embodiment, the stop layer 28 may comprise a metallic or an extremely thin insulating layer. Alternatively, the stop layer 28 may comprise an appropriately doped and passivated amorphous silicon material. Still other materials may also be used for the stop layer 28, as will be described in greater detail below.
The diode portion 12, switchable element portion 14, and optional stop layer 28 of device 10 may be fabricated in accordance with any of a wide variety of processes that are well-known in the art or that may be developed in the future that are or would be suitable for fabricating the various layers comprising each portion 12, 14, and 28. Consequently, the present invention should not be regarded as limited to any particular fabrication processes or techniques to fabricate the device 10.
However, by way of example, in one preferred embodiment, the various layers of the device may be fabricated by chemical vapor deposition (CVD), for example, hot-wire CVD or plasma-enhanced CVD. As mentioned above, the switchable element 14 is initially in the low-conductance or OFF state, but may be placed in the high-conductance or ON state in response to the application to the switchable element 14 of a forming current. Consequently, the switchable element 14 functions like an "anti-fuse" in that it closes or becomes more conductive after the application of the forming current. This is in contrast to a conventional fuse which opens in response to the application to the fuse of an excessive current. When the switchable element 14 is in the low-conductance or OFF state, the impedance of the switchable element is relatively high (e.g., typically on the order of tens to hundreds of megaohms (MΩ) in one embodiment. When the switchable element is in the high- conductance or ON state, the impedance of the semiconductor switch 14 is several orders of magnitude lower than the impedance of the switchable element in the low-conductance state. For example, in one preferred embodiment, the impedance of the switchable element 14 is on the order of hundreds to thousands of ohms (Ω). As will be described in greater detail below, the absolute impedance of the switchable element 14 in either state is less important than is the magnitude of the impedance difference between the two states. That is, the difference in the impedances between the high- and low -conductance states should be sufficient to allow for the reliable determination of the state of the device 10.
When the switchable element 14 is first formed or fabricated it is in the low-conductance or OFF state. That is, the switchable element 14 has a relatively high impedance and passes very little current. The state of the switchable element 14 may be changed to the high-conductance or ON state by applying a forming current across the switchable element 14. For example, in one preferred embodiment, the switchable element 14 may be changed from the low-conductance or OFF state to the high-conductance or ON state by applying a forming current of sufficient magnitude and for sufficient time in the manner that will be described below. While the mechanisms responsible for causing the switchable element 14 to be switched from the low-conductance state to the high- conductance state are not yet well-understood, it is believed that the application of the forming current causes one or more conductive filaments (shown schematically in Figure 1 at 30) to form or "grow" from the metal layer 24 through the intermediate layer 26. The filament or filaments 30 provide a conductive pathway through the intermediate layer 26 of switchable element 14.
The filament growth theory is supported by observations that if the forming current and time of application are not carefully controlled, the diode element 12 will become shorted. It is believed that such diode shorting is the result of continued filament growth through the diode element 12. Accordingly, it is generally preferred, although not required, to provide the stop layer 28 between the switchable element 14 and the diode element 12. The stop layer 28 reduces the likelihood that the diode element 12 will become shorted during the forming process.
The device 10 may be written to as follows. Assuming that the device 10 has been fabricated in the manner briefly described above, the switchable element 14 will be in the low-conductance or OFF state. That is, the device 10 will act electrically in a manner akin to an open circuit, with little current flowing in response to the application of a potential voltage across the series combination of the diode 12 and switch 14. That is, the device 10 will have a current-voltage characteristic substantially as shown by curve 32 in Figure 2. Of course, the device 10 may be utilized in this state, if desired. For example, if the device 10 comprises an individual cell or element of an electronic memory array, the low-conductance state may be made to correspond to a selected binary state (e.g.,
0 or 1), as the case may be.
If it is desired to change the state of the device 10, a forming current can be applied across the series combination of the diode 12 and switch element 14. The polarity of the forming current is such that the diode element 12 of device 10 is biased in the forward direction. The application of the forming current causes the switchable element 14 of the device 10 to change to the high- conductance or ON state. In the high-conductance state, the device 10 will have a current-voltage characteristic substantially as shown by curve 34 in Figure 2. The curve 34 is similar to the electrical characteristics of the diode element 12, since the switchable element 14 is relatively conductive. Accordingly, the state of the device 10 can be detected or "read" by forward biasing the diode element 12. If the diode element 12 conducts (i.e., passes current) then the switchable element
14 is in the high-conductance or ON state. If the device 10 comprises an individual cell or element of an electronic memory array, the high-conductance state may correspond to the other binary state (e.g., a 1 or a 0).
A significant advantage of the device 10 according to the present invention is that it provides a series combination of an electronic switch and diode in a stacked arrangement. Accordingly, the device 10 of the present invention eliminates the need to provide a lateral conduction path between the two devices, as would be required if the two devices were fabricated in side-by-side (as opposed to the stacked) relationship. As a result, the device 10 would readily lend itself to the simplified manufacture of high density memory arrays, since the lithography steps required to form a separate conductive path between the diode and switch may be eliminated.
Having briefly described one embodiment 10 of a device according to the present invention, as well as some of its more significant features and advantages, various preferred embodiments of the device will now be described in detail. However, before proceeding with the detailed description it should be noted that while the device 10 is shown and described herein as it may be used in a semiconductor memory array to store binary (i.e., two state) data, it is not limited to use in such applications. Indeed, since the device of the present invention is functionally similar to a switch and diode connected in series, the present invention may be used in any of a wide range of applications wherein such functionality is desired. Accordingly, the device of the present invention should not be regarded as limited to the particular applications shown and described herein.
With the foregoing considerations in mind, a first embodiment 10 of a device according to the present invention is illustrated in Figure 1 and may comprise a semiconductor diode 12 and a switchable element 14 positioned in stacked adjacent relationship so that the semiconductor diode 12 and switchable element 14 form a monolithic, series-connected stack. The various elements (i.e., the semiconductor diode 12 and switchable element 14) comprising device 10 may be fabricated to have any of a wide range of configurations or shapes depending on the requirements of the particular application. Consequently, the present invention should not be regarded as limited to a device 10 comprising any particular configuration or shape. However, by way of example, in one preferred embodiment, the device 10 is fabricated so that it has a generally square shape or configuration, with each side of the square having a length of about 10 micrometers (μm).
The semiconductor diode element 12 of the device 10 may comprise any of a wide range of diode types having any of a wide range of structures suitable for producing a diode device 12 having any of a wide range of electrical characteristics that would be required or desired for any particular application. For example, diode structures and types that may be used with the present invention include, but are not limited to, diodes comprising n-i-p structures or p-i-n structures, diode structures involving conventional n-p or p-n structures can also be used, provided such diodes are fabricated from crystalline silicon or other crystal materials. Moreover, the diodes may be of any of a wide range of types, such as, for example, "conventional" rectifying diodes, Schottky diodes, tunnel diodes, or even light emitting diodes. Consequently, the present invention should not be regarded as limited to any particular diode structure having any particular electrical characteristics. However, by way of example, in the embodiment shown and described in Figure 1 , the semiconductor diode device 12 comprises an n+-i-p device having a highly doped n-type layer 18, an intrinsic (or a very lightly doped) layer 20, and a p-type layer 22. All three layers 18, 20, and 22 are fabricated from microcrystalline silicon, although amorphous silicon may also be used.
The thicknesses of the various layers 18, 20, and 22 comprising diode device 12 are not particularly critical and may comprise any of a wide range of thicknesses depending on the electrical characteristics and other performance parameters that may be required or desired in any particular application. However, by way of example, in the embodiment shown and described herein, the n+ layer 18 may have a thickness of about 60 nano-meters (nm), whereas the thicknesses of the intrinsic layer 20 and the p-layer 22 may be about 260 nm and 60 nm, respectively.
The layers 18, 20, and 22 comprising diode device 12 may be formed by any of a wide range of processes that are now known in the art or that may be developed in the future that are or would be suitable for forming the layers 18, 20, and 22 to produce the diode device 12. Accordingly, the present invention should not be regarded as limited to any particular process for forming the various layers of the diode device 12. However, by way of example, in one preferred embodiment, the various layers 18, 20, and 22 of diode device 12 are formed by chemical vapor deposition. The diode device 12 may be provided with a suitable electrical contact, such as contact 16, to allow one of the electrodes (i.e., either the anode or the cathode, as the case may be) of the diode device 12 to be electrically connected to an external circuit and/or device. In the embodiment shown and described herein, the contact 16 contacts the cathode (i.e., n+ layer 18) of diode device 12. The contact 16 may comprise any of a wide range of materials (e.g. , metals or doped semiconductors) that would be suitable for the intended application. Also, any of a wide range of interface layers (e.g., doped semiconducting layers) may be positioned between the diode 12 and the contact 16 if required or desired for the particular application. Consequently, the present invention should not be regarded as limited to contacts comprising any particular material or to the presence or absence of any interface layers or material between the diode 12 and the contact 16. However, by way of example, in one preferred embodiment, the contact 16 comprises stainless steel. Alternatively, other materials, such as aluminum, may also be used, as would be obvious to persons having ordinary skill in the art after having become familiar with the teachings of the present invention.
As mentioned above, the particular process used to form the diode device 12, as well as the exact compositions and structural characteristics of each of the various layers (e.g., 18, 20, and 22) of the diode device 12 are not particularly critical and may comprise any of a wide range of forming processes, compositions and structural characteristics that would be suitable for producing a diode device having any of a wide range of desired electrical characteristics. For example, certain electrical characteristics of diode devices that are dependent on such fabrication parameters (e.g., the forming processes, layer compositions and structural characteristics) include, but are not limited to forward turn-on voltage, forward series resistance, forward breakdown current, reverse breakdown voltage, reverse shunt resistance, and lateral resistance between elements. However, since the various fabrication parameters of the layers comprising the diode devices may be varied depending on the desired electrical characteristics of the diode device 12, and since persons having ordinary skill in the art could readily select such fabrication parameters after selecting the required or desired electrical characteristics of the diode device 12, the various fabrication parameters associated with the particular diode device 12 utilized in one preferred embodiment of the present invention will not be described in further detail herein. Thecontact 16 maycomprise the substrate itself which supports the device 10. Alternatively, the contact 16 may be supported by a separate, preferably insulating, substrate 36, such as glass, ceramic, or plastic. See Figure 1. Also, any of a wide range of interface layers (not shown) may be positioned between the contact 16 and the substrate 36, as may be required or desired in the particular application. For example, in certain cases it may be desirable to provide an interface layer or material between the contact 16 and the substrate 36 to provide for improve adhesion of the contact 16 to the substrate 36. The use of an insulating substrate 36 is advantageous if the device 10 comprises an individual cell or element in an array of cells, such as may be provided for in an electronic memory circuit. In such an application, an insulating substrate 36 provides a means for electrically insulating a contact 16 associated with a single "row" or "column" of cells (i.e., devices 10) from the contacts associated with adjacent rows or columns of cells.
The switchable element 14 may comprise any of a wide range of structures that are well- known in the art or that may be developed in the future capable of being switched between a non- conductive or "OFF' state and a conductive or "ON" state. For example, the switchable element 14 may comprise any of the structures and devices disclosed in U.S. Patent No. 4,684,972 issued on August 4, 1987, and entitled "Non- Volatile Amorphous Semiconductor Memory Device Utilizing a
Forming Voltage" and U.S. Patent No. 5,360,981, issued November 1, 1994, and entitled "Amorphous Silicon Memory", both of which are hereby specifically incorporated herein by reference for all that they disclose.
In the embodiment shown in Figure 1 , the switchable element 14 may comprise a metal layer 24 and an intermediate layer 26 positioned in stacked adjacent relationship. The switchable element
14 may be positioned in stacked adjacent relationship with the diode device 12 so that the diode device 12 and switchable element 14 are electrically connected in series. As was mentioned above, the mechanism or mechanisms by which the switchable element 14 may be switched between at least two states (e.g., the ON state and the OFF state) are not well understood at this time. However, it is believed that the application of the forming current results in the formation or growth through the intermediate layer 26 of one or more filaments (represented schematically in Figure 1 at 30) from the metal layer 24. This theory is supported by experimental evidence which indicates that certain metals for the metal contact 24 work better than others in causing the switchable element 14 to operate in either the conductive state or the non-conductive state. For example, Ag and V appear to diffuse easily through a semiconducting intermediate layer 26 comprising hydrogenated (i.e., passivated) amorphous silicon (a-Si:H), whereas Cr appears to be less likely to diffuse through such a semiconducting intermediate layer 26. Consequently, it is generally preferable to fabricate the metal layer 24 from either Ag or V, especially where the intermediate layer 26 comprises a-Si:H.
The thickness of the metal layer 24 is not particularly critical, but should be sufficient to provide the required mechanical strength and durability that may be required or desired for the particular application. Consequently, the present invention should not be regarded as limited to a metal layer 24 having any particular thickness. However, by way of example, in one preferred embodiment, the metal layer 24 may have a thickness of about 60 nm. The metal layer 24 may be deposited by any of a wide variety of processes that are well-known in the art or that may be developed in the future that would be suitable for forming such metallic layers. By way of example, in one preferred embodiment, the metal layer 24 is formed by evaporation, although other processes (e.g., sputter deposition) may also be used. The intermediate layer 26 may be deposited directly on the diode device 12 and may comprise either a semiconducting material or an insulating material. It will normally be best if the filament 30 grows through the layer 26 more readily than through the diode device 12. Alternatively, and as will be described in greater detail below a supplemental layer, such as a stop layer 28, may be formed between the intermediate layer 26 and the diode device 12. The intermediate layer 26 may comprise any of a wide range of semiconducting materials, such as amorphous silicon passivated with hydrogen (a-Si:H) and may be either doped or undoped. In the embodiment shown and described herein, the intermediate layer 26 comprises p-type passivated amorphous silicon. Alternatively, the intermediate layer 26 may comprise intrinsic a-Si:H or even a p-i, p-i-n, or n-i-p structure of a-Si:H or of microcrystalline silicon. In addition, other materials, such as those described in U.S. Patent Nos. 4,684,972 and 5,360,981, may also be used. In still another application, the intermediate layer 26 may comprise an insulating material (e.g., any of a wide range of polymers or other organic materials). Insulating materials that may be used include, but are not limited to alloys of hydrogen-passivated amorphous silicon with carbon or with germanium. Alternatively, microcrystalline silicon may also be used. The intermediate layer may also be formed from conventional photoresist films. The intermediate layer 26 may be deposited by any of a wide variety of processes that are well-known in the art or that may be developed in the future that would be suitable for forming an intermediate layer 26 comprising the desired material. By way of example, in one preferred embodiment, the semiconducting intermediate layer 26 is formed by chemical vapor deposition, although other processes may also be used.
The thickness of the intermediate layer 26 may be important depending on whether a supplemental layer, such as stop layer 28, is positioned between the switchable element 14 and the semiconductor diode device 12. Generally speaking, the thickness of intermediate layer 26 should be sufficient to prevent unintentional diffusion of the metal layer 24 through the intermediate layer 26. Such unintentional diffusion may cause the switchable element 14 to change from the low- conductance to the high-conductance state. However, the thickness of the intermediate layer 26 should not be so great that it is difficult to intentionally change the state of the switchable element 14 in response to the forming current. In accordance with the foregoing considerations, we have found that a semiconducting intermediate layer 26 having a thickness in the range of about 10 nm to about 500 nm (100 nm preferred) provides good results.
As was described above, it is generally preferred, but not required, to position a stop layer 28 between the intermediate layer 26 of switchable element 14 and the diode 12. The stop layer 28 reduces the likelihood that the diode device 12 will be shorted during the application of the forming current to the switchable element 14. That is, in accordance with the theory that the switchable element 14 is made conductive due to the growth of one or more conductive filaments 30 through the intermediate layer 26, the presence of the stop layer 28 retards the growth of the filament 30 by an amount sufficient to allow the forming current to be removed before the filament contacts or grows through the diode device 12. Alternatively, and as will be described below, careful control of the forming current may allow the device 10 to be operated satisfactorily in the absence of a supplemental or stop layer 28. Certain variations in the materials and characteristics comprising the switchable element 14 may also allow the device 10 to be satisfactorily operated without a supplemental or stop layer 28. In one preferred embodiment the stop layer 28 comprises a highly doped n-type semiconducting material, such as hydrogen passivated amorphous silicon. Alternatively, other materials, such as metals or thin insulating layers (e.g., silicon oxide or silicon nitride), may also be used in the manner that will be described in greater detail below. The stop layer 28 may be deposited by any of a wide variety of processes that are well-known in the art or that may be developed in the future that would be suitable for forming such semiconducting layers. By way of example, in one preferred embodiment, the stop layer 28 is formed by chemical vapor deposition, although other processes may also be used. If the stop layer 28 comprises an insulating or undoped semiconducting material then the thickness of the stop layer should be carefully controlled. For example, thin stop layers 28 may reduce the ability to reliably stop filament growth (e.g, by removing the forming current) before the filament 30 shorts the diode device 12. On the other hand, excessive thickness of an insulating stop layer 28 may impede the flow of current between the switchable element 14andthediode 12, thereby making it difficult to read the state of the switch device 14. In this regard it is believed that the growth of the filament 30 should be terminated at a position within an insulating stop layer 28 that will allow electrons to "tunnel" through the remaining thickness of the stop layer 28. Such a phenomenon is known in the art as "electron tunneling." In accordance with the foregoing considerations, then, we have determined that if the stop layer 28 comprises an insulator, it should have a thickness between about 0.5 nm and about 2 nm (1 nm preferred). Alternatively, of course, other thicknesses may be used provided they allow the switchable element 14 to be reliably written without shorting the diode 12 while also allowing sufficient current flow through the junction from the switchable element 14 and to determine whether the switch device 12 is in the ON state or the OFF state.
As mentioned above, other materials may be used for the stop layer 28. For example, the stop layer 28 may also comprise a relatively "stable" metal (i.e., a metal having low diffusivity through the adjacent layers 22 and 26) such as Cr. A stop layer 28 comprising a metallic material functions in a manner similar to the semiconducting stop layer in that it allows the filament growth to be more easily terminated before the filament 30 contacts the diode device 12. Such a metallic stop layer may be fabricated in accordance with any of a wide range of processes that are now known in the art or that may be developed in the future that are or would be suitable for depositing metallic layers. Consequently, the present invention should not be regarded as limited to any particular fabrication process. However, by way of example, in one preferred embodiment, a metallic stop layer 28 may be formed by evaporation. Alternatively, other processes, such as sputter deposition, may also be used.
Because such a metallic stop layer 28 is highly electrically conductive, it removes the concern of providing a low resistance path (such as by electron tunneling in the case of an insulating stop layer 28) between the filament 30 and the diode device 12. Consequently, a stop layer 28 fabricated from metal may be made thicker, if desired (compared with an insulating stop layer), in order to provide an enhanced margin against diode shorting by filament impingement. However, a metallic stop layer 28 would need to be patterned (e.g., by means of lithography) if the device 10 is to comprise an individual cell or element of an array of devices 10. A patterned metallic stop layer 28 is required in such an application in order to prevent the metallic stop layer 28 from shorting out other memory cells in the array. In contrast, a stop layer 28 comprising a semiconducting material, such as thin n+-a-Si:H or an insulating stop layer, such as SiNx , will not usually need to be patterned in such an application. That is, the higher electrical resistance of a semiconducting stop layer is usually sufficient to prevent shorting and/or unacceptable cross-talk between adjacent memory cells.
Accordingly, it is generally advantageous to fabricate the stop layer 28 from a semiconducting material (e.g., n+-a-Si:H) or an insulating material if the device 10 is to be used in an electronic memory array.
When the device 10 is first formed or fabricated, the switchable element 14 is in the low- conductance or OFF state and will have a current-voltage characteristic substantially as shown by curve 32 in Figure 2. That is, the switchable element 14 has a relatively high impedance and passes very little current, much like an open switch. If it is desired to change the state of the device 10, a forming current can be applied across the series combination of the diode 12 and switchable element 14. The polarity of the forming current is such that the diode element 12 of device 10 is biased in the forward direction. The application of the forming current causes the switchable element 14 to change to the high-conductance or ON state. In the ON state, the device 10 will have a current- voltage characteristic substantially as shown by curve 34 in Figure 2. The curve 34 corresponding to the high-conductance or ON state of switchable element 14 is similar to the electrical characteristics of the diode element 12 by itself. The magnitude and duration of the forming current required to change the state of the switchable element 14 may vary depending on the particular materials used to form the device 10. Consequently, the present invention should not be regarded as limited to forming currents of any particular magnitudes, voltages, and durations. However, by way of example, in one preferred embodiment the forming current may have a magnitude in the range of about 0.1 micro-amperes (μ A) to about 10 μ A (1 μA preferred). The forming current may be applied for durations in the range of about 1 nano-second (ns) to about 1 second, with faster times being preferable. Alternatively, the forming processes may correspond to those disclosed in U.S. Patent Nos.4,684,972 and 5,360,981 if the switchable element 14 is fabricated in accordance with the teachings contained therein.
External electronic circuitry (not shown) connected to the device 10 can be made to recognize or differentiate between the changed current-voltage characteristics (i.e., I-V curves 32 and 34) of the device 10, thus determine whether the switchable element 14 is in the ON or OFF state. For example, if the device 10 comprises one element in an array of such elements, such as may be the case if the device 10 comprises a portion of an electronic memory array, any element (e.g., device 10) in the array may be "read" by forward biasing the diode device 12 associated with desired element while reverse biasing the diodes associated with the other elements in the array. If the element conducts (i .e., passes current), then the element is in the high-conductance or ON state. This may be made to correspond to one of the states (e.g., "0" or "1") in a binary system. A second embodiment 110 of a device according to the present invention is illustrated in
Figure 3. The second embodiment 110 is similar to the first embodiment 10 described above except that the positions of the diode device 112 and the switchable element 114 are reversed. That is, the switchable element 114 is positioned adjacent a supporting substrate 136 with the diode device 112 in stacked adjacent relationship with the switchable element 112 so that the two devices form a monolithic, series-connected stack.
As was the case for the first embodiment 10, the diode device 112 of the second embodiment 110 may comprise any of a wide range of structures and materials to provide any required or desired diode characteristic. For example, in the embodiment shown in Figure 3, the diode device 112 comprises a p-i-n+ device having a p-type layer 122, an intrinsic layer 120, and a highly doped n-type layer 118. All three layers 18, 20, and 22 are fabricated from microcrystalline silicon, although amorphous silicon may also be used. A contact 116 may be formed adjacent to the n+ layer 118.
The switchable element 114 may comprise any of the materials recited above for the switchable element 14 for the first embodiment 10 and may be fabricated in accordance with the methods and considerations discussed herein. For example, the switchable element 114 may comprise a metal layer 124 and an intermediate layer 126 positioned in stacked adjacent relationship.
The metal layer 124 may be fabricated on the support substrate 136.
The device 110 may be provided with a stop layer 128 or the stop layer 128 may be omitted if the formation of the filament 130 can be reliably controlled in the manner already described to avoid shorting the diode element 112. If a stop layer 128 is used, it may comprise either a semiconducting material (e.g., n+-a-Si:H), an insulating material, or a metallic material, whichever may be more advantageous for the intended application.
It is contemplated that the inventive concepts herein described may be variously otherwise embodied and it is intended that the appended claims be construed to include alternative embodiments of the invention except insofar as limited by the prior art.

Claims

Claims
1. A device comprising a semiconductor diode and a switchable element positioned in stacked adjacent relationship so that said semiconductor diode and said switchable element are electrically connected in series with one another, said switchable element being switchable from a low- conductance state to a high-conductance state in response to the application of a forming current.
2. The device of claim 1 , wherein said switchable element comprises an intermediate layer and a metallic layer, said intermediate layer being in stacked adjacent contact with said metallic layer.
3. The device of claim 2, wherein said intermediate layer comprises p-type amorphous silicon.
4. The device of claim 2, wherein said intermediate layer comprises intrinsic-type amorphous silicon.
5. The device of claim 2, wherein said metallic layer is Ag, Cr, or V.
6. The device of claim 1 , further comprising a stop layer positioned between said semiconductor diode and said switchable element so that said semiconductor diode, said stop layer, and said switchable element are in stacked adjacent contact with one another.
7. The device of claim 6, wherein said stop layer comprises n-type amorphous silicon.
8. The device of claim 6, wherein said stop layer comprises a metal.
9. The device of claim 8, wherein said metal stop layer is Cr.
10. The device of claim 1, further comprising a contact in adjacent contact with said semiconductor diode.
11. The device of claim 10, wherein said contact comprises a metal.
12. The device of claim 11, wherein said metal contact comprises stainless steel.
13. The device of claim 1 , wherein said semiconductor diode comprises an amorphous silicon structure.
14. The device of claim 1, wherein said semiconductor diode comprises a microcrystalline silicon structure.
15. A device comprising: a semiconductor diode device; a switchable element; and a stop layer positioned between said semiconductor diode device and said switchable element, the arrangement being such that said semiconductor diode device, said stop layer, and said switchable element are positioned in stacked adjacent relationship, said switchable element being switchable from a low-conductance state to a high-conductance state in response to the application of a forming current.
16. The device of claim 15, wherein said switchable element comprises an intermediate layer and a metallic layer, said intermediate layer being in stacked adjacent contact with said metallic layer.
17. The device of claim 16, wherein said stop layer comprises n-type amorphous silicon.
18. The device of claim 16, wherein said stop layer comprises a metal.
19. The device of claim 18, wherein said metal stop layer is Cr.
20. A method of forming a device, comprising forming a diode device from semiconducting material; forming an intermediate layer in stacked adjacent relationship with said diode device; and depositing a metallic layer on said intermediate layer, said intermediate layer and said metallic layer forming a switchable element, said switchable element being switchable from a low-conductance state to a high-conductance state in response to the application of a forming voltage to said switchable element, said switchable element being in electrical series with said diode device.
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US9412790B1 (en) 2012-12-04 2016-08-09 Crossbar, Inc. Scalable RRAM device architecture for a non-volatile memory device and method
US9520557B2 (en) 2008-10-20 2016-12-13 The Regents Of The University Of Michigan Silicon based nanoscale crossbar memory
US9543359B2 (en) 2011-05-31 2017-01-10 Crossbar, Inc. Switching device having a non-linear element
US9564587B1 (en) 2011-06-30 2017-02-07 Crossbar, Inc. Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
US9570678B1 (en) 2010-06-08 2017-02-14 Crossbar, Inc. Resistive RAM with preferental filament formation region and methods
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US9583701B1 (en) 2012-08-14 2017-02-28 Crossbar, Inc. Methods for fabricating resistive memory device switching material using ion implantation
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US9620206B2 (en) 2011-05-31 2017-04-11 Crossbar, Inc. Memory array architecture with two-terminal memory cells
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US9685608B2 (en) 2012-04-13 2017-06-20 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US9729155B2 (en) 2011-07-29 2017-08-08 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
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US9793474B2 (en) 2012-04-20 2017-10-17 Crossbar, Inc. Low temperature P+ polycrystalline silicon material for non-volatile memory device
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US11068620B2 (en) 2012-11-09 2021-07-20 Crossbar, Inc. Secure circuit integrated with memory layer

Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
JP5702725B2 (en) * 2008-10-08 2015-04-15 ザ・リージェンツ・オブ・ザ・ユニバーシティ・オブ・ミシガンＴｈｅ Ｒｅｇｅｎｔｓ Ｏｆ Ｔｈｅ Ｕｎｉｖｅｒｓｉｔｙ Ｏｆ Ｍｉｃｈｉｇａｎ Silicon-based nanoscale resistor with adjustable resistance
US9166163B2 (en) 2011-06-30 2015-10-20 Crossbar, Inc. Sub-oxide interface layer for two-terminal memory
US10056907B1 (en) 2011-07-29 2018-08-21 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
JP5537524B2 (en) * 2011-09-22 2014-07-02 株式会社東芝 Resistance change memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663580A (en) * 1996-03-15 1997-09-02 Abb Research Ltd. Optically triggered semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663580A (en) * 1996-03-15 1997-09-02 Abb Research Ltd. Optically triggered semiconductor device

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