Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words

Definitions

• the present invention relates to error correction code (ECC). More particularly, this invention is related to device and applications of the ECC circuits for error corrections of data with variable data width.
• ECC error correction code
• ECC error correction circuit
• Prior art ECC mechanism provides excellent protections for data integrity, but it also introduces many technical difficulties.
• the ECC calculator takes a large number of data into large parity trees while each parity tree executes different parity calculations for different data subsets.
• the complex wiring needed for such parity calculations make the ECC circuits slow and complex. Performance degradation caused by ECC calculation often limited its applications.
• Each prior art ECC mechanism is defined for a particular data size. In oirder to change the size of the data package, it is required to re-design the ECC mechanism. Testing is another issue.
• the speed of a prior art ECC calculator is strongly dependent on the input data pattern; they always slow down significantly when the size of the data package is increased. If there is a manufacture defect in one of the complex wiring used by a prior art ECC circuit, it is very difficult to detect the problem because of the large number (2 72 x 2 72 for the example in FIG. 1) of test vectors required to have full fault coverage.
• the primary objective of this invention is to provide an ECC calculator with simplified structure.
• This simplified ECC calculator can support data packages of nearly any size using the same circuit at the same speed.
• Another objective is to improve the speed of ECC circuits.
• Another primary objective of the present invention is to provide novel applications for practical products using the novel ECC circuits of the present invention.
• FIG. 1 is a block diagram for prior art ECC circuits
• FIG. 2(a) is a schematic diagram showing the rotational relationship between ECC blocks of the present invention
• FIG. 2(b) is the schematic diagram for the ECC block in FIG. 2(a);
• FIG. 2(c) shows the structure of an ECC decoder of the present invention
• FIG. 2(d) is the schematic diagram for the ECC decoder block in FIG. 2(c);
• FIG. 3(a) shows a variable width ECC calculator of the present invention
• Fig. 3(b) shows a variable width ECC calculator that allows process of continuous incoming data streams of different data-widths
• FIG. 4 shows the structure of a prior art floating gate device
• FIG. 5 is a float chart for the ECC self repair procedures of the present invention
• Figs- 6(a-d) illustrates different methods to represent multiple bit digital data with one analog signal
• FIG. 6(e) is the block diagram for a circuit to implement the analog-to- digital data translation according to the table in FIG. 6(b);
• Figs. 7(a-c) show the structures for prior art content addressable memory and its associated memory cells.
• Figs. 8(a-d) show examples for ECC protection on CAM devices.
• D[3:2][4:l] means a set of 8 symbols D34, D33, D32, D31, D24, D23, D22, and D21.
• the "mod" function is implemented by a rotational relationship in the input connections of actual circuits.
• the ECC calculator in this example takes 64 input data (D[7:0] [7:0]). It comprises 8 identical parity circuit blocks (P7-P0). Schematic diagram for the parity circuit block is shown in FIG. 2(b). Each parity circuit block (P7-P0) comprises 19 exclusive-or gates, one exclusive-nor, and one inverter.
• the parity circuit block P[k] takes data D[k][7:0] and stored ECC bit Ck as inputs, where k is an integer between 0 to 7. It sends four outputs (Nil, N22, N33, N41) to the parity circuit on top of it, and receives corresponding outputs
• N33 Parity ⁇ N23B, Dk2, Dk5, Dk6 ⁇ (lc),
• N41 Parity ⁇ N33B, N24T, Dkl, Dk4, Dk5 ⁇ (Id),
• N24 Parity ⁇ Dk4, Dk5, Dk6, Dk7 ⁇ (le),
• Fk Parity ⁇ N42T, N41B ⁇ (lh), where "Parity ⁇ ” means the parity value of all the inputs included in “ ⁇ ” signs.
• the inputs (NUB, N22B, N33B, N41B, N24T, N32T, N42T) provided by nearby parity circuits can be determined by the fact that all of those parity circuits are identical. For example, from Eq. (la) a functional relationship can be established that:
• NUB Parity ⁇ C[(k+l) mod 8], D[(k+1) mod 8]0 ⁇ (2) where C[(k+1) mod 8] is the stored ECC bit, and D[(k+1) mod 8]0 is the first data connected to the parity circuit below it. All other inputs (N22B, N33B, N41B,N24T, N32T, N42T) can be determined in similar ways. Based on the connections in FIG.
• Fk Parityf Ck, D[(k-2) mod 8][7:0], D[(k-1) mod 8][5:0], D[k][7:4,0],D[(k+l) mod 8][5,4,1], D[(k+2) mod 8][6,5,2 ⁇ , D[(k+3) mod 8][7,4,3] ⁇ (3)
• k (0,1,2,3,4,5,6,7).
• the signals (Fk) would be all zeros. If there is one error in the input data D[7:0][7:0], the error bit is identified by checking the correction factors (FO-Fk) using the ECC decoder shown in FIG. 2(c).
• This ECC decoder comprises 8 ECC decoding blocks (CB0-CB7). Those 8 ECC decoding blocks have identical logic functions, as shown in the schematic diagram in FIG. 2(d). The only difference is in the connection to the Fk signals. There is, again, an rotational relationship in the Fk connections. For example, the FI of CB1 is equal to F0 of CB0, while the F2 of CB2 is also F0, .... etc.
• the same circuit in FIG. 2(a) can be used to calculate the ECC bits for a set of raw data; all the Ck inputs is assigned a value of zero, and the resulting Fk would be the ECC bits as
• ECC(k) Parity ⁇ D[(k-2) mod 8][7:0], D[(k-1) mod 8][5:0], D[k] [7:4,0],D[(k+l) mod 8] [5,4,1],
• the ECC mechanism shown in FIGs. 2(a-d) is novel by the rotation relationship in the parity calculation; parity calculation of C[k+1] is the result of simple rotation of C[k]. This rotation relationship is also applied to the ECC correction circuits.
• Such ECC circuits are called “rotational ECC calculator (REC)" in the present invention.
• the REC circuits are different from other prior art ECC circuits by the following features:
• FIG. 3 shows an REC circuit that uses identical circuit blocks as those in FIG. 2(a) to support input data of variable length.
• the ECC calculator in this example takes N bytes of input data (D[(N- 1):0][7:0]), where N is an arbitrary integer. It comprises N identical parity circuit blocks (P j ⁇ -PO) connected in rotation relationship as shown in FIG. 3(a). The logic functions of these parity circuit blocks (P N . ⁇ -P0) are identical to that in FIG.
• Fk Parity! Ck, D[(k-2) mod N][7:0], D[(k-1) mod N][5:0], D[k][7:4,0],D[(k+l) mod N] [5,4,1], D[(k+2) mod N] [6,5,2], D[(k+3) mod N] [7,4,3] ⁇ (6)
• ECC(k) Parity ⁇ D[(k-2) mod N][7:0], D[(k-1) mod N][5:0],
• a REC can be expanded to support input data set of any number by implementing the same repeating REC building blocks as that shown in Fig. 3(a).
• the resulting circuits will have identical speed and identical circuit connections, no matter what is the width of the input data set. There is no need to re-design ECC calculator to support different data width.
• FIG. 3(b) shows an alternate preferred embodiment for application to situations often encountered in data communication systems where a long stream of incoming data that starts and ends with pre-defined data, e.g., header records, are received continuously.
• a series rotational error correction circuits is implemented to continuously receive and process the data stream to assure correction of data transmission.
• An artificial wrap around logic circuit (AWALC) is implemented wherein the error code calculations are performed by feeding simplified bit patterns such as all ones or all zeros to the beginning and the ending REC calculator blocks.
• the error code calculations can be carried out similar to the closed loop REC with the fixed bit-pattern input to those blocks.
• the open loop wrap-around ECC calculator can be conveniently controlled or reconfigure to process data streams of variable lengths by first sending the length of a data record then applying a corresponding number of ECC blocks to carry out the error code calculations.
• Eq. (1-7) can be modified to different forms while keeping the rotation relationship.
• the parity block can access different numbers of inputs other than 8, and output different number of ECC bits and intermediate signals.
• the novel element for the correction mechanism of the present invention is to enforce a rotational relationship in parity calculation of ECC mechanism. Based on the rotational relationship, repeating circuit design can be used to simplify design effort. Higher performance is also achieved by minimizing wiring complexity.
• this invention discloses a method for changing a configuring of an error correction code (ECC) logic circuit for performing an error-check of a changed data-width.
• ECC error correction code
• the method includes the steps of: A) sequentially interconnecting a set of Nl identical error-check blocks where Nl is a first positive integer. And, the method further includes a step B) of reconfiguring the ECC logic circuit by changing the ECC logic circuit to a set of
• N2 sequentially interconnected circuits comprising N2 of the identical error- check blocks where N2 is a second positive number.
• the step of sequentially interconnecting a set of Nl identical error-check blocks is a step of interconnecting the Nl error-check blocks only between sequentially neighboring blocks for transmitting signals only between the neighboring error- check blocks.
• the step of reconfiguring the ECC logic circuit by changing the ECC logic circuit to a set of N2 sequentially interconnected circuits is a step of interconnecting the N2 error-check blocks only between sequentially neighboring blocks for transmitting signals only between the neighboring error-check blocks.
• FIG.4 shows the symbolic structure of a floating gate transistor.
• This transistor comprises source (S), drain (D), and gate (G), just like common transistors.
• the difference is that it has a floating gate (FG) between gate and channel region.
• the floating gate is isolated under most operation conditions, while charges can be injected into or removed from it by hot carrier mechanism or tunneling mechanism during a program or an erase operation.
• the conductivity of the floating gate device is a function of the amount of charge trapped in the floating gate (FG). It is therefore possible to store data into the floating gate device by changing the amount of trapped charges i the floating gate.
• Many commercial products, such as EPROM, EEPROM, and FLASH, have been built on the floating gate devices.
• the most difficult reliability problems for floating gate devices are the charge loss (QL) problem and program-erase (PE) cycling induced failures.
• QL charge loss
• PE program-erase
• the QL problem is often caused by manufacture defects on the surrounding insulators around the floating gate. A manufacture defect can cause small leakage on the floating gate so that the device is not able to maintain its data due to loss in trapped charges.
• the QL problem usually does not cause permanent damages to the floating gate device; if the data is re-written into the failed device, it will maintain functional for a period of time until its trapped charges gradually leak out.
• the PE cycle induced failures are often permanent. When a user executes a program to erase a floating gate device many times, the high energy charges going through the floating gate causes damages to its surrounding materials, so that the device may fail after certain PE cycles.
• This self-repair procedure can be started by an external system such as a computer software. It also can be started internally while external users do not know it happened. For example, execution of the procedure can be invoked during a power up initialization cycle, or a timer signal is used to trigger the procedure. Assume that the ECC bits have been written into the memory device together with the raw data. After the self-repair procedure is started, a data set is read from the memory device with associated ECC bits. ECC circuits are used to check if there is any error in the raw data. If there is no error, the error-check operation progress to next data set until the procedures are completed. If an error is found, and ECC can not correct it, the device will send out a warning signal to the system.
• ECC Error Correction Code
• a corrected data bit is written back into the storage device. If the problem is caused by a soft error such as charge loss problem in floating gate device, or a problem caused by alpha particles, the problem may be resolved by writing the correct data back into the memory device. The faulty data should be read and checked again. If the problem has been fixed, the error code checking operation can now move to operate on the next data set. If the problem can't be fixed by write back, a programmable redundancy circuit maybe implemented to resolve the problems caused by the faulty memory cells. If the redundancy circuit is able to fix the problem, the error-check operation progresses to next data set. If not, the product is still functional because a user will obtain the correct data after ECC corrections.
• the device maybe getting close to fatal failures.
• a counter may be implemented to count the number of corrected failures. If the number is larger than a pre-defined value, warning signals are generated to notify the user of the system.
• this invention further discloses a method for operating a memory device comprising a plurality of memory cells.
• the method includes a step A) of performing an error-check on said memory cells.
• the step of repairing a faulty memory cell further includes a step of performing the step of repairing the faulty memory cell automatically by writing a correct bit into the faulty memory cell.
• ECC protections or the self-repair mechanism will require additional resources, but the resulting product maybe more cost efficient due to better yield and or better reliability. It is also possible to use the improvement in reliability to carry more data in the same device.
• four analog levels are defined for representing the amount of floating gate trapped charge, so that one memory cell now may be used to store two bits of binary data, instead of one bit.
• FIG. 2(a) shows one example of this multiple level digital data (MLDD) representation. The two bit binary data (1,1) is stored when the trapped charges
• (Q) in a floating gate device is more than a pre-defined value (Q3) as Q > Q3; binary data (1,0) is stored when Q3 > Q > Q2; binary data (0,1) is stored when Q2 > Q > Ql; and binary data (0,0) is stored when Q ⁇ Ql; where Q3, Q2, and Ql are a pre-defined values related to the trigger level of sensing circuits and Q3 > Q2 > Ql.
• Q3, Q2, and Ql are a pre-defined values related to the trigger level of sensing circuits and Q3 > Q2 > Ql.
• the MLDD representation in FIG.2(a) has one problem. If the original storage data is (1,0) while Q3 > Q > Q2, and the device lose some charges so that Q2 > Q > Ql, the data become (0,1). There can be two binary bits changed due to a small amount of charge loss.
• the ECC protection needs to be able to correct two bits, otherwise, two separated ECC circuits are required to protect those two bits separately. Both methods require more resources. This resource requirement can be reduced if the two bit MLDD representation is redefined as that shown in FIG. 2(b). For each higher step of Q, the binary data never changes more than one bit. Therefore, the resource requirements will be simplified to fix small charge loss. Similar methods can be applied to the 8-level-3-bit example in FIG. 6(c), and the 16-level-4-bit example in FIG. 6(d).
• FIG. 6(e) is the block diagram for a circuit to implement the analog-to- digital data translation according to the table in FIG. 6(b).
• An analog signal (Q) is compared with three pre-defined values (Q3, Q2, Ql) by comparators (651).
• the output of the first comparator (CP1) is 1 when Q > Ql while it is 0 when Q ⁇ Ql
• the output of the second comparator (CP2) is 1 when Q > Q2 while it is 0 when Q ⁇ Q2
• the output of the third comparator (CP3) is 1 when Q > Q3 while it is 0 when Q ⁇ Q3.
• These outputs (CP3, CP2, CP1) of comparators are sent to an encoder (652) circuit.
• This encoder (652) provides two digital output bits (Dl, DO).
• this invention further discloses a memory device that includes a plurality of memory cells each having a floating gate for storing a plurality of electric charges therein.
• the memory device further includes an error-check logic circuit that includes a set of identical error- check blocks sequentially interconnected for checking errors of data storage in the memory cells.
• the memory device further includes a multiple-level voltage means for applying at least two electrical charge levels on the floating gates for representing at least two binary bits stored in the memory cells.
• the memory device further includes a multiple-level electrical-charge sensing means for sensing at least two electric-charge levels stored in the floating gates for detecting at least two binary bits stored in the memory cells.
• the multiple- level electrical-charge sensing means further comprising a bit-pattern means for generating a bit-pattern based on the electric-charge levels sensed by the multiple-level electrical-charge sensing means.
• the bit-pattern means is further provided for generating a sequence of bit-patterns based on the electric-charge levels wherein each of the bit patterns based on a first electrical-charge level differing by only a single bit from a second bit-pattern representing a second electrical-charge level sequentially adjacent to the first electrical-charge level.
• Q can be any analog parameter such as voltage or current, it does not need to be the trapped charge.
• the device also does not need to be a floating gate device.
• FIG. 7(a) shows the basic structures of a prior art CAM device. There are two kinds of data stored in a CAM device - common digital data stored in typical random access memory (RAM) array (703), and the addressing data (called “TAG” in IC industry) stored in CAM array (701).
• FIG. 7(b) is the schematic for a typical memory cell in the RAM array (703). This memory cell use four transistors (MpO, Mpl, MnO, Mnl) to form a bi-stable latch to store data, and two transistors (Mw, Mw#) for selecting the memory cell through word line (WL).
• FIG. 7(c) is the schematic for a typical memory cell in the CAM array (701).
• This memory cell is similar to the RAM cell except that it has four more transistors (McO, Mel, Mc0#, Mcl#) forming an XOR gate to compare new TAG placed on bit lines (BL, BL#) with the storage data (CC, CC#). If the storage data and the bit line values are different, the miss line (MISS#) will be pulled down.
• Each row in the CAM array (701) comprises a plurality of CAM cells with their MISS# line connected together. When any one bit in one row of the stored TAG is different from the TAG that is been looked up, the MISS# line will be low.
• the MISS# line (705) of each TAG row is used to control the word line (WL) of one corresponding RAM row. Only when the row with the same stored TAG as the look up TAG will be selected, so that its stored data can be read from the RAM array.
• Such CAM device in FIG. 7(a) is a powerful device for simultaneous lookup a large number of stored addresses, while reading out the desired data with the right addresses. Due to this parallel look up operation, prior art CAM does not have ECC protection. In order to assure that the results of a TAG lookup is correct, it is necessary to assure that there is no faulty bit in the whole TAG array during the lookup process.
• FIG. 8(a) is a block diagram for a CAM protected by ECC. This CAM device still have the same CAM array (801) for
• FIG. 8(b) is a flow chart showing the look up procedures for the CAM in FIG. 8(a). During the look up, both TAG and its ECC bits are compared. If there is no match, notification operation is carried out by the system as usual.
• TAG match If there is a TAG match while its ECC bits also match, data transmission of the matched data is carried out as usual. If there is a TAG match while its ECC bits do not match, that means it is a false match. It is required to notify the system about this false match and treat it as a mismatch. An attempt to fix the problem may be carried out by writing the correct value determined by ECC back into the CAM array. If there are more than one TAG match found in the TAG array, the one with ECC match is the real match. Only the correct data bit stream is transmitted, while an operation to fix the wrong TAG is also performed with a notification sent to the system about such an data error and correction events.
• the RAM array also can have its own ECC bits to protect RAM data.
• FIG. 8(d) Another example is to save ECC bits in a RAM array instead of the CAM array as shown in FIG. 8(c).
• the look up procedures are shown in FIG. 8(d). During a TAG look up, only TAG is compared. If there is no match, notification of no-matches found is carried out by the system as usual. If there is a TAG match, both data and ECC bits from the
• This ECC bits can be just for the TAG. It is also possible to include both data and TAG into the ECC calculations to protect both. After ECC calculation, if no errors are detected, transmission of the data and claim TAG hit is carried out by the system as usual. If errors are detected by ECC, it is necessary to notify the system about this false match and treat it as a mismatch.
• An attempt to fix the problem may be carried out by writing the correct value determined by ECC back into the CAM and RAM array.
• the example in FIG. 8(c) uses less resource than the example in FIG. 8(a). When there are multiple matches found in the TAG array, the structure in FIG. 8(c) can not distinguish which one is the right match.
• this invention further discloses a content addressable memory (CAM) device.
• the CAM memory device includes a plurality of memory-cell arrays for storing an array content therein provided for an data-access to an array based on a match with the array content.
• the CAM device further includes an error-check logic circuit for checking errors of the data access to each of the memory-cell arrays.
• the CAM device further includes an error-code storage means for storing an error-code check (ECC) bit for each of the memory-cell array used by the error-check logic circuit for checking errors of the data access to each of the memory-cell arrays.
• ECC error-code check
• each of the memory-cell array further storing an error-code check (ECC) bit generated by the error-check logic circuit for checking errors of the data access to each of the memory-cell arrays.
• the error-code storage means is a random access memory (RAM) device for storing the error-code check (ECC) bit for each of the memory-cell array used by the error-check logic circuit for checking errors of the data access to each of the memory-cell arrays.

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• For Increasing The Reliability Of Semiconductor Memories (AREA)
• Detection And Correction Of Errors (AREA)

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• 2002
  • 2002-03-25 CN CN 02104497 patent/CN1409492A/zh active Pending
  • 2002-04-15 WO PCT/US2002/011735 patent/WO2003023770A1/en not_active Application Discontinuation

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