Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
  • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B19/00—Programme-control systems
  • G05B19/02—Programme-control systems electric
  • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
  • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
  • G05B19/0428—Safety, monitoring
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B19/00—Programme-control systems
  • G05B19/02—Programme-control systems electric
  • G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
  • G05B19/406—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by monitoring or safety
  • G05B19/4063—Monitoring general control system
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/20—Pc systems
  • G05B2219/24—Pc safety
  • G05B2219/24026—Latch, block unlatch, unblock
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/20—Pc systems
  • G05B2219/24—Pc safety
  • G05B2219/24056—Portable, detachable module to input test signals, read test results
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/20—Pc systems
  • G05B2219/25—Pc structure of the system
  • G05B2219/25039—Clock
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/20—Pc systems
  • G05B2219/25—Pc structure of the system
  • G05B2219/25258—ASIC

Definitions

• the present invention in particular addresses the problem how a stable transfer of indications from the first reference clock domain to the second reference clock domain can be achieved for arbitrary phase relationships between the first and second reference clock.
• Fig. 2 shows a typical phase/frequency relationship between the clock domain A and the clock domain B for the example in Fig. 1.
• the raising or falling edges of the clock pulses do not match if the respective clock frequencies are not multiple integers of each other, i.e. the period length Ta is not an integer multiple of the period length Tb.
• the phase mismatch may vary in time, even if the respective clock frequencies are nominally integer multiples of each other, especially when the clock frequencies are generated from different sources.
• a new status indication SI (indicated with IN_STATUS in Fig. 2) may be clocked into the input storage means ISN synchronized to the first reference clock CLK_A, however, it may not be appropriately transferred and stored in the output storage means OSM when there is a phase and/or frequency mismatch.
• the United States Patent US 5,357,613 discloses a similar circuit as shown in Fig. 1, i.e. an input storage stage consisting of a multiplexer and a D flip flop and an output storage means also consisting of a multiplexer and a D flip-flop. A synchronization stage consisting of two serially connected D flip flops is also provided. Similarly as in Fig. 1, the circuit disclosed in this US-patent operates with two different reference clocks in the input domain and the output domain.
• clock domain A and clock domain B phase and frequency relations between indication latching and indication fetching clock domains.
• the classic synchronization stage approach as for example described in the aforementioned US-patents US-5,357,613 and US-5 , 638 , 015 , for example does not work if the fetching clock domain B works on a slower clock C K_B than the latching domain A, which operates on the clock CLK_A. Therefore, conventional techniques may fail to synchronize or do not deliver the stored (latched or detected) indication as fast as possible if clear at read functionality is required at arbitrary phase/ frequency relations . Therefore, conventionally there is not known a status indication detection apparatus and a status indication detection method which incorporates all three functions of latching, synchronization and update at the read time simultaneously without missing incoming status indications.
• the status indication detection apparatus comprises a further stage called the intermediate storage stage belonging to the latching domain.
• the intermediate storage stage is controlled in such a manner that a current status indication in the intermediate storage stage is locked for the time period of the hold signal such that the output storage stage can apply a readout pulse synchronous to said second reference clock during the hold signal duration.
• the readout pulse can be still synchronized to the second reference clock whilst the hold signal can be synchronized to the first reference clock.
• the read request signal can have any phase with respect to the first or second reference clock, preferably in accordance with one embodiment (claim 3/18) the read request signal is input into the output storage stage synchronized with said second reference clock. Thus, it can be guaranteed that the generation of the readout signal is also synchronized to said second reference clock.
• the hold signal is applied to said intermediate storage stage synchronized with said first reference clock. Furthermore, in accordance with another embodiment of the invention (claim 5/20) the status indication from the input storage means is kept in the input storage stage at least for one more first reference clock before the status indication is shifted to the intermediate storage stage.
• said control pulse generator in response to said read request signal, said control pulse generator generates a read lock pulse synchronized to said second reference clock and supplies it from said second reference clock domain to said first reference clock domain, said read lock pulse having a pulse length being the sum of a time duration needed to allow a safe synchronisation of said read lock pulse in said first reference clock domain with said first reference clock and a time duration to read said status indication from said intermediate storage stage into the output storage stage.
• the read lock signal can be transferred from the output clock domain to the input clock domain to serve as a basis for the generation of the hold signal.
• said synchronisation stage of said intermediate storage stage synchronizes said read lock pulse to said first reference clock and derives said hold signal with a pulse length of at least the duration of the synchronized read lock pulse from said synchronized read lock pulse.
• said synchronisation stage derives said hold signal in such a manner that it has a duration of at least one and preferably two periods of said first reference clock and covering at least one clock pulse of the second reference clock.
• an input update control means of said input storage stage generates a clear pulse for deleting status indications from the input storage stage, said clear pulse being generated after the ceasing of said hold signal.
• the read request signal is synchronized to said second reference clock and has a duration of one second reference clock period. That is, the read request signal only serves as a basis for generating the read lock pulse which can be much longer than one second reference clock period, for example for the case when the second reference clock has a much higher frequency than the first reference clock.
• the status indications are generated synchronized to the first reference clock.
• the status indications can be caught without additional synchronisation problems.
• said read status indications can comprise one bit in said input, intermediate and output storage stages.
• said read status indications comprise n bits in said input, intermediate and output storage stages.
• the output register can comprise an output multiplexer and a connected output D flip flop or an n-bit register (claim 30) .
• control pulse generator (claim 31) can comprise a control means receiving said read request signal and outputting said read lock signal and said readout signal.
• said intermediate register comprises an intermediate multiplexer and an intermediate D flip flop or an n-bit register.
• the synchronization stage comprises at least two serially connected D-flip flops.
• the input register (claim 34) can comprise two serially connected multiplexers and an input D flip flop.
• the input register can comprise an n-bit register capable of storing n bits simultaneously (claim 35) .
• the input update control means can comprise a D flip flop, two AND gates and an XNOR gate.
• the input update control means can comprise a D flip flop, one AND gate and a four input/single output multiplexer (claim 37) .
• the hold signal has a primary function to be long enough to cover the occurrence of at least one second clock reference pulse to prevent metastability in the output register and the hold signal is synchronized to the first reference clock to avoid metastability in the intermediate register.
• all operations (claim 38) in the input storage stage and in the intermediate storage stage are carried out synchronized to said first reference clock and all operations in said output storage stage are carried out synchronized to the second reference clock.
• the status indications may for example be generated by the surveillance of a plurality, e.g. 16, SDH/SONET data bit streams (claim 39) .
• Fig. 1 shows a status indication detection apparatus in accordance with the prior art, comprising an input storage stage ISM and an output storage stage OSM;
• Fig. 6 shows a sequential flow chart of generating signals and transferring status indications for the circuits in Fig. 3 and Fig. 4; and Fig. 7 shows a more detailed embodiment of the elements shown in Fig. 3, for the case of counted raw indications; and
• Fig. 8 shows a sequential flow chart of generating signals and transferring status indications for the circuits in Fig. 7.
• the status indication detection apparatus SIDM in accordance with the invention is similar to the apparatus in Fig. 1 in as far as it comprises an input storage stage INS into which status indications
• IN_STATUS are read synchronized to first reference clock CLK_A and an output storage stage OSS into which status indications IN_STATUS ' are input synchronized to a second reference clock CLK_B .
• the first and second reference clock C K_A, C K_B generally have a different phase and/or frequencies £&; fg as already illustrated in Fig. 2.
• the inventive apparatus in Fig. 3 comprises between the input storage stage INF and the output storage stage OSS a further intermediate storage stage ISS.
• Status indications in said input storage stage INS are shifted to said intermediate storage stage ISS synchronized to said first reference clock CLK_A, as is indicated with the inputting of the first reference clock CLK_A into the input and intermediate storage stages INS, ISS.
• the status indications IN_STATUS may be output for example by a hardware device (HW) , for example from a SONET/SDH application.
• HW hardware device
• the status indications can generally come from other sources and it is in the context of this invention for example irrelevant whether they are generated by hardware or software.
• the status indications have a bit-structure and depending on the logic used they will indicate a certain status depending on their level “0" or " 1 " .
• the status indications may occur synchronized to the first reference clock CLK_A.
• the status indication IN_STATUS need not necessarily be synchronized to the first reference clock CLK_A and need not necessarily be one period of the first reference clock CLK_A long.
• IN_STATUS may be synchronized to the first reference clock C K_A but may be longer than this first reference clock CLK_A period.
• a negative edge detection could be performed (for example similarly as with the gates 110, 111, 112 in Fig. 4 which is hereinafter explained with more details below) to input this status indication synchronized into the input storage stage.
• the status indication IN_STATUS may be asynchronous to the first reference clock CLK_A.
• a conventional synchronisation stage (comprising at least two serially connected flip-flops like 109, 110 in Fig. 4 to be explained with more details below) could be introduced with the limitation that the status indication frequency fc K IN ⁇ s smaller than the first reference clock frequency CLK_A.
• the result would be the same as in the previous example, namely that the status indication IN_STATUS is read into the input storage stage in such a manner that it is available in the input storage stage synchronized to said first reference clock CLK_A, as shown in Fig. 5a, 5b, 5c and in Fig. 6.
• the status indications IN_STATUS are latched in the input storage means INS, are then transferred to the intermediate storage stage ISS and are then transferred to the output storage stage OSS when a read request signal RDRQ is input into the output storage stage OSS.
• a processing device interested in the status indications may output such a read request signal RDRQ to the output storage stage OSS at any arbitrary timing although as explained above also an inputting only synchronized to the second reference clock CLK_B is possible.
• an input register INM of the input storage stage INS, an intermediate register INT of the intermediate storage ISS and an output register ORM of an output storage stage OSS are controlled with special control signals CLEAR_PULSE, LOCK and STROBE such that the first and second reference clocks CLK_A, CLK_B can have an arbitrary frequency and/or a phase relationship and still no status indication will be lost; i.e. every status indication IN_STATUS input to the input storage stage INS will be safely transferred into the output register ORM in response to the issuance of the read request signal RDRQ.
• a synchronization between the two clock domains A, B is provided on a functional basis and not by synchronization stages and is inseparately merged with a "clear at read” feature (as seen in Fig. 6) to build up a generic design applicable for arbitrary clock relationships between the first and second reference clock CLK_A, CLK_B .
• the read request signal RDRQ may be misaligned to the pulses of the second reference -clock CLK_B since in the general case it only provides an indication to the output storage stage OSS that a transfer of a status indication IN_STATUS ' into said output storage stage OSS is desired. However, it may be arranged that the read request signal RDRQ is indeed synchronized to the second reference clock CLK_B, as can be seen in Fig. 6.
• the read request signal RDRQ may be synchronized to the second reference clock CLK_B but it is for example misaligned to the first reference clock CLK_A of the first clock domain A, as indicated with the arrow IN.
• the read request signal RDRQ may preferably have the duration of one second reference clock period.
• a control pulse generator CG of the output storage stage OSS In response to receiving the read request signal RDRQ with the above-described configuration, a control pulse generator CG of the output storage stage OSS generates the read lock pulse RDLCK and the readout signal STROBE respectively applied to the input storage stage ISS and an output register ORM of the output storage stage OSS, as indicated with steps SI, S2 in Fig. 6.
• the read lock pulse RDLCK has a pulse length RDLCKL, RDLCKL' and RDLCKL' ' of at least one period length of the second reference clock CLK_B synchronized RDE, RDE', RDE' ' to the read request signal RDRQ.
• the read lock pulse RDLCK is to be transferred from the clock domain B to the clock domain A.
• the pulse RDLCK should preferably have a pulse length RDLCKL, RDLCKL' and RDLCKL'' of at least one period length Tclk_A of the first clock reference CLK_A.
• the read lock signal RDLCK (read lock) is derived from the read request pulse RDRQ synchronously to the second reference clock CLB_B . Basically, it is the pulse RDRQ widened synchronously to the second reference clock CLK_B.
• the readout signal STROBE has preferably a pulse length equal to one period of the second reference clock CLKJ3; in particular the readout signal STROBE with the single pulse period length is synchronized to the end of the read lock pulse RDLCK. Due to the different frequency relationships Fig. 5b and 5c clearly indicate the single pulse length of the STROBE signal whilst in Fig. 5a the STROBE signal has the same length as the RDLCK pulse. However, this is generally only true for the case f ⁇ > f B whilst in the general case in Fig. 5b and Fig. 5c it can be seen that the STROBE signal has generally a single pulse period synchronized to the end of the RDLCK pulse.
• a new status indication occurs synchronized to a pulse of the first reference clock CLK_A (as indicated with the arrow IN, IN' and IN' ' in Fig. 5a, 5b, 5c) in step STl and with successive occurrences of pulses of the first reference clock CLK_A the input register INS of the input storage stage INS remains set with a value corresponding to the status indication in step ST2 (as will be understood later from the description of Fig.
• the status indication IN_STATUS is not really "clocked" into the register STATREG of the input register INM because there is no direct connection between the status indication line IN_STATUS and the D-input of the register STATREG; a logical 1 on IN_STATUS merely causes a setting of the register STATREG via the gates 102, 101 until it is read out) .
• the readout pulse STROBE should preferably be generated for one second clock period at the end of the readout pulse STROBE.
• Fig. 5a, 5b, 5c and Fig. 6 shows the read out signal STROBE to be synchronized to the second reference clock CLK_B
• the read out pulse STROBE needs not necessarily be generated synchronized to the second reference clock CLK_B.
• Important is merely that neither changes of the read out signal STROBE itself nor changes in the intermediate register of the intermediate storage stage violate the setup-hold window of the output register of the output register stage.
• an outside clock C is used by the processing means PROC for generating the read request signal RDRQ and, for a relationship of T ⁇ LK" B ⁇ T CLK C wit a known maximum phase jitter, that the read out signal STROBE is composed of a plurality of pulses each having the period of CLK_B and that these pulses are placed under a positive edge of the output register (positive-edge triggered) in such a manner that the setup-hold window of the output register remains free of signal changes. Therefore, the read out signal STROBE may not necessarily be generated synchronized to said second reference clock CLK_B pulses.
• the read lock signal RDLCK is responsible that a synchronization stage SS in the intermediate storage stage ISS can generate the hold signal LOCK to be applied to the intermediate register INT of the intermediate storage stage for holding a current status indication in said intermediate register INT and for blocking a shifting of a new indication from said input to said intermediate storage stage INS; ISS.
• the hold signal LOCK has a duration LOCKL; LOCK ' ; LOCKL ' ' (shown in Fig. 5a, 5b, 5c) such that at least one clock pulse of the second reference clock CLK 3 occurs therein. This is generally true for all cases in Fig. 5a, 5b and 5c. Due to the different frequency relationships, in Fig. 5a the hold signal LOCK covers only one occurrence of second reference clock pulse, in Fig. 5b the duration of the hold signal LOCK covers two occurrences of a pulse and in Fig. 5c a hold signal LOCK covers a plurality of second reference clock pulses.
• the timing of generation the hold signal LOCK and the duration of the hold signal LOCK can be easily understood by looking at the time relationships of the read lock pulse RDLCK, the hold signal LOCK itself and the readout signal pulse STROBE. It is best to first look at the generation of RDLCK.
• RDLCK is mainly responsible for generating the hold signal LOCK, used for freezing the status indication transferred to the intermediate register INT.
• the duration of the read lock signal RDLCK mainly determines the duration of the hold signal LOCK. Essentially, the hold signal LOCK must be long enough that the data from the intermediate register INT can be moved to the output register ORM with the read pulse STROBE.
• the read lock signal must be long enough to allow a clocking or sampling of it into the clock domain A since otherwise the hold signal LOCK cannot be generated at all.
• the duration of the read lock pulse RDLCK is the sum of the time for the safe synchronization of RDLCK into the first clock domain A plus the transfer time for data from the intermediate register INT to the output register ORM.
• the duration of the hold signal LOCK solely depends from the length of the read lock signal RDLCK and is not automatically 2 clock periods of the first reference clock CLK_A long (although in Fig. 5a, 5b, 5c it happens to be of this duration to fulfil the above equation (1) with 2Tclk_A) .
• a typical duration for the hold signal LOCK to fulfil equation (1) is 2Tclk_A.
• the synchronization stage SS generates the hold signal LOCK synchronized to the first reference clock CLK_A because the synchronization stage SS receives the first reference signal CLK_A.
• the length RDLCKL (RDLCKL', RDLCKL'') will in principle determine the duration LOCKL of the hold signal LOCK
• the lengths LOCKL and RDLCKL will not be completely identical because basically the length RDLCKL is "mapped" or "synchronized" to the first reference clock CLK_A by the synchronisation stage .
• a hold signal LOCK which has a length covering at least one clock pulse of the second reference clock, is generated, preferably synchronized to the first reference clock CLK_A and, since it is at least of the duration of the read lock pulse RDLCK transferred to the first clock domain A, with a duration which allows the capturing of RDLCK in the clock domain A plus the necessary setup-hold time in accordance with the above equation (1) .
• the current status indication in the intermediate register INT is kept (for example by a clock cycling procedure as will be explained with the specific embodiment in Fig. 4) and that during the duration of the hold signal LOCK a shifting of a new indication from the input register INM to the intermediate register INT is blocked.
• the readout pulse STROBE and the hold pulse LOCK can be made, i.e. a hold signal LOCK covering at least one period of the second reference clock occurs some time after a read request pulse RDRQ, an important quasi-temporal relationship exists between the strobe pulse STROBE and the hold pulse LOCK.
• a readout pulse STROBE having a duration of one second clock pulse CLK_B period is placed at the end of the read request signal RDRQ synchronized to the second reference clock CLK_B (to avoid that the readout pulse STROBE is generated before the read lock pulse RDLCK being based on the read request signal RDRQ has been synchronized in the clock domain A) .
• the read lock signal RDLCK has a duration necessary for the synchronization in the clock domain A plus a duration necessary for the setup-hold (in accordance with equation (1) ) and at least of a duration allowing a shifting of data from the intermediate register to the output register.
• the hold signal LOCK has a duration at least of the same duration as the read lock signal RDLCK, i.e. long enough to allow the transfer of the data from the intermediate register to the output register.
• the readout pulse STROBE may occur exactly during the hold signal LOCK duration LOCKL, LOCKL', LOCKL' 1 .
• the strobe pulse STROBE always occurs synchronized to the second reference clock CLK_B and when this strobe pulse STROBE occurs during the duration LOCKL, LOCKL', LOCKL' ', then it is possible to readout, synchronized with the second reference clock CLK_B, whatever current status indication is held in the intermediate register INT.
• the readout signal STROBE will readout this status indication during the duration of the hold signal LOCK because from the lock start position LS, LS ' , LS ' ' of the hold signal LOCK, any current status indication in the intermediate register INT will be kept (through a cycling process) and the shifting of a new status indication into the intermediate register INT is blocked.
• any status indication present in the input register INM is shifted to the intermediate register INT synchronized to said first reference clock CLK_A, as indicated with step ST5 in Fig. 6.
• the hold signal LOCK has no direct influence on the input register INM.
• a detection of a negative edge of the hold signal LOCK (via the gates 112) leads to the generation of a primary clear pulse CP.
• this primary clear pulse CP was directly applied to the input register INM, CP would cause the input register INM, more specifically the register
• the clear pulse CLEAR_PULSE for allowing the take-in of a new status indication is only generated after the expiration of the hold signal LOCK and when the stored contents of the input register INM and the intermediate register INT coincide.
• the duration or pulse length LOCKL, LOCKL', LOCKL'' of the hold signal LOCK (in Fig. 5a: three first reference clock periods; in Fig. 5b: two first reference clock periods; in Fig. 5c: two first clock reference periods; i.e. at least two periods of said first reference clock) and the actual temporal occurrence of this hold signal LOCK is uncritical, as long as its duration is long enough to allow the placement of a strobe pulse STROBE synchronized to the second reference clock within the hold signal pulse LOCKL.
• the hold signal LOCK has a duration long enough to allow a transfer of data from the intermediate register INT to the output register ORM when the readout pulse STROBE is generated. Since the length of the hold signal LOCK is also based on the length of the read lock pulse RDLCK which itself must have a duration allowing its synchronisation in the clock domain A (plus the setup-hold time in the synchronisation stage SS) , a typical length for the hold signal LOCK (also covering at least one pulse of the second reference clock at which the read out strobe STROBE is generated) is a multiple, e.g. twice or three times the first reference clock CLK_A period. For the frequency relationships in Fig.
• the hold signal LOCK causing the holding of a current status indication in the intermediate storage stage and blocking a shifting of a new status indication from the input storage stage acts as a kind of "masking time" long enough for compensating any frequency and/or phase relationships of the two reference clocks CLK_A, CLK_B, as can easily be seen from Fig. 5a, 5b, 5c.
• Fig. 5c it is only important that indeed the readout pulse STROBE occurs within the time duration of the hold signal LOCK, however, it does not matter at all whether it is the second or third pulse within the hold signal duration LOCKL'' which is used for reading out the intermediate registers INT.
• the read out strobe STROBE is generated synchronized to the end of the read lock signal RDLCK to avoid that a read out occurs from the intermediate to the output register before the read lock pulse RDLCK is synchronized in the clock domain A and consequently the hold signal LOCK can be generated.
• step SI some time later (LS, LS ' , LS ' ' ) the hold signal LOCK covering at least one pulse period of the second reference clock is generated.
• LOCK has a duration long enough to allow a transfer of data from the intermediate register INT to the output register ORM when the readout pulse STROBE is generated. Since the length of the hold signal LOCK is also based on the length of the read lock pulse RDLCK which itself must have a duration allowing its synchronisation in the clock domain A (plus the setup- hold time in the synchronisation stage SS) , a typical length for the hold signal LOCK (also covering at least one pulse of the second reference clock at which the read out strobe STROBE is generated) is twice the first reference clock CLK_A period.
• a readout strobe STROBE is generated (S6) within the hold signal duration at the end of the read lock pulse
• control means CNTRL may comprise a simple shift register if all capturing clock domains are of the same frequency or a more complex state machine which is capable of handling access to a variety of differently clocked domains .
• an indication clkcnt_a of clock cycles may be defined.
• This indication clkcnt_a corresponds to the number of clock cycles in the domain A and facilitates the understanding of the time relationship in Fig. 8.
• Such a status indication detection apparatus and status indication detection method are particularly useful for monitoring SONET/SDH applications as hardware devices.

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