WO2003001387A1

WO2003001387A1 - Semiconductor integrated circuit and computer-readable recording medium

Info

Publication number: WO2003001387A1
Application number: PCT/JP2002/006194
Authority: WO
Inventors: Tetsuya Yamato; Hiromitsu Inada; Keisuke Matsuda; Kazuyuki Takada; Akihiro Uto
Original assignee: Renesas Technology Corp.
Priority date: 2001-06-26
Filing date: 2002-06-21
Publication date: 2003-01-03
Also published as: TWI221223B; JP2003006144A

Abstract

A plurality of different function areas are flexibly mapped by a protocol conversion unit (24) on a protocol conversion area (25) of memory (5) in a storage area of different function information constituting a serial packet, according to the preset value of a mapping register (33), and necessary information is distributed to the function areas, so as to perform parallel conversion of a serial packet, i.e., so that an interface protocol of the serial packet is converted into an interface protocol of the parallel packet. Since the memory (5) controlled by the so-called UMA method can flexibly store information of different data structures, it is possible to realize a high-speed data structure conversion without being limited by the memory access boundary and without applying a heavy load to the CPU.

Description

Description: Semiconductor integrated circuit and computer readable recording medium

The present invention relates to a packet interface technology using a serial packet. For example, a serial AT API (AT / attachment / packet / interface), USB (universal / serial / bus), or IEEE 139

The present invention relates to a semiconductor integrated circuit having an interface circuit conforming to the standard of 4, and a technology effective when applied to a so-called IP module relating to such an interface circuit. Background art

Currently, HDD (hard disk 'drive'), DVD-ROM (digital disk, video disk, ROM) and DVD which are built-in storage devices for PC (personal 'computer) use and information home appliance use In RAM, etc., AT A / AT API interface has established an overwhelming share. The ATA / ATAP interface defines an 8Z16-bit parallel transfer protocol, and the data signal is single-ended. Therefore, the transfer rate is about 10 OMB / sec because of the shift timing of each bit information and noise tolerance.

In recent years, in order to meet the market demand for large capacity and high speed for storage devices, the AT A / AT API interface (8 / 16-bit parallel transfer protocol) has been used to convert serial AT A (Serial- A high-speed serial transfer protocol standard called ATA) is in the development stage. You. The high-speed serial transfer protocol represented by the serial ATA (hereinafter, also simply referred to as a serial ATA) is, for example, for performing ATA / ATAP I interface serially using differential signals. The serial transfer eliminates the problem of timing shift between parallel data bits, and cancels common-mode noise components with differential signals to improve noise immunity. High-speed transfer such as sec is also possible.

As an example of a document describing AT A / AT API, there is an interface (pages 60 to 87) published by CQ Publishing Co., Ltd.

The present inventor has studied a conversion circuit for converting between AT A / A TAP I and serial ATA. This pre-charge circuit is a circuit that allows a CD-ROM, DVD-OM, DVD-RAM disk drive with AT A / AT API interface specifications to interface with a host device in accordance with Serial ATA. is there. Conventionally, as a serial / parallel conversion circuit, a USB-ATA / ATAP I conversion bridge circuit and an IEEE 1394-AT A / A API conversion circuit have been developed. AT A / A In parallel A / A interface such as TAP I, the host device transfers data, commands, status, etc. through the register of the interface circuit and controls the interface. Do. Therefore, in the serial / parallel conversion, it is necessary to perform conversion by recognizing data, commands, statuses, and the like with respect to information transferred as a bucket 1. When such processing is performed by software processing by the CPU, a situation in which the processing cannot be performed at a high transfer rate may occur. The transfer rate of the serial transfer protocol based on USB or IE EE 1394 is sufficiently lower than the transfer rate (about 100 MB / sec) on the ATA / ATAP I interface side. It seems that there are few problems. However, during high-speed transfer of about 150 MB / sec, 300 MB / sec, etc., which is expected to be realized in Serial ATA, the load on the CPU increases, so serial-to-parallel conversion reduces the processing capacity of the entire system. It has been found by the present inventor that they have an effect or that they cannot fully enjoy the advantages of speeding up by serial transfer.

Also, individual information such as data, commands, and status included in the serial packet is expected to have a different data structure or bit length. According to this, when recognizing and extracting data, commands, status, etc. from information transferred as a serial packet, information having such a difference is mapped to a work memory for each functional area and temporarily stored. It has been found by the present inventor that it is convenient for subsequent processing if stored in.

Further, the inventor of the present invention has provided a conversion interface circuit for converting the AT A / AT API and the serial AT A into a host interface of a recording information reproducing apparatus such as a CD-ROM or a DVD-RAM or an information recording / reproducing apparatus. We examined the case of application to circuits. The coder's decoder as a digital signal processing means for performing modulation processing for information recording and demodulation processing for information reproduction uses a work memory. The present inventor has considered using such a work memory also for serial-to-parallel conversion. According to this, the use form of such a work memory by the coder / decoder section is optimized or specific to the modulation / demodulation processing method by the coder / decoder section. When such a work memory is used for other purposes such as serial / parallel conversion, it must be possible to use the work memory regardless of the type of memory area used by the coder's decoder. The need has been clarified by the present inventors. In particular, in view of the fact that circuit module data is independently traded as IP module data, the work memory is fixed by another circuit module such as a coder / decoder unit configured using IP module data. The inventor has clarified the usefulness of preventing the occurrence of inconsistency or inconsistency in addressless rubbing between various use modes.

An object of the present invention is to provide a semiconductor integrated circuit capable of performing serial-parallel data conversion between serial and parallel without increasing the load on CPU.

An object of the present invention is to perform a process of recognizing and extracting a command or the like from information transferred as a serial packet by software processing by a CPU at a high speed when transferring a serial packet. In this case, it is difficult to increase the load on the CPU, the serial Z-parallel conversion does not affect the processing capacity of the whole system, or the parallel conversion of the serial packet can be performed without limiting the speed of the serial transfer. It is to provide a possible semiconductor integrated circuit.

Another object of the present invention is to recognize and extract data, commands, and the like having different data structures or bit lengths from information transferred as a serial bucket so that post-processing is convenient. An object of the present invention is to provide a semiconductor integrated circuit capable of parallel conversion of a serial packet.

Still another object of the present invention is to use work memory used by a digital signal processing means for performing a modulation process for recording information and a demodulation process for reproducing recorded information also for serial-to-parallel conversion of a serial packet. Then, no matter how the work memory area is used by the digital signal processing means (for example, such a work memory usage form by the digital signal processing means is determined by the digital signal processing means). Modulation and demodulation processing (Even if optimized or specific to the logical system), it is possible to perform address mapping with a high degree of freedom so that such a private memory can also be used for parallel conversion of serial packets. An object of the present invention is to provide a semiconductor integrated circuit capable of converting a serial packet into parallel data. Still another object of the present invention is to provide a discrepancy relating to address rubbing between a fixed use form of a work memory and another circuit module such as a digital signal processing means constituted by using IP module data. Another object of the present invention is to provide a semiconductor integrated circuit capable of preventing a mismatch from occurring and performing parallel conversion of a serial bucket.

Another object of the present invention is to provide a recording medium readable by a combination which stores circuit module data of the semiconductor integrated circuit, which can contribute to facilitating the design of the semiconductor integrated circuit according to each of the above objects. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] That is, the semiconductor integrated circuit performs conversion processing capable of performing parallel conversion of a serial packet including the first packet area (61) and the second packet area (62) using the memory (5). Circuit (1 2).

Focusing on the processing for the input serial packet, the conversion processing circuit stores the input serial packet in the first memory area (25A) and based on the information of the first packet area included in the input serial packet. 2 The control information of the packet area is transferred from the first memory area to the second memory area (25 D), and stores the data information of the second bucket area from the first memory area to the third memory area (26) based on the information of the first packet area included in the input serial packet. (3 1, 3 2) for performing the above-mentioned operations and a register unit (33) for defining the first to third memory areas. Noting that, the conversion processing circuit stores the input serial packet in the first memory area, and converts the control information of the second packet area into the first packet area based on the information of the first packet area included in the input serial bucket. From the memory area to the second memory area, and based on the information of the first packet area included in the input serial packet, the data information of the second bucket area is stored from the first memory area to the third memory area. , (3) A control unit (31) that stores the output serial packet generated by adding predetermined function information to the data to be output held in the memory area in the fourth memory area (25B). , 32 2), and a register section defining the first to fourth memory areas. The function information to be added to the data information to be output may be selected, for example, from the fifth memory area (25C).

According to the conversion processing circuit, the first to fourth memory areas are defined on the memory according to the initial setting contents for the register section by the CPU (6) or the like. It is expected that the mapping of the first to fourth memory areas is partially restricted. For example, the third area is defined as a buffer area for another circuit which processes data stored in the input serial packet and processes data information to be added to the output serial packet. If necessary, the third memory area may have to be determined according to the request for address matching by the other circuit. Even in such a case, for example, the address rubbing of the first, second, and fourth areas is determined under the above restrictions. The address may be freely determined by avoiding the moving address in the third memory area. In short, like the so-called UMA (Unified 'Memory' architecture), it is possible to flexibly map and use multiple different functional areas in memory.

With the address rubbing of the first to fourth memory areas determined in this way, the input serial packets are sequentially stored in the first memory area on the memory. At the time of storage, the serial information is stored in the first memory area in units of, for example, 8 bits or 16 bits in accordance with an address management unit (eg, a byte address in units of bytes) for the memory. The information of the serial packet temporarily stored in the first memory area is read therefrom, and subjected to decoding processing such as 8B10B, CRC error determination, and the like, and is performed according to the packet format specified by the packet format. It is separated into one bucket area and the second packet area. The first packet area contains information such as an operation code, and the contents of the second packet area are recognized in accordance with the result of decoding. For example, a command packet format for parallel AT A such as AT AZAT API is used. The conversion processing into evening packets and the like is executed, and control information such as parameters and commands is stored in the second memory area as an AT A / A API task file register. If data information is included in the second packet area, the data information is stored in the third memory area. The control information stored in the second memory area is used as access information or drive control information for, for example, a DVD-RAM drive using an ATA / ATAPI interface, and the data information stored in the third memory area. Is modulated by a digital signal processing circuit and used as a write data for a DV D-RAM drive or the like.

The data used for generating the serial bucket for output is, for example,

CD-ROM and DVD-D The playback data is demodulated by the signal processing circuit and stored in the third memory area from the digital signal processing circuit of the DVD-RAM drive. Control information or function information is added to the data information in the third memory area, and is stored in the fourth memory area as a serial packet that satisfies a predetermined packet format. The data read-accessed from the fourth memory area is output to the host device in a bit-serial manner as a serial packet.

As described above, the storage areas for the different functional information that make up the serial packet (the control information area of the first packet area, the control information area of the second packet area, and the data information area of the second packet area) Multiple different functional areas are flexibly mapped to the necessary information, and the necessary information is allocated to it. The parallel conversion of the serial packet, that is, the interface protocol of the serial packet is converted to the interface protocol of the parallel packet. Can be converted.

As a result, when performing processing to recognize and extract data, commands, etc. from information transferred as a serial bucket by software processing by the CPU, it is assumed that a serial bucket with a high transfer rate is used. Since the serial packet is temporarily buffered in the first memory area and the size of the first memory area can be determined flexibly, it is difficult to increase the load on the CPU, and the parallel conversion of the serial packet affects the processing capacity of the entire system. This allows parallel conversion of serial packets without limiting the speed of serial transfer.

As described above, data and commands with different data structures or bit lengths from information transferred as serial packets should be temporarily stored in memory in separate areas for convenient post-processing. Can be. For example, specifying the second memory area and the third memory area by limiting the memory access boundary If this is done in such a way that the DVD-RAM drive modulates and demodulates digital signal processing means, it can access serial packet control information and data overnight information without being restricted by memory access boundaries. Data processing can be speeded up.

As described above, when the work memory used by the coder / decoder unit as a digital signal processing unit for performing modulation processing for information recording and demodulation processing for recording information reproduction is also used for parallel conversion of a serial packet, etc. Even if the form of use of such a work memory by the coder / decoder section is optimized or specific to the modulation / demodulation processing method by the coder / decoder section, such a work memory can be used in parallel with serial packets. It is possible to perform high-response addressing that can be used for other purposes such as conversion.

As described above, the address mapping between the fixed use form of the memory by another circuit module such as the digital signal processing means configured using the IP module data which is dealt with independently is performed. It is easy to prevent the occurrence of inconsistencies or inconsistencies.

[2] A semiconductor integrated circuit according to another aspect of the present invention uses a memory (5) to perform parallel conversion of a serial packet including a first packet area (61) and a second packet area (62). And a conversion processing circuit (12) capable of performing the following.

Focusing on processing for an input serial packet, the conversion processing circuit includes first register means (RegS1, RegE1) for designating a first memory area allocated for storing an input serial packet. A second register setting means (RegS4, RegE4) for designating a second memory area allocated for storing control information of the second packet area of the serial packet stored in the first memory area; ), And the memory stored in the first memory area. Third register means e gS5) for specifying a third memory area for storing data information of the second packet area of the real packet, and a memory area corresponding to the set values of the first to third register means. And a control unit (31, 32) for performing control for storing the information of the input serial packet. The control unit distinguishes control information and data information of the second bucket area based on the information of the first bucket area.

When the conversion processing circuit pays attention to the processing of the input serial packet and the generation of the output serial packet, the conversion processing circuit designates a first register unit (RegS 1, Reeg S 1, Re gE1), and second register means (RegS4, R) for designating a second memory area allocated for storing control information of a second packet area of the serial packet stored in the first memory area. egE4) and a third memory area for storing data information of the second packet area of the serial packet stored in the first memory area and data information to be output by the serial packet. A third register means (RegS5); a fourth register means (RegS2, RegE2) for designating a fourth memory area for storing an output serial packet; Regis Evening Means And a control unit (31, 32) for controlling the storage of the information of the input serial bucket and the output serial packet in a memory area specified by the first bucket area, wherein the control unit is configured to control the first bucket area. Based on this information, the control information of the second packet area is distinguished from the overnight information.

Also according to the configuration of this conversion processing circuit, similarly to the above [1], storage areas for different function information constituting the serial packet (the control information area of the first packet area, the second packet area, and the second packet area). Area), a plurality of different functional areas are flexibly mapped to the memory, and the necessary information is allocated there, and the parallel conversion of serial packets is performed. Alternatively, protocol conversion can be performed.

The first packet area includes, for example, an operation code of a serial packet, and the first packet area includes information indicating a subsequent information amount.

As the serial packet, for example, serial ATAPI standard, USB standard, IEEE1394 standard, and the like can be assumed.

[3] From the viewpoint of facilitating the design of a semiconductor integrated circuit employing the above-described conversion processing circuit, a computer-readable recording medium (71) uses a computer (70%) to store a semiconductor integrated circuit to be formed on a semiconductor chip. ) Is stored in a manner readable by the computer. The circuit module data stored in the recording medium is a pattern data or a function for forming a first packet area and a conversion processing circuit capable of parallel conversion of a serial bucket including the first packet area on the semiconductor chip. Includes descriptive data. The conversion processing circuit stores an input serial packet in a first memory area, and controls control information of a second packet area from the first memory area based on information of the first packet area included in the input serial packet. (2) Stores data in the memory area, and performs processing for storing data of the second packet area from the first memory area to the third memory area based on the information of the first packet area included in the input serial packet. A control unit; and a register unit that defines the first to third memory areas.

Focusing on the generation of an output serial packet as well as the processing of an input serial packet, the conversion processing circuit, which is specified by the graphic pattern data or the function description data, stores the input serial packet in the first memory area. Storing the control information of the first bucket area from the first memory area to the second memory area based on the information of the first packet area included in the input serial packet, and storing the control information of the first packet area included in the input serial packet; Territory The data information of the second packet area is stored in the third memory area from the first memory area based on the information of the area, and predetermined function information is added to the data to be output held in the third memory area. The control unit includes a control unit that performs processing for storing the generated output serial bucket in the fourth memory area, and a register unit that defines the first to fourth memory areas.

Still another computer-readable recording medium (71) from the viewpoint of contributing to the simplification of the design or manufacture of a semiconductor integrated circuit employing the above-mentioned conversion processing circuit, uses a computer (70). The circuit module data to be designed by the computer is stored so as to be readable by the computer. The circuit module stored in the recording medium is a graphic pattern for forming a conversion processing circuit capable of parallel-to-parallel conversion of a serial packet including a first packet area and a second bucket area on the semiconductor chip. Includes data or function description data. The conversion processing circuit includes a first register for designating a first memory area allocated for storing the input serial packet, and control information for a second packet area of the serial bucket stored in the first memory area. Second register means for designating a second memory area allocated for storage, and a third memory area for storing data information of the second bucket area of the serial packet stored in the first memory area And a control unit that controls to store the information of the input serial packet in a memory area corresponding to a set value of the first to third register settings. The control section distinguishes the control information of the second bucket area from the overnight information based on the information of the first bucket area.

Focusing on output serial packet generation as well as processing on input serial packets, the conversion processing circuit, which specifies graphic pattern data or function description data, is assigned to storage of input serial packets. A first register means for designating a first memory area to be allocated and a second memory area allocated for storing control information of a second packet area of a serial bucket stored in the first memory area. A second register means for designating, and a third memory area for storing data information of the second packet area of the serial packet stored in the first memory area and data information to be output by the serial packet The third register means for specifying the first register, the fourth register means for specifying the fourth memory area for storing the output serial packet, and the memory area corresponding to the set value of the first to fourth register means. A control unit for performing control to store the information of the input serial packet and the output serial packet, wherein the control unit stores the information of the second packet area based on the information of the first packet area. It distinguishes between control information and overnight information.

If a semiconductor integrated circuit is designed using the circuit module data stored and provided in the recording medium, other circuit modules such as a coder 'decoder configured using other IP module data can be used. This makes it easy to prevent the occurrence of inconsistencies or inconsistencies in address mapping between the fixed use of memory and the fixed use of memory. Therefore, the design of a semiconductor integrated circuit employing the above conversion processing circuit can be facilitated.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an example of a host interface section included in a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a DVD drive to which the semiconductor integrated circuit according to the present invention is applied.

Figure 3 shows the DRAM protocol conversion area and codec area. It is explanatory drawing which shows the area division mapping example.

FIG. 4 is an explanatory diagram showing another example of region division mapping of a protocol conversion region and a codec region.

FIG. 5 is an explanatory diagram illustrating an operation flow of a parallel conversion process of a serial packet.

FIG. 6 is an explanatory diagram showing a state where data information obtained by parallel conversion processing of a serial bucket is stored in a codec area and control information is stored in a task file register area.

FIG. 7 is an explanatory diagram illustrating an example of a serial packet output processing flow.

Fig. 8 shows the fixed pattern for serial output added to the data information stored in the codec area obtained by the conversion processing to the serial packet and the control data contained in the string in the task file register area. FIG. 4 is an explanatory diagram showing a state temporarily held in a serial output data storage area.

FIG. 9 is an explanatory diagram showing an example of the IP module data together with a preview such as an integrated circuit design tool. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 2 shows an example of a DVD drive to which the semiconductor integrated circuit according to the present invention is applied. The DVD drive 1 is a disk drive capable of accessing a disk 3 such as a DVD-ROM, a DVD-RAM, and a CD-ROM, although not particularly limited, and a personal computer (simply a PC) serving as a host device. It is described as one of the peripheral devices. The data transmission between the DV D drive 1 and the PC 2 employs an interface specification using a serial packet such as serial ATA. The DVD drive 1 includes, but is not limited to, a disk controller 4 formed as a semiconductor integrated circuit, a DRAM (Dynamic Random Access Memory) 5 as an example of a memory, and a micro computer 6. Further, a read / write head, a read / write channel, and a read / write channel 7 having a read / write amplifier and the like are provided. In FIG. 2, a drive system such as a disk motor and a servo control system thereof are not shown. The microcomputer 6 includes a CPU (central processing unit), its operation program, a work area of the CPU, and appropriate input / output circuits.

The disk controller 4 includes, but is not limited to, a digital signal processing unit (a coder / decoder or a codec) that performs digital signal processing such as demodulation processing of information read from the disk 3 and modulation processing of information to be written to the disk. ) Section) 10, PC2, serial cape, host interface section 12 connected by a line 11, DRAM controller port 13, microcomputer interface section 14, audio interface section 15, etc. It is formed on one semiconductor substrate (or semiconductor chip) such as single crystal silicon. Although not particularly limited, the digital signal processing unit 10 includes a digital signal processing processor (DV D-DSP) 16 for modulation processing, a digital signal processing processor (C DD SP) 17 for demodulation processing, and a demodulated signal. A ROM decoder 18 that performs error correction on information, detection of a synchronization signal, and the like is realized by hardware and software.

The DRAM controller 13 controls the activation of a memory cycle for the DRAM 5 in response to an access request from the digital signal processing unit 10, host interface unit 12, and microcomputer 6. Modulation and demodulation of DRAM 5 by digital signal processor 10 It is used as a work area and a temporary storage area for sector data and the like, and as a buffer area and a work area when controlling the serial packet interface by the host interface unit 12. FIG. 1 shows an example of the host interface section 12. Although not particularly limited, the host interface unit 12 shown in the figure has a serial input FIF 020 and a serial output FIF 021 used for input and output of a serial packet, and has a parallel ATAATAPI interface. It has a parallel ATA / ATAPI input / output unit 22 used for parallel input / output by the face. Switching between serial input / output by the serial input FIFO 20 and serial output FIF 0 21 and parallel input / output by the parallel AT AZA TAPI input / output unit 22 is performed by a multiplexer (MUX) 23. The protocol converter 24 and the bus 46 are connected to the multiplexer 23. The operation of the protocol conversion unit 24 is determined according to an instruction from the micro computer 6 or an operation mode instruction from an external terminal together with the switching operation of the multiplexer 23 for the serial input / output or the parallel input / output. You.

The protocol conversion unit 24 performs protocol conversion control and the like such as parallel conversion of a serial packet and generation of a serial packet using the protocol conversion area 25 and the codec area 26 of the DRAM 5. . For example, in the protocol conversion control, serial packet parallel conversion is performed by buffering the input serial packet, analyzing the command of the buffered serial packet, extracting information from the serial packet, and buffering the extracted information. Also, a serial packet is generated by taking in buffered output data for output and adding functional information to the taken-in data information. At the time of buffering and information extraction processing at that time, the protocol conversion unit 24 In step 5, information storage processing such as the so-called UMA for storing the data of an arbitrary area in an arbitrary area or mapping processing of a memory area is performed. The protocol conversion unit 24 that performs such processing includes a control unit 30 that controls the entire protocol conversion sequence for protocol conversion, and a data processing unit 40 that performs data processing at the time of protocol conversion. They are roughly divided into

The control unit 30 performs sequence control for the protocol conversion control, address mapping control for the protocol conversion area 25, and the like. The controller 30 includes, for example, a sequencer 31 for controlling a protocol conversion sequence, an address calculator 32 for calculating an access address at the time of memory access, and a protocol conversion area 2 in the DRAM 5. It has a resisting area 33 for matting that defines 5 mappings.

The data processing unit 40 performs command analysis and information extraction operations for disassembly and generation of serial packets based on the sequence control and the address matching control by the control unit 30. The data processing unit 40 includes, for example, an input / output FIFO 41 for data storage at the time of protocol conversion, an encoding / decoding unit 42 for performing coding / decoding processing at the time of protocol conversion, and a serial CRC operation part 43, which realizes error detection of input data and error check code added to serial output data, bit shift circuit for alignment operation during serial data / parallel data conversion 44, a code detector 45 for detecting an operation code held in the decoded serial input data.

FIG. 3 shows an example of the area division into the protocol conversion area 25 and the codec area 26 of the DRAM 5.

The protocol conversion area 25 has a serial input data storage area (first memory area) 25 A and a serial output data storage area (fourth memory area) 2 It is divided into 5B, fixed pattern storage area for serial output (fifth memory area) 25C, and task file register area (second memory area) 25D. Each of the areas 25A to 25D is determined in accordance with the register setting value of the above-mentioned registering section for moving 33, and here, each of the areas 25A to 25D has its own address register RegSl to RegS4. The end address is determined by the set value of the register. The register register RegS1 and RegE1 are first register means for designating the serial input data storage area 25A, and the register register RegS4 and RegE4 are the task file registers. The second register means for designating the evening area 25D, the above-mentioned register RegS2, RegE2 are the fourth register means for designating the serial output data storage area 25B, and the registers RegS3, R egE3 constitutes the fifth register means for specifying the fixed pattern storage area for serial output.

The codec area 26 is not particularly limited, but is a codec-specific buffer area or code area in which data information to be demodulated by the codec unit 10 or modulated data information is stored in sector units. For the sake of convenience, two areas 26 A and 26 B capable of storing data for two sectors can be secured in the figure. The read operation for demodulating the data information stored in the codec area 26 and the access control for writing the modulated data information to the codec area 26 are not particularly limited. The codec section 10 performs this. On the other hand, access to write the data information extracted from the input serial packet to the codec area 26 and read access to the demodulated information written by the codec section 10 to the codec area 26 are performed by the codec. This is performed by the protocol conversion unit 24. In the example of FIG. 3, the protocol conversion unit 24 registers the register R eg S 5 (the third register register) to define the codec area 26. Stage). The size of each area 26A, 26B is a fixed value on the system determined by the data sector size. In this example, the register for specifying the size is not shown.

Although not particularly limited, in the codec area 26, optimized address rubbing is specified in accordance with a request for a digital signal processing algorithm or the like by the codec section 10, and the empty area is used as the protocol conversion area 25. Will be available. In short, the protocol conversion of the free address area of DRAM 5 or its mapping address, which was originally used as the work memory or buffer memory of the codec 10 in the parallel AT A / A TAP I interface, by the serial ATA interface It is intended to be diverted to. Even in such a case, the address mapping of the areas 25A to 25D is determined under the above-mentioned restrictions by appropriately setting a value in the mapping register section 33. It can be freely determined by avoiding the mapping address of the codec area 26. Therefore, it is possible to flexibly use the protocol conversion area 25 as a plurality of different functional areas in the DRAM 5, as in a so-called UMA (Unified'Memory Architecture).

FIG. 4 illustrates another example of the area division into the protocol conversion area 25 and the codec area 26. As shown in FIG. 4, when two core regions 26 A and 26 B are mapped separately, the above-mentioned regions 25 A to 25 D of the protocol conversion region 25 are located between the two regions. May be arranged. Here, in order to define the above-mentioned respective areas 25 A to 25 D of the protocol conversion area 25, the start address registers R eg S l to R eg S 4 and the height register R e defining the vertical size of the area are defined. gHl to Reg H4, a viral registry that defines the horizontal size of the region RegWl: Reg Use W4. The registers RegSl, RegHl, RegWl are the first register means for designating the serial input data storage area 25A, and the registers EgS4, RegH4, RegW4 are the task files. The second register means for designating the register area 25D; the register means RegS3, RegH3, and RegW3 are fourth register means for designating the serial output data storage area 25C; RegS2, RegS2, RegH2, and RegW2 constitute a fifth register procedure for specifying the fixed pattern storage area for serial output.

A first address register RegS5A, Reg5B (third resister means) is provided to define the two separated areas 26A, 26B of the codec area 26 respectively. . The size of each of the areas 26A and 26B is a fixed value on the system determined by the data sector size. In this example, the register for designating the area size is not shown.

In the area specifying method of FIG. 4, as in FIG. 3, even if there is a situation that the address mapping of the area 26 is determined under the constraints of the digital signal processing algorithm of the codec section 10, the codec is It is possible to freely determine the protocol conversion area 25 while avoiding the guessless:

Next, the operation of the parallel conversion process of the serial packet by the protocol conversion unit 24 will be described. Here, it is assumed that the addressing of the protocol conversion area 25 is the addressing of FIG.

FIG. 5 shows an example of an operation flow of a parallel conversion process of a serial packet. The serial packet PACKET input to the host interface 12 is sequentially written from the beginning to the serial input data storage area 25A via the serial input data FI F020, the MUX 23, and the memory controller 13. The write address is generated by the address operation unit 32 Is generated. FIG. 5 illustrates a serial input data storage area 25A having a width of 16 bits, in which two serial packets (serial input bucket 1 and serial input packet 2) are stored. Have been. The serial packet P ACKET is stored at any time, and when the storage address of the bucket information reaches the end address (end address) of the area 25A, the sequencer 31 accesses the address arithmetic unit 32 to access the area 25A. Register address as address: By reloading the start address of RegSl, the serial input data is stored from the first address of the re-input serial input data storage area 25A.

When the serial bucket is started to be stored in the area 25A, using this as a trigger, the sequencer 31 of the protocol conversion unit 24 sequentially reads data from the start address of the area 25A, and the input / output FIF 041 of the data processing unit 40. Send to The data internally transferred to the input / output FIFO 41 is the serial data information DAT A1 as encoded. The encoding / decoding unit 42 decodes the serial packet information by, for example, 8B10B conversion (S1). DATA 2 means the decoded serial packet information. Next, the decoded serial packet information DATA 2 is input to the CRC calculation unit 43, and a transfer error detection process of the serial packet is performed (S2). DATA3 means a serial packet that has undergone CRC error detection and correction processing. '

The serial packet information DATA 3 has a first packet area 61, a second packet area 62, and a CRC area 63. The first packet area 61 holds serial packet generation codes (codes), flags, transfer word count data indicating the amount of subsequent data in the first packet area, and the like. The second packet area 62 holds data information and control information. The data information is, for example, data written on a disk. Control information is a disk access operation This command is a command for specifying the operation, and is access control information such as the file name, and corresponds to the setting information for the disk file registry.

The serial bucket information DATA 3 is input to the code detector 45, the operation code is decoded, and a control operation corresponding to the decoded result is instructed to the sequencer 31 to make a first packet area 61 1 as a header. The other information is internally transferred to the sequencer 31 and the address calculator 32 (S3).

The sequencer 31 analyzes the header structure to execute the sequence determined by the operation code. The contents to be analyzed include the data transfer position and the task file register setting values, etc., and the data transfer position and the number of data held in the second packet area. By analyzing the header structure, the information in the second packet area is input to the bit shift circuit 44, and the data is aligned so that the beginning of the information is at the boundary of the byte address. Shift operation) is performed (S4). The transfer data information that is the data information of the second bucket area and / or the task file register setting value information that is the control information of the second packet area is temporarily stored in the input / output FIF041 ( S5). The control information temporarily held in the FIF 04 1 is stored in the task file register area 25 D of the DRAM 5 (S 6), and the data as the data to be written to the disk is stored in the core. It is stored in one deck area 26 (S7). At this time, the storage destination address is controlled by the sequencer 31 by referring to the address calculation unit 32 with reference to the set value of the mapping register unit 33.

As shown in FIG. 6, by the parallel conversion processing of the serial packet, as shown in FIG. 6, the data contained in the decoded serial packet with respect to the input serial packet is converted into a codec area 26. In A, control information is stored in evening file register evening area 25D. The stored state is This is equivalent to the data format that is input and stored at the LALER AT A / A TAP I input interface. The control information such as parameters and commands stored in the task file registry area 25D is used as disk access information or drive control information of, for example, a DVD-RAM drive employing an ATA / ATAP I interface, The decoding information stored in the codec area 26A is modulated by the codec section 10 and used as a writing data for a DVD-RAM drive or the like.

Next, the output processing of the serial packet will be described. Here, it is assumed that the mapping shown in FIG. 3 is adopted as the address mapping of the protocol conversion area 25.

FIG. 7 shows an example of a serial packet output processing flow. When a data read command to the PC (host device) 2 is issued, the sequencer 31 reads data from the disk via the microcomputer interface 14 via the microcomputer interface unit 14 and the micro computer via the codec unit 10. Issue a demodulation request for overnight. The codec 10 demodulates the data read from the disk, and the demodulated data is stored in the codec area 26 via the DRAM controller 13. Control information such as parameters that should be attached to this data information is stored in the task file registry area 25D. The sequencer 31 of the protocol conversion unit 24 uses the address operation unit 32 as a trigger when the transfer data storage end signal to the codec area 26 or Z and the task file register area 25 D is a trigger signal. Data information and / or control information is sequentially read from the disk area 26 and / or the task file register area 25D, and is temporarily stored in the input / output FIF 041 in the protocol conversion unit 24. Information stored in FIF 041 DAT A 11 is information that should constitute the second packet area 62 It is said. The overnight information and / or control information stored in the input / output FIFO 41 is input to the bit shift circuit 44 and aligned (S11). Further, the function information for the serial packet read from the fixed pattern storage area for serial output 25C is added to the first packet area 61 as header information (S12). DATA12 is information of the first packet area 61 and the second packet area 62 in the information of the serial packet before encoding. Next, in order to add a transfer error check code (CRC code) to the header section and the data section, the information is input to the CRC calculation section 43, and a CRC code is added to the end of the serial packet. (S13). The information 13 of the serial bucket to which the CRC code has been added is subjected to 8B10B code processing by the encoding / decoding section 42 (S14), and the encoded information is output to the serial output data DATA14. The data is temporarily stored in the output FI F041 and transferred to the serial output data storage area 25B via the DRAM controller 13 (S15). The serial packet stored in the serial output data storage area 25B is transferred from the serial output port to the PC 2 via the multiplexer 23 and the serial output data FIF 021 (S16).

As shown in FIG. 8, the data information read from the disk, demodulated and stored in the codec area 26A, and the task file register area 25D by the conversion processing to the serial packet as shown in FIG. The control information stored in the area is added with a fixed pattern for serial output from the area 25C, and is temporarily stored in the serial output data storage area 25B. The stored information is equivalent to the serial bucket data format. In short, the transfer data of the parallel AT A / AT API is converted into a serial packet. The serial packet held in the serial output data storage area 25B is output to the PC 2. When the interface via the parallel AT AZA TAPI input / output unit 22 is selected, the processing related to the parallel conversion of the serial packet and the serial conversion of the parallel information in the above control operation is omitted. The face operation may be performed, and a detailed description thereof will be omitted.

Next, from the viewpoint of facilitating the design of the disk controller 4 formed into a semiconductor integrated circuit, the design data of the circuit module 12 or the design data of the disk controller 4 itself is referred to as a so-called IP. A description will be given of providing as a module.

The circuit module data provided as an IP module includes at least graphic pattern data or HDL (hardware description language) or RTL (register) for forming the disk controller 12 on the semiconductor chip. · Transfer · Logic) and other functional descriptions. The pattern pattern data is a mask pattern data or electron beam drawing data. The function description data is a so-called program data, and a circuit or the like can be specified by symbol display by reading it into a predetermined design file.

Further, the scale of the IP module may be an LSI level such as a disk controller 4 illustrated in FIG.

As shown in FIG. 9, the data of these IP modules are used to design an integrated circuit to be formed on a semiconductor chip using a computer 70 such as a design tool. In the evening, the program is stored in a recording medium 71 such as a CD-ROM, a DVD-ROM or a magnetic tape so as to be readable by the computer # 0 and provided. For example, the data of the hard IP module corresponding to the host interface section 12 in FIG. 1 includes the mask pattern data D 1 for configuring the host interface section 12 and the host pattern data. Function description data D2 of the host interface section 12 and the host Verification data to enable simulation considering the relationship with other modules when designing the LSI by applying the data of the IP module of the interface section 1 2 D 3 Having.

If the semiconductor integrated circuit is designed using the circuit module data of the host interface section 12 provided and stored in the recording medium 71, it is possible to configure the semiconductor integrated circuit using other IP module data. It is easy to prevent the occurrence of inconsistency or inconsistency in address matching with the fixed use of memory by another circuit module such as the codec unit 10. More specifically, the IP module data of the codec section 10 basically realizes its own function, and one of the functions is determined by optimizing the use form of the RAM as a work area. Often. In such a case, if the usage of the work RAM is fixedly determined by the original logic of the other IP module based on its unique function, it is inevitable that the RAM access to the same address area will collide with each other. . At this time, the IP module data of the host interface module 12 is guaranteed to have a function of flexibly determining the address moving of the protocol conversion area 25. Therefore, the design of a semiconductor integrated circuit employing the host interface module 12 can be facilitated.

According to the data structure conversion between the serial packet and the parallel ATAZATAPI described above, it is possible to flexibly store information having different data structures on the memory 5 managed by the so-called UMA method, The protocol conversion unit 24 having the conversion function can realize high-speed data structure conversion or protocol conversion that is not restricted by the memory access boundary.

Data structure conversion between serial and parallel: Controls data in RAM 5 It is realized by processing by the data processing unit 40 based on the control of the unit 30. Therefore, by changing the processing routine, adding a cryptographic processing circuit, etc., it is possible to execute parallel AT A / A with other serial interface protocols. It is possible to implement a data structure between the TAP I interface and a protocol conversion function.

It has the function of shaping the data from both the so-called UMA protocol conversion memory area and the decoding memory area into the protocol of the external serial packet interface. It is easier to ensure consistency between the use of memoryries.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and it is needless to say that the invention can be variously modified without departing from the gist of the invention.

For example, the data and control information included in a serial packet may be transferred in separate serial packets. The input / output switching function by the parallel AT AZAT API may not be adopted.

Further, the semiconductor integrated circuit in which the host interface section 12 is on-chip is not limited to the configuration shown in FIG. 1. The DRAM 5 may be on-chip, and the microcomputer 6 or the CPU may be on-chip.

Further, the patterning on the memory such as the serial input data storage area and the task file register area used for the parallel conversion of the serial packet is not limited to the above example, and can be changed as appropriate. The memory for such an application is not limited to DRAM, but may be SRAM. In the case of DRAM, it is naturally a good idea to use a synchronous DRAM of the clock synchronous operation type.

Also, IP module data is stored in software IP module data. There may be. That is, the design data is composed of the function description data D2 and the verification data D3 except for the mask data D1 shown in FIG.

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

In other words, the storage areas for the different function information that make up the serial packet (the control information area of the first packet area, the control information area of the second packet area, and the data area of the second packet area) are stored in the memory. A plurality of different functional areas are flexibly mapped, necessary information is distributed there, and the parallel conversion of the serial packet, that is, the serial packet interface protocol is converted to the parallel packet interface. It can be converted to Ace protocol.

As a result, when performing processing such as recognizing and extracting commands and the like for information transferred as a serial packet by software processing by the CPU, a serial packet with a high transfer rate can be obtained. Assuming, the serial packet is temporarily buffered in the first memory area, and the size of the first memory area can be flexibly determined. Therefore, it is difficult to increase the load on the CPU, and the parallel conversion of the serial packet is performed by the entire system. The parallel conversion of the serial packet can be performed without affecting the performance or limiting the speed of the serial transfer.

As described above, data, commands, and the like having different data structures or bit lengths from information transferred as serial packets are temporarily stored in a memory in separate areas for convenient post-processing. be able to.

From the above, when the work memory used by the digital signal processing means for performing modulation processing for information recording and demodulation processing for recording information reproduction is also used for parallel conversion of serial packets, etc. processing Even if the use form of such a work memory by the means is optimized or specific to the modulation / demodulation processing method by the digital signal processing means, such a work memory can be used for other purposes such as parallel conversion of a serial packet. It is possible to perform flexible dressing that can be used for various purposes.

Due to the above, the inconsistency or inconsistency of address matching with the fixed use form of the memory by other circuit modules such as digital signal processing means configured using the IP module data is generated. It is easy to prevent it before it happens. Therefore, if the semiconductor integrated circuit is designed using the circuit module data stored and provided on the recording medium, the design of the semiconductor integrated circuit employing the conversion processing circuit can be facilitated. Industrial applicability

The present invention can be widely applied not only to DVD drives, but also to CD-ROM, CD-RW (compact / disk-rewritable), MO (porcelain / optical) disk drives, and the like. is there. Further, the present invention can be widely applied to serial interfaces other than disk drives.

Claims

The scope of the claims

1. having a conversion processing circuit capable of performing parallel conversion of a serial packet including a first packet area and a second packet area using a memory,

The conversion processing circuit stores an input serial packet in a first memory area and transmits control information of a second packet area from the first memory area based on information of the first packet area included in the input serial packet. A process of storing data in the second memory area and storing data of the second packet area from the first memory area to the third memory area based on the information of the first packet area included in the input serial packet. A semiconductor integrated circuit, comprising: a control unit for performing the following; and a register unit for defining first to third memory areas on the memory.

2. It has a conversion processing circuit capable of using a memory to convert a serial packet including the first bucket area and the second bucket area into parallel and generate a serial packet,

The conversion processing circuit stores an input serial packet in a first memory area, and controls control information of a second packet area from the first memory area based on information of the first packet area included in the input serial packet. In the memory area, based on the information in the first bucket area included in the input serial bucket, the data in the second packet area is stored in the third memory area from the first memory area. A control unit for performing a process of storing an output serial packet generated by adding predetermined function information to the data to be output held in the memory area in a fourth memory area; And a register portion defining a fourth memory area.

3. The control unit outputs data to be stored in the third memory area to be output. 3. The semiconductor integrated circuit according to claim 2, wherein function information to be added is selected from a fifth memory area.

4. The method according to claim 1, wherein the first packet area includes an operation code of a serial packet and information indicating a subsequent information amount in the first packet area. Semiconductor integrated circuit.

5. The semiconductor integrated circuit according to claim 4, wherein the register unit has a CPU interface capable of connecting a CPU capable of initially setting information for defining a memory area.

6. The semiconductor integrated circuit according to claim 4, wherein the register unit has a CPU for initial setting information for defining a memory area.

7. The semiconductor integrated circuit according to claim 2, wherein said semiconductor integrated circuit comprises said memory.

8. Having a conversion processing circuit capable of performing parallel conversion of serial packets including the first packet area and the second bucket area using the memory,

The conversion processing circuit includes: first register means for designating a first memory area to be allocated for storing an input serial packet; and control information of a second packet area of the serial packet stored in the first memory area. Second register means for designating a second memory area allocated for storing data, and a third memory for storing data of the second packet area of the serial bucket stored in the first memory area. A third register unit for designating an area; and a control unit for performing control for storing information of the input serial packet in a memory area corresponding to a set value of the first to third register units. A semiconductor integrated circuit for distinguishing control information and data information in a second packet area based on the information in the first bucket area.

9. A semiconductor integrated circuit having a conversion processing circuit capable of performing parallel conversion of a serial packet including a first packet area and a second packet area using a memory and generation of a serial packet,

The conversion processing circuit includes: first register means for designating a first memory area allocated to storage of an input serial packet; and control information of a second packet area of the serial packet stored in the first memory area. The second register means for designating a second memory area allocated to store the data, and output by the serial packet and the data of the second packet area of the serial packet stored in the first memory area. Third register means for designating a third memory area for storing data to be stored, fourth register means for designating a fourth memory area for storing an output serial packet, and the first to fourth registers. And a control unit for controlling the storage of the input serial packet information and the output serial packet in a memory area specified by the evening means. The semiconductor integrated circuit, characterized in that based on the information of one packet region is intended to distinguish control information and de Isseki information of the second packet region.

10. The method according to claim 8, wherein the first packet area includes an operation code of a serial packet, and information indicating a subsequent information amount in the first packet area. Semiconductor integrated circuit.

11. The semiconductor integrated circuit according to claim 8, wherein the serial bucket conforms to one of serial ATAPI standard, USB standard, and IEEE 1394 standard. circuit.

12. Digital signal processing means used for recording / reproducing information on / from a recording disk, wherein the digital signal processing means comprises an input serial bucket stored in the first memory area and stored in the third memory area. The third data is modulated as the information to be output by serial packet 10. The semiconductor integrated circuit according to claim 9, wherein demodulation processing is performed on data to be stored in a memory area.

13. A recording medium in which a circuit module for designing a semiconductor integrated circuit to be formed on a semiconductor chip using a computer is stored readable by the computer, and is stored in the recording medium. The circuit module data includes graphic pattern data or function description data for forming a conversion processing circuit capable of parallel conversion of a serial packet including the first packet area and the first bucket area on the semiconductor chip,

The conversion processing circuit stores an input serial packet in a first memory area, and transmits control information of a second packet area from the first memory area to a second information based on information of the first packet area included in the input serial packet. A control unit that stores the data information of the second packet area from the first memory area to the third memory area based on the information of the first packet area included in the input serial bucket; A computer-readable recording medium, comprising: a register section defining the first to third memory areas.

14. A recording medium in which circuit module data for designing a semiconductor integrated circuit to be formed on a semiconductor chip using a computer is stored readable by the computer, and is stored in the recording medium. The obtained circuit module data is used for forming a pattern processing circuit for forming a conversion processing circuit capable of parallel conversion of a serial packet including the first packet region and the second packet region and generation of the serial packet on the semiconductor chip. Including function description data,

The conversion processing circuit stores an input serial packet in a first memory area, and based on information of the first packet area included in the input serial packet. Control information of the first packet area from the first memory area to the second memory area, and based on the information of the first packet area included in the input serial packet, the data information of the second packet area is stored in the first memory area. From the area to the third memory area, and store the output serial bucket generated by adding predetermined function information to the data to be output held in the third memory area in the fourth memory area. A recording medium readable by a combination, comprising: a control unit for performing processing; and a register unit for defining the first to fourth memory areas.

15. A recording medium in which a circuit module for designing a semiconductor integrated circuit to be formed on a semiconductor chip by using a computer is stored readable by the computer, and is stored in the recording medium. The circuit module data includes graphic pattern data or function description data for forming a conversion processing circuit capable of parallel conversion of a serial packet including the first packet area and the second packet area on the semiconductor chip. Including

The conversion processing circuit includes a first register for designating a first memory area allocated for storing an input serial packet, and control information for a second packet area of the serial packet stored in the first memory area. Second register means for designating a second memory area allocated for storage, and designating a third memory area for storing data information of the second packet area of the serial packet stored in the first memory area A third register unit; and a control unit that controls to store information of the input serial packet in a memory area corresponding to a set value of the first to third register units. A computer readable recording medium characterized by distinguishing control information and data information of a second packet area based on information of one packet area.

16. A recording medium in which a circuit module for designing a semiconductor integrated circuit to be formed on a semiconductor chip by using a computer is stored readable by the computer, and is stored in the recording medium. The generated circuit module data is converted into a graphic pattern data for forming a conversion processing circuit capable of parallel conversion of a serial packet including the first packet area and the second packet area and generation of the serial packet on the semiconductor chip. Evening or function description

The conversion processing circuit includes a first register unit for designating a first memory area allocated for storing an input serial packet, and a control unit for controlling a second packet area of a serial packet stored in the first memory area. Second register means for designating a second memory area allocated to store information, and output by data and serial packet of the second packet area of the serial packet stored in the first memory area Third register means for designating a third memory area for storing data to be stored, fourth register means for designating a fourth memory area for storing an output serial packet, and the first to fourth means. A control unit for performing control for storing the information of the input serial packet and the output serial packet in a memory area corresponding to a setting value of a register unit, wherein the control unit is configured to A computer-readable recording medium for distinguishing between control information and data in a second packet area based on information in a first packet area.

17. The serial packet according to any one of claims 13 to 16, wherein the serial packet conforms to one of serial ATAP standard, USB standard, and IEEE 1394 standard. Or a recording medium readable by the combination according to item 1.