JP2003006144A - Semiconductor integrated circuit and computer-readable recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize data structure conversion between a serial packet and a parallel packet, without causing increase in the load of a CPU. SOLUTION: A protocol conversion part (24) flexibly maps a plurality of different function areas into an area (25) for protocol conversion of a memory (5) according to a set value of a register part (33) for mapping, with respect to a storage area for different pieces of function information constituting a serial packet, allocates needed information to the plurality of different function areas and performs serial packet conversion, that is, converts interface protocol of the serial packet into an interface packet of a parallel packet. Since information of different data structure can be flexibly stored on the memory 5 managed with the so-called UMA(unified memory architecture) system, it is possible to realize high-speed data structure conversion, without being affected by the limitation of a memory access boundary or imposing a large load on a CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet interface technology using serial packets.
The invention is applied to a serial ATAPI (AT Attachment Packet Interface), a USB (Universal Serial Bus), or a semiconductor integrated circuit having an interface circuit conforming to the IEEE 1394 standard, and a so-called IP module relating to such an interface circuit. And effective technology.

[0002]

2. Description of the Related Art Currently, HDD (hard disk drive), D which is a built-in storage device for PC (personal computer) use / information home appliance use
VD-ROM (Digital Video Disc-RO
M), DVD-RAM, etc., ATA / ATAP
The I interface has established an overwhelming market share. A
The TA / ATAPI interface defines an 8 / 16-bit parallel transfer protocol, and data signals are single-ended. Therefore, the transfer rate is about 100 MB / sec from the viewpoint of shift timing change in each bit information and noise resistance.

In recent years, in order to meet the market demand for large capacity and high speed for storage devices, ATA / ATAP
A high-speed serial transfer protocol standard called Serial ATA (Serial ATA) from the I interface (8 / 16-bit parallel transfer protocol) is in the development stage. A high-speed serial transfer protocol typified by the serial ATA (hereinafter, also simply referred to as serial ATA) is, for example, a serial ATA / ATAPI interface using differential signals.
Since it is serial transfer, it is not necessary to consider the shift of the change timing between parallel data bits as a problem, and the common-mode noise component can be canceled by the differential signal to improve the noise resistance, such as about 150 MB / sec, 300 MB / sec, etc. High-speed transfer is also possible.

As an example of a document describing ATA / ATAPI, there is an interface (pages 60 to 87) issued by CQ Publishing Co., Ltd.

[0005]

DISCLOSURE OF THE INVENTION The present inventor has found that ATA / A
A conversion bridge circuit between TAPI and serial ATA was examined. This bridge circuit uses ATA / ATAPI
Interface specification CD-ROM, DVD-ROM,
It is a circuit for interfacing a DVD-RAM disk drive with a host device in conformity with Serial ATA.
As described above, as the serial / parallel conversion bridge circuit, a USBATA / ATAPI conversion bridge circuit, an IEEE1394ATA / ATAPI conversion bridge circuit, and the like have been conventionally developed. In a parallel ATA interface represented by ATA / ATAPI, a host device transfers data, commands, statuses, etc. through a register of an interface circuit to perform interface control. Therefore, in the serial / parallel conversion, it is necessary to recognize the data, the command, the status, etc. of the information transferred as a packet and perform the conversion. When such processing is performed by software processing by the CPU, it may occur that the processing may not be in time at a high transfer rate. USB or IE
Since the transfer rate of the serial transfer protocol according to EE1394 is sufficiently lower than the transfer rate (about 100 MB / sec) on the ATA / ATAPI interface side, it is considered that there is little problem in that respect. However, about 150M expected to be realized in Serial ATA
During high-speed transfer such as B / sec, 300 MB / sec, etc., the load on the CPU increases, so the serial-to-parallel conversion affects the processing capacity of the entire system, or the advantage of speed-up by serial transfer cannot be fully enjoyed. Have been found by the inventor.

Further, it is expected that individual information such as data, commands and statuses contained in the serial packet have different data structures or bit lengths. According to this, when recognizing and extracting data, commands, status, etc. from the information transferred as a serial packet, the information having such a difference is temporarily stored by mapping it into the work memory for each functional area. It was found by the present inventor that this would be convenient for subsequent processing.

Further, the inventor has found that such ATA / ATA
CD-R conversion bridge circuit between PI and serial ATA
The case of applying to a recording information reproducing apparatus such as OM or DVD-RAM or a host interface circuit of the information recording / reproducing apparatus was examined. A coder / decoder unit as a digital signal processing means for performing a modulation process for recording information and a demodulation process for reproducing information uses a work memory.
The present inventor considered using such a work memory also for serial / parallel conversion. According to this, the usage pattern of such a work memory by the coder / decoder unit is optimized or unique to the modulation / demodulation processing method by the coder / decoder unit. When such a work memory is used for other purposes such as serial / parallel conversion, it can be used regardless of how the coder / decoder uses the memory area. The need was identified by the inventor.

Particularly, in view of the situation where the circuit module data is traded as the IP module data alone,
It is possible to prevent the occurrence of a discrepancy or inconsistency in address mapping with a fixed usage mode of a work memory by another circuit module such as a coder / decoder unit configured using IP module data. The usefulness of this was revealed by the present inventor.

An object of the present invention is to provide a semiconductor integrated circuit capable of performing serial / parallel data structure conversion without increasing the load on the CPU.

An object of the present invention is to improve the transfer rate of serial packets at a high speed when the CPU performs software processing for recognizing and extracting data, commands, etc. from information transferred as serial packets. Even so, it is difficult to increase the load on the CPU, the serial / parallel conversion does not affect the processing capability of the entire system, or the parallel conversion of serial packets is possible without limiting the speedup of serial transfer. To provide a circuit.

Another object of the present invention is to recognize data, commands, etc. having different data structures or bit lengths from information transferred as a serial packet, by recognizing and extracting them for convenient post-processing, thereby serializing. It is to provide a semiconductor integrated circuit capable of parallel packet conversion.

Still another object of the present invention is to use a work memory used by a digital signal processing means for performing a modulation process for recording information and a demodulation process for reproducing recorded information for serial / parallel conversion of serial packets. At this time, regardless of the usage form of the work memory by the digital signal processing means (for example, such usage form of the work memory by the digital signal processing means is compared with the modulation / demodulation processing method by the digital signal processing means). A semiconductor device capable of parallel conversion of serial packets, which can perform address mapping with a high degree of freedom to enable such work memory to be used for parallel conversion of serial packets (even if optimized or specific). It is to provide an integrated circuit.

Still another object of the present invention is a discrepancy in address mapping between a fixed use mode of a work memory by another circuit module such as a digital signal processing means configured by using IP module data. Another object of the present invention is to provide a semiconductor integrated circuit capable of parallel conversion of serial packets by preventing the occurrence of mismatch.

Another object of the present invention is to provide a computer-readable recording medium storing circuit module data of the semiconductor integrated circuit, which can contribute to facilitation of design of the semiconductor integrated circuit according to each of the above objects. Especially.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

[1] That is, the semiconductor integrated circuit utilizes the memory (5) to generate the first packet area (61) and the second packet area (61).
It has a conversion processing circuit (12) capable of parallel conversion of a serial packet including a packet area (62).

Focusing on the processing for the input serial packet, the conversion processing circuit has the first memory area (25
The input serial packet is stored in A), the control information of the second packet area is stored from the first memory area to the second memory area (25D) based on the information of the first packet area included in the input serial packet, and the input information is input. A control unit (31, 32) for performing a process of storing the data information of the second packet area from the first memory area to the third memory area (26) based on the information of the first packet area included in the serial packet.
And a register unit (33) defining the first to third memory areas.

Focusing on the generation of the output serial packet as well as the processing of the input serial packet, the conversion processing circuit stores the input serial packet in the first memory area and stores the information of the first packet area included in the input serial packet. Based on the information of the first packet area contained in the input serial packet, the control information of the second packet area is stored in the first memory area from the first memory area based on the information of the first packet area. To the third memory area, the output serial packet generated by adding predetermined function information to the data information to be output held in the third memory area is generated in the fourth memory area (25B).
And a register unit that defines the first to fourth memory areas. The function information to be added to the data information to be output may be selected from the fifth memory area (25C), for example.

According to the conversion processing circuit, the CPU (6)
The first to fourth memory areas are defined on the memory in accordance with the initial setting contents of the register unit by the above. It is expected that some restrictions will be imposed on a part of the mapping of the first to fourth memory areas. For example, if the third area needs to be defined as a buffer area for another circuit that processes the data information of the input serial packet stored therein or the data information that should be added to the output serial packet, The third memory area may have to be determined according to a request for address mapping by another circuit. Even in such a case, for example, the address mapping of the first, second, and fourth areas may be freely determined by avoiding the mapping address of the third memory area determined under the above constraint. In short, like a so-called UMA (Unified Memory Architecture), it is possible to flexibly map and use a plurality of different functional areas in the memory.

With the address mapping of the first to fourth memory areas determined in this way, the input serial packets are sequentially stored in the first memory area on the memory. When storing, address management unit for memory
The serial information is divided into, for example, 8-bit or 16-bit units and stored in the first memory area according to (for example, a byte address in byte units). The information of the serial packet temporarily stored in the first memory area is read from the information and is used for decoding processing such as 8B10B or CRC.
An error determination or the like is performed, and the packet is separated into a first packet area and a second packet area defined by the packet format. The first packet area contains information such as an operation code, and the contents of the second packet area are recognized according to the decoding result, and conversion processing into a command packet or data packet for parallel ATA such as ATA / ATAPI is performed. The second memory area is executed and ATA /
Control information such as parameters and commands is stored as an ATAPI task file register. If the second packet area contains data information, the data information is stored in the third memory area. The control information stored in the second memory area is used as disk access information or drive control information for a DVD-RAM drive adopting an ATA / ATAPI interface, and the data information stored in the third memory area is a digital signal. The data is modulated by the processing circuit and used as write data for a DVD-RAM drive or the like.

The data information used for generating the output serial packet is, for example, CD-ROM or DVD-RA.
This is reproduction data demodulated by the digital signal processing circuit for format data such as M, and is stored in the third memory area from the digital signal processing circuit of the DVD-RAM drive. Control information or function information is added to the data information in the third memory area and stored in the fourth memory area as a serial packet satisfying a predetermined packet format. The data read-accessed from the fourth memory area is output as a serial packet bit serially to the host device.

As described above, the storage areas (the first packet area and the second packet area) for storing the different function information constituting the serial packet are provided.
A plurality of different functional areas are flexibly mapped to the memory for the control information area of the packet area and the data information area of the second packet area, and the necessary information is distributed to the functional areas to perform parallel conversion of the serial packet, that is, A serial packet interface protocol can be converted into a parallel packet interface protocol.

As a result, when the CPU performs software processing to recognize and extract data, commands, etc. from information transferred as a serial packet, assuming a serial packet with a high transfer rate, Since the serial packet is temporarily buffered in the first memory area and the size of the first memory area can be flexibly determined, it is difficult to increase the load on the CPU.
The parallel conversion of serial packets can be performed without affecting the processing capability of the entire system or limiting the speedup of serial transfer.

From the above, data, commands, etc., having different data structures or bit lengths from information transferred as a serial packet can be temporarily stored in the memory in divided areas for convenient post-processing. it can. For example,
If the second memory area and the third memory area are specified without being restricted by the memory access boundary, the DVD
-The digital signal processing means for modulation and demodulation of the RAM drive can access the control information and data information of the serial packet without being restricted by the memory access boundary, and the high speed data processing can be realized.

From the above, when the work memory used by the coder / decoder unit as the digital signal processing means for performing the modulation process for recording information and the demodulation process for reproducing recorded information is also used for parallel conversion of serial packets, etc. , Even if the usage pattern of such a work memory by the coder / decoder unit is optimized or unique to the modulation / demodulation processing method by the coder / decoder unit,
Such work memory can be used for other purposes such as parallel conversion of serial packets, and address mapping with high flexibility can be performed.

As a result of the above, there is a discrepancy in address mapping between the fixed use mode of the memory by another circuit module such as a digital signal processing means configured by using the IP module data which is independently traded, or It is easy to prevent the occurrence of inconsistency.

[2] A semiconductor integrated circuit according to another aspect of the present invention uses a memory (5) to perform parallel conversion of a serial packet including a first packet area (61) and a second packet area (62). Possible conversion processing circuit (12)
Have.

Focusing on the processing on the input serial packet, the conversion processing circuit stores in the first memory area the first register means (RegS1, RegE1) for designating the first memory area allocated for storing the input serial packet. Second register means (RegS4, RegE) designating a second memory area allocated to store control information of the second packet area of the stored serial packet.
4) and third register means (RegS5) for designating a third memory area for storing data information of the second packet area of the serial packet stored in the first memory area.
And a control unit (31, 32) for controlling to store the information of the input serial packet in the memory area corresponding to the set values of the first to third register means. The control unit distinguishes control information and data information of the second packet area based on the information of the first packet area.

Focusing on the processing for the input serial packet and the generation of the output serial packet, the conversion processing circuit specifies the first memory means (Reg) for designating the first memory area allocated for storing the input serial packet.
S1, RegE1) and a second memory area that is assigned to store control information for the second packet area of the serial packet stored in the first memory area.
Register means (RegS4, RegE4) and the first
Third register means (RegS5) for designating the third memory area for storing the data information of the second packet area of the serial packet stored in the memory area and the data information to be output by the serial packet, and storing the output serial packet A fourth register means (RegS2, RegE2) for designating a fourth memory area, and the first to fourth
And a control unit (31, 32) for controlling the storage of the input serial packet information and the output serial packet in a memory area corresponding to the designation by the register means, and the control unit stores information in the first packet area. Based on this, the control information and the data information of the second packet area are distinguished.

Also according to the configuration of this conversion processing circuit, similarly to the above-mentioned [1], the storage areas (the first packet area, the control information area of the second packet area, and the second packet area) of the different function information which form the serial packet are formed. Data area), a plurality of different functional areas can be flexibly mapped in the memory, and necessary information can be distributed to the parallel functional conversion or protocol conversion of the serial packet.

The first packet area includes, for example, an operation code of a serial packet, and information indicating the subsequent information amount in the first packet area.

As the serial packet, for example, the serial ATAPI standard, the USB standard, and the IEEE13 standard are used.
The 94 standards and the like can be assumed.

[3] From the viewpoint of facilitating the design of a semiconductor integrated circuit that employs the conversion processing circuit, a computer-readable recording medium (71) is a computer-readable recording medium (71) which is a semiconductor integrated circuit to be formed on a semiconductor chip. 7
Circuit module data for designing using 0) is stored so that it can be read by the computer. The circuit module data stored in the recording medium is the first
It includes graphic pattern data or function description data for forming a conversion processing circuit capable of parallel conversion of a serial packet including a packet area and a first packet area on the semiconductor chip. The conversion processing circuit stores the input serial packet in the first memory area, and transfers the control information of the second packet area from the first memory area to the second memory area based on the information of the first packet area included in the input serial packet. And a control unit that stores the data information of the second packet area from the first memory area to the third memory area based on the information of the first packet area included in the input serial packet; And a register unit that defines a third memory area.

Focusing on the generation of the output serial packet as well as the processing of the input serial packet, the conversion processing circuit, which is to be specified by the graphic pattern data or the function description data, stores the input serial packet in the first memory area, The control information of the first packet area is stored from the first memory area to the second memory area based on the information of the first packet area included in the input serial packet, and based on the information of the first packet area included in the input serial packet. And stores the data information of the second packet area in the first memory area to the third memory area, and adds the predetermined functional information to the data information to be output held in the third memory area to generate the output serial packet. A control unit that performs a process of storing in the fourth memory area, and a register that defines the first to fourth memory areas. And a data section.

Still another computer-readable recording medium (7) from the viewpoint of contributing to facilitation of designing or manufacturing of a semiconductor integrated circuit employing the conversion processing circuit.
In 1), circuit module data for designing a semiconductor integrated circuit using a computer (70) is stored so that it can be read by the computer. The circuit module data stored in the recording medium is graphic pattern data or function description data for forming a conversion processing circuit capable of parallel conversion of a serial packet including a first packet area and a second packet area on the semiconductor chip. including. The conversion processing circuit stores first register means for designating a first memory area allocated for storing an input serial packet, and control information for a second packet area of the serial packet stored in the first memory area. Second register means for designating a second memory area allocated to the first memory area, and third register means for designating a third memory area for storing the data information of the second packet area of the serial packet stored in the first memory area. , The first to third
A control section for controlling the storage of the information of the input serial packet in a memory area corresponding to the set value of the register means, and the control section of the second packet area based on the information of the first packet area. It distinguishes control information from data information.

Focusing on the generation of the output serial packet as well as the processing of the input serial packet, the conversion processing circuit which is to be specified by the graphic pattern data or the function description data has the first memory area allocated for storing the input serial packet. First register means for designating a second memory area assigned to store control information of a second packet area of the serial packet stored in the first memory area, and second register means for designating Second serial packet stored in one memory area
Third register means for designating a third memory area for storing data information of the packet area and data information to be output by the serial packet, and fourth register means for designating a fourth memory area for storing the output serial packet,
And a control unit for performing control of storing the information of the input serial packet and the output serial packet in a memory area corresponding to the set values of the first to fourth register means, and the control section stores in the first packet area. The control information and the data information of the second packet area are distinguished based on the information.

If a semiconductor integrated circuit is designed using the circuit module data stored and provided in the recording medium, another circuit module such as a coder / decoder configured by using other IP module data. It becomes easy to prevent the occurrence of a discrepancy or inconsistency in address mapping with the fixed usage mode of the memory. Therefore, it is possible to facilitate the design of a semiconductor integrated circuit that employs the conversion processing circuit.

[0039]

FIG. 2 shows an example of a DVD drive to which the semiconductor integrated circuit according to the present invention is applied. DV
The D drive 1 is not particularly limited, but is a DVD-RO.
Disk 3 such as M, DVD-RAM, and CD-ROM
Is a disk drive device that allows access to the personal computer (PC) and is one of the peripheral devices of a personal computer (simply referred to as a PC) 2 that is a host device. For data transmission between the DVD drive 1 and the PC 2, an interface specification using serial packets such as serial ATA is adopted.

The DVD drive 1 is not particularly limited, but a disk controller 4 and a DRAM (Dynamic
Random access memory) 5 and microcomputer 6. Further, a read / write channel 7 including a read / write head, an actuator thereof, a read / write amplifier, etc. is provided. In FIG. 2, a drive system such as a disk motor and its servo control system are not shown. The microcomputer 6 is a CPU
(Central processing unit), its operation program, CPU work area, and appropriate input / output circuits.

The disk controller 4 is not particularly limited, but it is a digital signal processing section (coder / decoder section or codec (codec / decoder section) which performs digital signal processing such as demodulation processing for information read from the disk 3 and modulation processing for information written to the disk. CODEC section) 10, PC
2, a host interface unit 12, a DRAM controller 13, a microcomputer interface unit 14, an audio interface unit 15, etc., which are connected to each other by a serial cable 11, and are formed on one semiconductor substrate (or semiconductor chip) such as single crystal silicon. To be done. Although not particularly limited, the digital signal processing unit 10 is a digital signal processor means (DVD-DSP) for modulation processing.
16, a digital signal processor means (CD-DSP) 17 for demodulation processing, and a ROM decoder 18 for performing error correction and sync signal detection on demodulated information are realized by hardware and software.

The DRAM controller 13 includes the digital signal processing unit 10, the host interface unit 12,
In response to the access request from the microcomputer 6, activation of a memory cycle for the DRAM 5 is controlled. The DRAM 5 is used as a work area and a temporary storage area for sector data and the like in the modulation processing and demodulation processing by the digital signal processing section 10, and as a buffer area and a work area in the interface control of the serial packet by the host interface section 12.

FIG. 1 shows the host interface unit 12
An example is shown. The host interface unit 12 shown in the figure has a serial input FIFO 20 and a serial output FIFO 21 used for input / output of serial packets, although not particularly limited, and a parallel ATA / AT.
It has a parallel ATA / ATAPI input / output unit 22 used for parallel input / output by an API interface. A multiplexer (MUX) 23 switches between serial input / output by the serial input FIFO 20 and serial output FIFO 21 and parallel input / output by the parallel ATA / ATAPI input / output unit 22. A protocol converter 24 and a bus 46 are connected to the multiplexer 23. The operation of the protocol conversion unit 24 is determined according to an instruction from the microcomputer 6 or an operation mode instruction from an external terminal together with the switching operation of the multiplexer 23 for the serial input / output or the parallel input / output.

The protocol conversion unit 24 uses the DRAM 5
Area for protocol conversion 25 and area for codec 26
Protocol conversion control such as parallel conversion of a serial packet and generation of a serial packet using.
For example, in protocol conversion control, serial packet parallel conversion is performed by buffering the input serial packet, analyzing the buffered serial packet command, extracting information from the serial packet, buffering the extracted information, and buffering the serial packet. A serial packet is generated by taking in the output data information that has been taken in, adding functional information to the taken-in data information, and the like. At the time of buffering or information extraction processing at that time, the protocol conversion unit 24 causes the DRAM 5 to
Information storage processing such as so-called UMA for storing data in an arbitrary area in another arbitrary area or memory area mapping processing is performed above.

The protocol conversion unit 24 that performs such processing is roughly divided into a control unit 30 that controls the entire protocol conversion sequence for protocol conversion and a data processing unit 40 that performs data processing during protocol conversion. It

The control unit 30 has a sequence control and protocol conversion area 25 for the protocol conversion control.
Address mapping control. This control unit 30
Has a sequencer 31 for controlling a protocol conversion sequence, an address calculation unit 32 for calculating an access address at the time of memory access, and a mapping register unit 33 for defining mapping of the protocol conversion area 25 in the DRAM 5.

The data processing section 40 includes the control section 30.
Command analysis and information extraction for disassembling / generating serial packets are performed based on the sequence control and address mapping control. This data processing unit 40
For example, an input / output FIFO for data storage during protocol conversion
O41, encoding / decoding unit 42 that performs encoding / decoding processing during protocol conversion, CRC operation unit 43 that realizes error detection of serial input data and addition of error check code to serial output data, serial data / parallel data A bit shift circuit 44 for alignment operation at the time of conversion, and a code detection unit 45 for detecting an operation code held by the decoded serial input data.
Have.

FIG. 3 illustrates a mode of area division for the protocol conversion area 25 and the codec area 26 of the DRAM 5.

The protocol conversion area 25 includes a serial input data storage area (first memory area) 25A, a serial output data storage area (fourth memory area) 25B, and a serial output fixed pattern storage area (fifth memory area) 25.
C, task file register area (second memory area) 2
It is divided into 5D. The areas 25A to 25D are determined according to the register setting values of the mapping register section 33, and here, the areas 25A to 25D are defined by the setting values of the start address registers RegS1 to RegS4 and the end address registers RegS1 to RegE4. It The registers RegS1 and RegE1 are first register means for specifying the serial input data storage area 25A, the registers RegS4 and RegE4 are second register means for specifying the task file register area 25D, and the registers RegS2 and RegE2 are serial output data storage areas. The fourth register means for designating the area 25B and the registers RegS3 and RegE3 constitute fifth register means for designating the fixed pattern storage area for serial output.

Although not particularly limited, the codec area 26 is a codec-specific buffer area or work area in which data information to be demodulated by the codec section 10 or modulated data information is stored in sector units. For convenience of illustration, two areas 26A and 26B capable of storing data information for two sectors can be secured. The read operation when demodulating the data information stored in the codec area 26 and the access control when the modulated data information is write-accessed to the codec area 26 are not particularly limited, but the codec section 1
0 does. On the other hand, the protocol conversion unit 24 performs an access to write the data information cut out from the input serial packet to the codec area 26 and a read access to the data information demodulated by the codec unit 10 and written to the codec area 26. In the example of FIG. 3, the protocol conversion unit 24 includes a register RegS5 (third register means) for defining the codec area 26. Each area 2
The sizes of 6A and 26B are fixed values on the system which are determined by the sector size of the data, and in this example, the register for specifying the size is not shown.

Although not particularly limited, in the codec area 26, an optimized address mapping is defined in accordance with a request such as a digital signal processing algorithm by the codec section 10, and the empty area can be used as the protocol conversion area 25. . In short, originally parallel A
It is intended to use the DRAM 5 used as the work memory or the buffer memory of the codec unit 10 in the TA / ATAPI interface or the empty address area of the mapping address thereof for the protocol conversion by the serial ATA interface. Even in such a case, in the address mapping of the areas 25A to 25D, the mapping address of the codec area 26 determined under the above constraint is set by appropriately setting the value in the mapping register unit 33. You can avoid it and decide freely. Therefore, like so-called UMA (Unified Memory Architecture), DR
It is possible to flexibly use the protocol conversion area 25 as a plurality of different functional areas in the AM 5.

FIG. 4 illustrates another mode of area division for the protocol conversion area 25 and the codec area 26. Two codec areas 26 as shown in FIG.
When A and 26B are separately mapped, the areas 25A to 25A of the protocol conversion area 25 are included in the area between them.
25D may be arranged. Here, in order to define each of the areas 25A to 25D of the protocol conversion area 25, start address registers RegS1 to RegS4 and height registers RegH1 to Re defining the vertical size of the areas are defined.
gH4, virus register R that defines the lateral size of the area
egW1 to RegW4 are used. The register RegS
1, RegH1, RegW1 are first register means for designating the serial input data storage area 25A, the registers RegS4, RegH4, RegW4 are second register means for designating the task file register area 25D,
The registers RegS3, RegH3, RegW3 are fourth register means for designating the serial output data storage area 25C, the registers RegS2, RegH2, Reg.
W2 constitutes fifth register means for designating a fixed pattern storage area for serial output.

Start address registers RegS5A and Reg5B (third part) for defining two separated areas 26A and 26B of the codec area 26, respectively.
Register means). The size of each area 26A, 26B is a fixed value on the system determined by the sector size of the data, and in this example, the register for specifying the area size is not shown.

In the area designating method of FIG. 4, as in the case of FIG. 3, even if the address mapping of the area 26 is determined under the constraint of the digital signal processing algorithm of the codec section 10 or the like, the codec The protocol conversion area 25 can be freely determined by avoiding the mapping address of the area 26.

Next, the operation of parallel conversion processing of serial packets by the protocol conversion unit 24 will be described. Here, it is assumed that the mapping of FIG. 3 is adopted as the address mapping of the protocol conversion area 25.

FIG. 5 illustrates an operation flow of parallel conversion processing of serial packets. The serial packet PACKET input to the host interface 12 is
Data is sequentially written from the beginning in the serial input data storage area 25A via the serial input data FIFO 20, the MUX 23, and the memory controller 13. The write address is generated by the address calculation unit 32. In FIG. 5, the serial input data storage area 25A is illustrated with a 16-bit width, and a state in which two serial packets (serial input packet 1 and serial input packet 2) are stored therein is illustrated. The serial packet PACKET is stored at any time, and when the storage address of the packet information reaches the end address (end address) of the area 25A, the sequencer 31 reloads the start address of the register RegS1 as the access address of the area 25A to the address calculation unit 32. Thus, the serial input data is stored again from the head address of the serial input data storage area 25A.

When the serial packet starts to be stored in the area 25A, the protocol conversion unit 2 is triggered by this.
The sequencer 31 of No. 4 sequentially reads the data from the start address of the area 25A, and inputs / outputs the FI of the data processing unit 40.
Send to FO41. The data internally transferred to the input / output FIFO 41 is the information D of the serial packet which remains encoded.
It is ATA1. The encoding / decoding unit 42 decodes the serial packet information by, for example, 8B10B conversion (S
1). DATA2 means the decoded serial packet information. Next, the decrypted serial packet information DA
TA2 is input to the CRC calculation unit 43, and serial packet transfer error detection processing is performed (S2). DAT
A3 means serial packet information that has undergone CRC error detection / correction processing.

The serial packet information DATA3 is the first
It has a packet area 61, a second packet area 62 and a CRC area 63. The first packet area 61 is a serial packet operation code (code), flag, first
It holds transfer word number data indicating the amount of subsequent data in the packet area. The second packet area 62 holds data information and control information. The data information is, for example, write data to the disc. The control information is access control information such as a command specifying a disk access operation or a file name, and corresponds to setting information for the task file register.

The serial packet information DATA3 is input to the code detecting section 45, the operation code is decoded, the control operation according to the decoding result is instructed to the sequencer 31, and the first packet area 6 as a header.
Other information of 1 is internally transferred to the sequencer 31 and the address calculation unit 32 (S3).

The sequencer 31 analyzes the header structure to execute the sequence determined by the operation code. The contents to be analyzed include grasping the data position and the number of data held in the second packet area such as the transfer data and the task file register set value. By analyzing the header structure, the information in the second packet area is input to the bit shift circuit 44, and data alignment (data shift operation) is performed so that the head of the information comes to the boundary of the byte address (S4). The transfer data information which is the data information of the aligned second packet area and / or the task file register setting value information which is the control information of the second packet area is the input / output FIFO 4
It is temporarily held at 1 (S5). The control information temporarily held in the FIFO 41 is stored in the task file register area 25D of the DRAM 5 (S6), and the data information as the write data to the disk is the codec area 2
6 (S7). The storage address at this time is
The sequencer 31 controls the address calculation unit 32 by referring to the set value of the mapping register unit 33.

By the parallel conversion processing of the serial packet, as shown in FIG. 6, the data information included in the serial packet decoded with respect to the input serial packet is stored in the codec area 26A, and the control information is stored in the task file. It is stored in the register area 25D. The stored state is equivalent to the data format input and stored by the parallel ATA / ATAPI interface. The control information such as parameters and commands stored in the task file register area 25D is AT
DVD-R with A / ATAPI interface
The data information that is used as disk access information or drive control information for the AM drive and that is stored in the codec area 26A is modulated by the codec unit 10 and then DV.
It is used as write data for a D-RAM drive or the like.

Next, a serial packet output process will be described. Here, the mapping of FIG. 3 is adopted as the address mapping of the protocol conversion area 25.

FIG. 7 illustrates a serial packet output processing flow. When a data read command to the PC (host device) 2 is issued, the sequencer 31 issues a demodulation request for the data read from the disc via the microcomputer interface section 14 and the microcomputer 6 via the codec section 10. Codec section 10
Performs demodulation on the data read from the disk, and the demodulated data information is stored in the codec area 26 via the DRAM controller 13. Control information such as parameters that should accompany this data information is stored in the task file register area 25D. The sequencer 31 of the protocol converter 24 uses the address calculator 32 to trigger the codec area 26 and / or the task file register area 25D using the transfer data storage end signal as a trigger. Data information and / or control information is sequentially read from the register area 25D and temporarily stored in the input / output FIFO 41 in the protocol conversion unit 24. The information DATA11 stored in the FIFO 41 is the information that should form the second packet area 62. The data information and / or control information stored in the input / output FIFO 41 is transferred to the bit shift circuit 4
It is input to 4 and is aligned (S11). Furthermore,
The function information for the serial packet read from the fixed pattern storage area for serial output 25C is added to the first packet area 61 as header information (S12). D
The ATA 12 is information of the first packet area 61 and the second packet area 62 in the information of the serial packet before encoding. Next, in order to add a transfer error check code (CRC code) to the header section and the data information section, the information is input to the CRC calculation section 43, and the CRC code is added to the end of the serial packet (S1).
3). The data DATA13 of the serial packet to which the CRC code is added is subjected to 8B10B code processing in the encoding / decoding unit 42 (S14), the encoded information is temporarily stored in the output FIFO 41 as the serial output data DATA14, and the DRAM controller 13 is transferred to the serial output data storage area 25B via S13 (S1
5). The serial packet stored in the serial output data storage area 25B is transferred from the serial output port to the PC 2 via the multiplexer 23 and the serial output data FIFO 21 (S16).

By the conversion processing into the serial packet, as shown in FIG. 8, the data information read from the disk and demodulated and stored in the codec area 26A, the control information stored in the task file register area 25D. Is added with the fixed pattern for serial output from the area 25C and is temporarily held in the serial output data storage area 25B. The information held is equivalent to the data format of the serial packet. In short, the parallel ATA / ATAPI transfer data is converted into a serial packet. Serial output data storage area 25B
The serial packet held in is output to PC2.

When selecting an interface via the parallel ATA / ATAPI input / output unit 22, the interface operation may be performed by omitting the processes related to parallel conversion of serial packets and serial conversion of parallel information in the above control operation. Of course, the detailed description is omitted.

Next, from the viewpoint of facilitating the design of the disk controller 4 which is made into a semiconductor integrated circuit, the design data of the circuit module 12 or the design data of the disk controller 4 itself is used as a so-called IP module. Describe what to offer.

The circuit module data provided as the IP module is at least the disk controller 1
2 includes graphic pattern data for forming 2 on the semiconductor chip or function description data by HDL (hardware description language) or RTL (register transfer logic). The figure pattern data is mask pattern data or electron beam drawing data. The function description data is so-called program data, and a circuit or the like can be specified by symbol display by reading it into a predetermined design tool.

Further, the scale of the IP module may be at the LSI level like the disk controller 4 illustrated in FIG.

The data of the IP modules is data for designing an integrated circuit to be formed on a semiconductor chip by using a computer 70 such as a design tool as illustrated in FIG. It is provided by being stored in a recording medium 71 such as a CD-ROM, a DVD-ROM, or a magnetic tape so that it can be read by the device 70. For example, the data of the hard IP module corresponding to the host interface unit 12 of FIG. 1 is the mask pattern data D1 for configuring the host interface unit 12, the function description data D2 of the host interface unit 12,
Also, when the LSI is designed by applying the data of the IP module of the host interface unit 12, it has verification data D3 for enabling a simulation in consideration of the relationship with other modules.

If the semiconductor integrated circuit is designed by using the circuit module data of the host interface unit 12 stored and provided in the recording medium 71, the codec unit 10 configured by using other IP module data.
It is easy to prevent the occurrence of a discrepancy or inconsistency in address mapping with the fixed usage pattern of the memory by another circuit module such as. More specifically, the IP module data of the codec section 10 basically realizes its own function, and in many cases, the usage pattern of the RAM as a work area is optimized and determined. In such a case, I
If the usage pattern for the work RAM of the P module is fixedly determined by its own logic based on its unique function, it is inevitable that RAM accesses to the same address area will collide with each other. At this time, the IP module data of the host interface module 12 is guaranteed to have a function of flexibly determining the address mapping of the protocol conversion area 25. Therefore, it is possible to facilitate the design of a semiconductor integrated circuit that employs the host interface module 12.

According to the data structure conversion between the serial packet and the parallel ATA / ATAPI described above,
A high-speed data structure that can flexibly store information having a different data structure on the memory 5 managed by the so-called UMA method and is not restricted by a memory access boundary by the protocol conversion unit 24 having a data structure conversion function. Conversion or protocol conversion can be realized.

Since the data structure conversion between serial and parallel is realized by processing the data in the RAM 5 by the data processing unit 40 under the control of the control unit 30,
By changing the processing routine, adding a cryptographic processing circuit, etc.,
Parallel A with other serial interface protocols
It is possible to implement a data structure or protocol conversion function with the TA / ATAPI interface.

Since it has a function of shaping the data from both the so-called UMA type protocol conversion memory area and the decoding memory area into the protocol of the external serial packet interface, it is a memory area with another module configured by the IP module. It becomes easier to achieve consistency regarding the use of.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the data information and control information contained in the serial packet may be transferred in separate serial packets. The input / output switching function by parallel ATA / ATAPI need not be adopted.

The semiconductor integrated circuit in which the host interface section 12 is on-chip is not limited to the configuration of FIG. 1, and the DRAM 5 may be on-chip, or the microcomputer 6 or the CPU may be on-chip.

The mapping on the memory such as the serial input data storage area and the task file register area used for parallel conversion of the serial packet is not limited to the above example and can be changed as appropriate. The memory for such an application is not limited to DRAM and may be SRAM. In the case of DRAM, it is naturally a good idea to adopt a clock synchronous operation type synchronous DRAM.

The IP module data may be software IP module data. That is, except for the mask pattern data D1 of FIG. 9, the function description data D
2 and design data D3.

The present invention is applicable not only to a DVD drive but also to a CD
The present invention can be widely applied to ROM, CD-RW (compact disc-rewritable), MO (porcelain / optical) disc drives, and the like. Furthermore, the present invention can be widely applied to serial interfaces other than disk drives.

[0080]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of different storage areas (first packet area, control information area of second packet area, data information area of second packet area) of different function information forming a serial packet are stored in the memory. It is possible to flexibly map the functional area and distribute the necessary information to the parallel conversion of the serial packet, that is, the interface protocol of the serial packet to the interface protocol of the parallel packet.

As a result, when the CPU performs software processing for recognizing and extracting data, commands, etc. from information transferred as a serial packet, assuming a serial packet with a high transfer rate, Since the serial packet is temporarily buffered in the first memory area and the size of the first memory area can be flexibly determined, it is difficult to increase the load on the CPU.
The parallel conversion of serial packets can be performed without affecting the processing capability of the entire system or limiting the speedup of serial transfer.

From the above, data, commands, etc., having different data structures or bit lengths from information transferred as a serial packet can be temporarily stored in the memory in divided areas for convenient post-processing. it can.

As described above, when the work memory used by the digital signal processing means for performing the modulation processing for recording information and the demodulation processing for reproducing recorded information is also used for parallel conversion of serial packets, the digital signal processing means Even if the usage pattern of such a work memory is optimized or specific to the modulation / demodulation processing method by the digital signal processing means, such a work memory is also used for other purposes such as parallel conversion of serial packets. It is possible to perform address mapping with a high degree of freedom.

As described above, a discrepancy or inconsistency in the address mapping with the fixed use form of the memory by the other circuit module such as the digital signal processing means configured by using the IP module data is caused. It is easy to prevent. Therefore, if the semiconductor integrated circuit is designed using the circuit module data stored and provided in the recording medium, the design of the semiconductor integrated circuit using the conversion processing circuit can be facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a host interface unit included in a semiconductor integrated circuit according to the present invention.

FIG. 2 is a DVD to which the semiconductor integrated circuit according to the present invention is applied.
It is a block diagram showing an example of a drive.

FIG. 3 is an explanatory diagram showing an example of area division mapping of a protocol conversion area and a codec area of a DRAM.

FIG. 4 is an explanatory diagram showing another example of area division mapping of a protocol conversion area and a codec area.

FIG. 5 is an explanatory diagram illustrating an operation flow of parallel conversion processing of a serial packet.

FIG. 6 is an explanatory diagram showing a state in which data information obtained by parallel conversion processing of a serial packet is stored in a codec area and control information is stored in a task file register area.

FIG. 7 is an explanatory diagram illustrating an output processing flow of a serial packet.

FIG. 8 is a serial output data storage area in which a fixed pattern for serial output is added to the data information stored in the codec area and the control data stored in the task file register area obtained by the conversion processing into a serial packet. It is explanatory drawing which shows the state hold | maintained temporarily.

FIG. 9 is an explanatory diagram showing an example of IP module data together with a computer such as an integrated circuit design tool.

[Explanation of symbols]

1 DVD Drive 2 Host Device 4 Disk Controller 5 DRAM 6 Microcomputer 10 Digital Signal Processor 12 Host Interface 13 DRAM Controller 14 Microcomputer Interface 24 Protocol Converter 25 Protocol Conversion Area 25A Serial Input Data Storage Area 25B Serial Output Data Storage Area 25C Serial output fixed pattern storage area 25D Task file register area 26 Codec areas 26A, 26B Codec area 30 Control section 31 Sequencer 32 Address operation section 33 Mapping register section RegS1 to RegS4 Start address register RegE1 to protocol conversion area RegE4 protocol conversion area end address register RegH1 to RegH4 protocol conversion Area height register RegW1 to RegW4 Protocol conversion area virus register RegS5 Codec area start address register RegS5A, RegS5B Codec area start address register 40 Data processing unit 41 Input / output FIFO 42 Encoding / decoding unit 43 CRC calculation Section 44 Bit shift circuit 45 Code detection section 46 Bus

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04L 12/56 H04L 12/56 Z (72) Inventor Keisuke Matsuda 5-22 No. 22, Kamimizumoto-cho, Kodaira-shi, Tokyo No. 1 within Hitachi Super L.S.I. Systems Co., Ltd. (72) Inventor Kazuyuki Takada 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Within Hitachi Super L.S.I. Systems Co., Ltd. (72) Inventor Akihiro Utsu 5-22-1, Kamisuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Inc. (reference) 5B060 AC19 CA17 5B061 AA00 FF04 GG02 5B065 CA18 CC08 CE04 CE15 5B077 NN02 NN07 5K030 GA01 HA08 KA01 KA02

Claims (17)

[Claims] 1. A conversion processing circuit capable of performing parallel conversion of a serial packet including a first packet area and a second packet area using a memory, wherein the conversion processing circuit inputs an input serial packet to the first memory area. First stored in the input serial packet
The control information of the second packet area is stored from the first memory area to the second memory area based on the information of the packet area, and the data information of the second packet area is stored based on the information of the first packet area included in the input serial packet. And a register unit that defines first to third memory areas on the memory, and a control unit that stores the data from the first memory area to the third memory area. Integrated semiconductor circuit. 2. A conversion processing circuit capable of parallel conversion of a serial packet including a first packet area and a second packet area and generation of a serial packet using a memory, wherein the conversion processing circuit is a first memory. The input serial packet is stored in the area, and the first serial packet included in the input serial packet
The control information of the second packet area is stored from the first memory area to the second memory area based on the information of the packet area, and the data information of the second packet area is stored based on the information of the first packet area included in the input serial packet. Is stored from the first memory area to the third memory area, and the output serial packet generated by adding predetermined function information to the data information to be output held in the third memory area is stored in the fourth memory area. 2. A semiconductor integrated circuit, comprising: a control unit for performing the above; and a register unit that defines first to fourth memory areas on the memory. 3. The semiconductor integrated circuit according to claim 2, wherein the control section selects, from the fifth memory area, the function information to be added to the data information to be output held in the third memory area. 4. The semiconductor integrated circuit according to claim 1, wherein the first packet area includes an operation code of a serial packet and information indicating a subsequent information amount in the first packet area. 5. The semiconductor integrated circuit according to claim 4, wherein the register unit has a CPU interface to which a CPU capable of initializing information for defining a memory area can be connected. 6. The semiconductor integrated circuit according to claim 4, further comprising a CPU that initializes information for defining a memory area in the register section. 7. The semiconductor integrated circuit according to claim 4, comprising the memory. 8. A conversion processing circuit capable of parallel conversion of a serial packet including a first packet area and a second packet area using a memory, wherein the conversion processing circuit is assigned to store an input serial packet. First register means for designating a first memory area and second register means for designating a second memory area assigned to store control information of a second packet area of a serial packet stored in the first memory area. And a second serial packet stored in the first memory area.
Third register means for designating a third memory area for storing the data information of the packet area, and control for storing the information of the input serial packet in the memory area according to the set values of the first to third register means are performed. Has a control unit,
The semiconductor integrated circuit, wherein the control unit distinguishes control information and data information of the second packet area based on the information of the first packet area. 9. A semiconductor integrated circuit having a conversion processing circuit capable of parallel conversion of a serial packet including a first packet area and a second packet area and generation of a serial packet using a memory, wherein the conversion processing circuit. Is a first register means for designating a first memory area allocated for storing an input serial packet, and a first register means allocated for storing control information of a second packet area of the serial packet stored in said first memory area. Second register means for designating two memory areas and a second serial packet stored in the first memory area
Third register means for designating a third memory area for storing data information of the packet area and data information to be output by the serial packet, and fourth register means for designating a fourth memory area for storing the output serial packet,
A control section for controlling the storage of the input serial packet information and the output serial packet in a memory area designated by the first to fourth register means, and the control section controls the information of the first packet area. The semiconductor integrated circuit is characterized in that the control information and the data information of the second packet area are distinguished based on the above. 10. The first packet area includes an operation code of a serial packet and information indicating a subsequent information amount in the first packet area.
Alternatively, the semiconductor integrated circuit according to item 9. 11. The serial packet is a serial AT
10. The semiconductor integrated circuit according to claim 8, which complies with one of the API standard, the USB standard, and the IEEE 1394 standard. 12. A digital signal processing means used for recording / reproducing information to / from a recording disk, wherein the digital signal processing means extends from the first memory area to the third area.
10. The data information of the input serial packet stored in the memory area is modulated, and the data information to be stored in the third memory area as information to be output by the serial packet is demodulated. The semiconductor integrated circuit described. 13. A recording medium in which circuit module data for designing a semiconductor integrated circuit to be formed on a semiconductor chip by using a computer is stored so as to be readable by the computer and stored in the recording medium. The circuit module data includes a first packet area and a first packet area.
The conversion processing circuit stores graphic pattern data or function description data for forming a conversion processing circuit capable of parallel conversion of a serial packet including a packet area in the semiconductor chip, and the conversion processing circuit stores an input serial packet in a first memory area. The first contained in the input serial packet
The control information of the second packet area is stored from the first memory area to the second memory area based on the information of the packet area, and the data information of the second packet area is stored based on the information of the first packet area included in the input serial packet. A computer-readable recording medium, comprising: a control unit that performs a process of storing the data from the first memory area to the third memory area; and a register unit that defines the first to third memory areas. . 14. A recording medium in which circuit module data for designing a semiconductor integrated circuit to be formed on a semiconductor chip by using a computer is stored so as to be readable by the computer and stored in the recording medium. The circuit module data includes the first packet area and the second packet area.
The semiconductor chip includes graphic pattern data or function description data for forming a conversion processing circuit capable of parallel conversion of serial packets and generation of serial packets including a packet area in the first memory area. The first serial packet that stores the input serial packet and is included in the input serial packet
The control information of the first packet area is stored in the second memory area from the first memory area based on the information of the packet area, and the data information of the second packet area is stored based on the information of the first packet area included in the input serial packet. Is stored in the third memory area from the first memory area, and the output serial packet generated by adding predetermined function information to the data information to be output held in the third memory area is stored in the fourth memory area. A computer-readable recording medium comprising: a control unit for performing the above; and a register unit that defines the first to fourth memory areas. 15. A recording medium in which circuit module data for designing a semiconductor integrated circuit to be formed on a semiconductor chip by using a computer is stored so as to be readable by the computer and stored in the recording medium. The circuit module data includes the first packet area and the second packet area.
A first conversion processing circuit that includes graphic pattern data or function description data for forming a conversion processing circuit capable of parallel conversion of a serial packet including a packet area on the semiconductor chip, wherein the conversion processing circuit is assigned to store an input serial packet; First register means for specifying a memory area, and second register means for specifying a second memory area allocated to store control information of a second packet area of the serial packet stored in the first memory area, The second of the serial packets stored in the first memory area
Third register means for designating a third memory area for storing the data information of the packet area, and control for storing the information of the input serial packet in the memory area according to the set values of the first to third register means are performed. Has a control unit,
The computer-readable recording medium, wherein the control unit distinguishes the control information and the data information of the second packet area based on the information of the first packet area. 16. A recording medium in which circuit module data for designing a semiconductor integrated circuit to be formed on a semiconductor chip by using a computer is stored so as to be readable by the computer and stored in the recording medium. The circuit module data includes the first packet area and the second packet area.
The conversion processing circuit includes graphic pattern data or function description data for forming a conversion processing circuit capable of performing parallel conversion of a serial packet including a packet area and generation of a serial packet on the semiconductor chip, and the conversion processing circuit stores an input serial packet. Register means for designating a first memory area allocated to the first memory area, and second memory area for designating control information of the second packet area of the serial packet stored in the first memory area. A second register means and a second serial packet stored in the first memory area.
Third register means for designating a third memory area for storing data information of the packet area and data information to be output by the serial packet, and fourth register means for designating a fourth memory area for storing the output serial packet,
And a control unit for performing control of storing the information of the input serial packet and the output serial packet in a memory area corresponding to the set values of the first to fourth register means, and the control section stores in the first packet area. A computer-readable recording medium characterized by distinguishing control information and data information of the second packet area based on information. 17. The serial packet is a serial AT
14. Compliant with one of the API standard, the USB standard, and the IEEE 1394 standard.
17. The computer-readable recording medium according to any one of 1 to 16.