WO2002101829A8 - Method for forming a wafer level chip scale package, and package formed thereby - Google Patents

Method for forming a wafer level chip scale package, and package formed thereby

Info

Publication number
WO2002101829A8
WO2002101829A8 PCT/SG2002/000118 SG0200118W WO02101829A8 WO 2002101829 A8 WO2002101829 A8 WO 2002101829A8 SG 0200118 W SG0200118 W SG 0200118W WO 02101829 A8 WO02101829 A8 WO 02101829A8
Authority
WO
WIPO (PCT)
Prior art keywords
copper pillars
package
coating material
solder balls
forming
Prior art date
Application number
PCT/SG2002/000118
Other languages
French (fr)
Other versions
WO2002101829A1 (en
Inventor
Romeo Emmanuel P Alvarez
John Briar
Hwee Seng Jimmy Chew
Original Assignee
Advanpack Solutions Pte Ltd
Romeo Emmanuel P Alvarez
John Briar
Hwee Seng Jimmy Chew
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanpack Solutions Pte Ltd, Romeo Emmanuel P Alvarez, John Briar, Hwee Seng Jimmy Chew filed Critical Advanpack Solutions Pte Ltd
Priority to AU2002309459A priority Critical patent/AU2002309459A1/en
Publication of WO2002101829A1 publication Critical patent/WO2002101829A1/en
Publication of WO2002101829A8 publication Critical patent/WO2002101829A8/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
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    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
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    • H01L2224/13144—Gold [Au] as principal constituent
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A layer of gold (405) is disposed on upper surfaces (225) of copper pillars (210) on a bumped wafer (205). Coating material (410) is then applied to a level which is less than the height of the copper pillars (210), and etchant is disposed to remove coating material on the layer of gold (405) and to remove coating material (410) adhering to side surfaces of the copper pillars (210). Solder balls (405) are then disposed on the ends of the copper pillars (210), with the copper pillars (210) protruding into the solder balls (405). In an alternative embodiment, solder balls are first attached to the free ends of the copper pillars and coating material applied to encapsulate the solder balls and the copper pillars on the semiconductor wafer. An etchant is then used to remove a portion of the coating material, substantially exposing the solder balls.
PCT/SG2002/000118 2001-06-13 2002-06-12 Method for forming a wafer level chip scale package, and package formed thereby WO2002101829A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002309459A AU2002309459A1 (en) 2001-06-13 2002-06-12 Method for forming a wafer level chip scale package, and package formed thereby

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
SG200103485-9 2001-06-13
SG200103485 2001-06-13
SG200107810-4 2001-12-10
SG200107810 2001-12-10

Publications (2)

Publication Number Publication Date
WO2002101829A1 WO2002101829A1 (en) 2002-12-19
WO2002101829A8 true WO2002101829A8 (en) 2004-04-08

Family

ID=26665229

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2002/000118 WO2002101829A1 (en) 2001-06-13 2002-06-12 Method for forming a wafer level chip scale package, and package formed thereby

Country Status (3)

Country Link
CN (1) CN1315187C (en)
AU (1) AU2002309459A1 (en)
WO (1) WO2002101829A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102489810B (en) * 2011-12-23 2013-07-31 哈尔滨工业大学 Method for self-assembling micro-electromechanical system (MEMS) based on solder ball laser remelting process
CN104425291A (en) * 2013-08-30 2015-03-18 吴勇军 Micron-order semiconductor device packaging method and formed packaging structure
CN109411424B (en) * 2016-11-27 2020-11-27 苏州鱼得水电气科技有限公司 Wafer package with heat radiation structure
CN113200514B (en) * 2021-04-28 2023-07-14 华南农业大学 Silicon-based eutectic bonding structure, micromechanical device, packaging structure and preparation method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2462595A (en) * 1994-05-05 1995-11-29 Siliconix Incorporated Surface mount and flip chip technology
US5904496A (en) * 1997-01-24 1999-05-18 Chipscale, Inc. Wafer fabrication of inside-wrapped contacts for electronic devices
US5818697A (en) * 1997-03-21 1998-10-06 International Business Machines Corporation Flexible thin film ball grid array containing solder mask
US6051489A (en) * 1997-05-13 2000-04-18 Chipscale, Inc. Electronic component package with posts on the active side of the substrate
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme

Also Published As

Publication number Publication date
WO2002101829A1 (en) 2002-12-19
CN1315187C (en) 2007-05-09
CN1486509A (en) 2004-03-31
AU2002309459A1 (en) 2002-12-23

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