AU2002309459A1 - Method for forming a wafer level chip scale package, and package formed thereby - Google Patents

Method for forming a wafer level chip scale package, and package formed thereby

Info

Publication number
AU2002309459A1
AU2002309459A1 AU2002309459A AU2002309459A AU2002309459A1 AU 2002309459 A1 AU2002309459 A1 AU 2002309459A1 AU 2002309459 A AU2002309459 A AU 2002309459A AU 2002309459 A AU2002309459 A AU 2002309459A AU 2002309459 A1 AU2002309459 A1 AU 2002309459A1
Authority
AU
Australia
Prior art keywords
package
forming
wafer level
chip scale
level chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002309459A
Inventor
Romeo Emmanuel P. Alvarez
John Briar
Hwee Seng Jimmy Chew
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanpack Solutions Pte Ltd
Original Assignee
Advanpack Solutions Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanpack Solutions Pte Ltd filed Critical Advanpack Solutions Pte Ltd
Publication of AU2002309459A1 publication Critical patent/AU2002309459A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
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    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
AU2002309459A 2001-06-13 2002-06-12 Method for forming a wafer level chip scale package, and package formed thereby Abandoned AU2002309459A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
SG200103485 2001-06-13
SG200103485-9 2001-06-13
SG200107810-4 2001-12-10
SG200107810 2001-12-10
PCT/SG2002/000118 WO2002101829A1 (en) 2001-06-13 2002-06-12 Method for forming a wafer level chip scale package, and package formed thereby

Publications (1)

Publication Number Publication Date
AU2002309459A1 true AU2002309459A1 (en) 2002-12-23

Family

ID=26665229

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002309459A Abandoned AU2002309459A1 (en) 2001-06-13 2002-06-12 Method for forming a wafer level chip scale package, and package formed thereby

Country Status (3)

Country Link
CN (1) CN1315187C (en)
AU (1) AU2002309459A1 (en)
WO (1) WO2002101829A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102489810B (en) * 2011-12-23 2013-07-31 哈尔滨工业大学 Method for self-assembling micro-electromechanical system (MEMS) based on solder ball laser remelting process
CN104425291A (en) * 2013-08-30 2015-03-18 吴勇军 Micron-order semiconductor device packaging method and formed packaging structure
CN109411422A (en) * 2016-11-27 2019-03-01 卢卫征 Wafer level packaging with radiator structure
CN113200514B (en) * 2021-04-28 2023-07-14 华南农业大学 Silicon-based eutectic bonding structure, micromechanical device, packaging structure and preparation method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0707741A4 (en) * 1994-05-05 1997-07-02 Siliconix Inc Surface mount and flip chip technology
US5904496A (en) * 1997-01-24 1999-05-18 Chipscale, Inc. Wafer fabrication of inside-wrapped contacts for electronic devices
US5818697A (en) * 1997-03-21 1998-10-06 International Business Machines Corporation Flexible thin film ball grid array containing solder mask
US6051489A (en) * 1997-05-13 2000-04-18 Chipscale, Inc. Electronic component package with posts on the active side of the substrate
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme

Also Published As

Publication number Publication date
CN1486509A (en) 2004-03-31
WO2002101829A8 (en) 2004-04-08
CN1315187C (en) 2007-05-09
WO2002101829A1 (en) 2002-12-19

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Legal Events

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MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase