WO2002101564A1 - Systeme multiprocesseur, procede permettant de le concevoir et systeme de multiprocesseur decrit en langage de description de materiel - Google Patents

Systeme multiprocesseur, procede permettant de le concevoir et systeme de multiprocesseur decrit en langage de description de materiel Download PDF

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Publication number
WO2002101564A1
WO2002101564A1 PCT/JP2001/004965 JP0104965W WO02101564A1 WO 2002101564 A1 WO2002101564 A1 WO 2002101564A1 JP 0104965 W JP0104965 W JP 0104965W WO 02101564 A1 WO02101564 A1 WO 02101564A1
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WO
WIPO (PCT)
Prior art keywords
bus
processors
engine
internal
data
Prior art date
Application number
PCT/JP2001/004965
Other languages
English (en)
Japanese (ja)
Inventor
Yukoh Matsumoto
Original Assignee
Tops Systems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tops Systems Corporation filed Critical Tops Systems Corporation
Priority to PCT/JP2001/004965 priority Critical patent/WO2002101564A1/fr
Publication of WO2002101564A1 publication Critical patent/WO2002101564A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un procédé permettant de concevoir, dans un langage de description de matériel, un système de multiprocesseurs comprenant un bus commun, une pluralité de processeurs connectés au bus commun et un mécanisme d'arbitrage par permutation circulaire de demandes d'utilisation du bus, émises par des processeurs, afin d'utiliser le bus commun. Un texte source écrit en langage de description de matériel comprend une description pour créer un nombre donné d'instances de processeurs inférieur au nombre maximal de processeurs et équiper le système de multiprocesseurs, de processeurs.
PCT/JP2001/004965 2001-06-12 2001-06-12 Systeme multiprocesseur, procede permettant de le concevoir et systeme de multiprocesseur decrit en langage de description de materiel WO2002101564A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/004965 WO2002101564A1 (fr) 2001-06-12 2001-06-12 Systeme multiprocesseur, procede permettant de le concevoir et systeme de multiprocesseur decrit en langage de description de materiel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/004965 WO2002101564A1 (fr) 2001-06-12 2001-06-12 Systeme multiprocesseur, procede permettant de le concevoir et systeme de multiprocesseur decrit en langage de description de materiel

Publications (1)

Publication Number Publication Date
WO2002101564A1 true WO2002101564A1 (fr) 2002-12-19

Family

ID=11737420

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/004965 WO2002101564A1 (fr) 2001-06-12 2001-06-12 Systeme multiprocesseur, procede permettant de le concevoir et systeme de multiprocesseur decrit en langage de description de materiel

Country Status (1)

Country Link
WO (1) WO2002101564A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182172A (ja) * 1993-11-05 1995-07-21 Microsoft Corp コンポーネント接続管理方法およびシステム
JPH09231253A (ja) * 1996-02-26 1997-09-05 Fujitsu Ltd 論理装置の検証データ生成方法
JP2000082019A (ja) * 1998-09-07 2000-03-21 Hitachi Ltd データ転送制御装置
JP2001160080A (ja) * 1999-12-02 2001-06-12 Nec Corp オブジェクト指向言語によるシステムのシミュレーション方法、装置及びそのプログラムを記録した記録媒体

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182172A (ja) * 1993-11-05 1995-07-21 Microsoft Corp コンポーネント接続管理方法およびシステム
JPH09231253A (ja) * 1996-02-26 1997-09-05 Fujitsu Ltd 論理装置の検証データ生成方法
JP2000082019A (ja) * 1998-09-07 2000-03-21 Hitachi Ltd データ転送制御装置
JP2001160080A (ja) * 1999-12-02 2001-06-12 Nec Corp オブジェクト指向言語によるシステムのシミュレーション方法、装置及びそのプログラムを記録した記録媒体

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