WO2002099650A3 - Verfahren zur verwaltung eines speichers einer chipkarte - Google Patents

Verfahren zur verwaltung eines speichers einer chipkarte Download PDF

Info

Publication number
WO2002099650A3
WO2002099650A3 PCT/EP2002/006143 EP0206143W WO02099650A3 WO 2002099650 A3 WO2002099650 A3 WO 2002099650A3 EP 0206143 W EP0206143 W EP 0206143W WO 02099650 A3 WO02099650 A3 WO 02099650A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
managing
chip card
card memory
virtual
Prior art date
Application number
PCT/EP2002/006143
Other languages
English (en)
French (fr)
Other versions
WO2002099650A2 (de
Inventor
Robin Boch
Stefan Erdmenger
Stephan Ondrusch
Original Assignee
Infineon Technologies Ag
Robin Boch
Stefan Erdmenger
Stephan Ondrusch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Robin Boch, Stefan Erdmenger, Stephan Ondrusch filed Critical Infineon Technologies Ag
Priority to AU2002316963A priority Critical patent/AU2002316963A1/en
Publication of WO2002099650A2 publication Critical patent/WO2002099650A2/de
Publication of WO2002099650A3 publication Critical patent/WO2002099650A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

Bei einem Verfahren zur Verwaltung eines Speichers (100) einer Chipkarte, wobei der Speicher (100) eine Mehrzahl von Speicherplätzen aufweist, wird zunächst ein virtueller Adressbereich für eine Adressierung des Speichers (100) festgelegt. Anschließend werden virtuelle Adresse (VA) des virtuellen Adressbereichs zu den physikalischen Adressen (PA) der Speicherplätze (102) zugeordnet, und ein Zugriff auf den Speicher (100) wird unter Verwendung der virtuellen Adresse (VA) des virtuellen Adressbereichs gesteuert.
PCT/EP2002/006143 2001-06-05 2002-06-04 Verfahren zur verwaltung eines speichers einer chipkarte WO2002099650A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002316963A AU2002316963A1 (en) 2001-06-05 2002-06-04 Method for managing a chip card memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10127179A DE10127179A1 (de) 2001-06-05 2001-06-05 Verfahren zur Verwaltung eines Speichers einer Chipkarte
DE10127179.4 2001-06-05

Publications (2)

Publication Number Publication Date
WO2002099650A2 WO2002099650A2 (de) 2002-12-12
WO2002099650A3 true WO2002099650A3 (de) 2003-11-27

Family

ID=7687196

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/006143 WO2002099650A2 (de) 2001-06-05 2002-06-04 Verfahren zur verwaltung eines speichers einer chipkarte

Country Status (3)

Country Link
AU (1) AU2002316963A1 (de)
DE (1) DE10127179A1 (de)
WO (1) WO2002099650A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10301969A1 (de) * 2003-01-20 2004-08-05 Giesecke & Devrient Gmbh Speicherdefragmentierung, insbesondere bei einem tragbaren Datenträger
US7243206B2 (en) 2003-04-14 2007-07-10 Arm Limited Method and apparatus for using a RAM memory block to remap ROM access requests
DE10347828A1 (de) * 2003-10-10 2005-05-25 Giesecke & Devrient Gmbh Zugreifen auf Datenelemente in einem tragbaren Datenträger

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19723676A1 (de) * 1997-06-05 1998-08-27 Siemens Ag Verfahren zum Nachladen von Programmen auf eine Chip-Karte
US5940850A (en) * 1996-10-31 1999-08-17 International Business Machines Corporation System and method for selectively enabling load-on-write of dynamic ROM data to RAM
WO2001029672A1 (en) * 1999-10-19 2001-04-26 Advanced Technology Materials, Inc. Partitioned memory device having characteristics of different memory technologies

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4429905C1 (de) * 1994-08-23 1995-09-07 Siemens Ag Verfahren zum Betrieb eines virtuellen Speichers
US6694402B1 (en) * 1998-09-04 2004-02-17 Hyperstone Ag Access control for a memory having a limited erasure frequency
JP3741895B2 (ja) * 1999-03-15 2006-02-01 岩手東芝エレクトロニクス株式会社 半導体記憶素子の不良パターン解析方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5940850A (en) * 1996-10-31 1999-08-17 International Business Machines Corporation System and method for selectively enabling load-on-write of dynamic ROM data to RAM
DE19723676A1 (de) * 1997-06-05 1998-08-27 Siemens Ag Verfahren zum Nachladen von Programmen auf eine Chip-Karte
WO2001029672A1 (en) * 1999-10-19 2001-04-26 Advanced Technology Materials, Inc. Partitioned memory device having characteristics of different memory technologies

Also Published As

Publication number Publication date
AU2002316963A1 (en) 2002-12-16
WO2002099650A2 (de) 2002-12-12
DE10127179A1 (de) 2002-12-19

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