WO2002093336A2 - Processor with protected test and debug mode - Google Patents

Processor with protected test and debug mode Download PDF

Info

Publication number
WO2002093336A2
WO2002093336A2 PCT/US2002/011935 US0211935W WO02093336A2 WO 2002093336 A2 WO2002093336 A2 WO 2002093336A2 US 0211935 W US0211935 W US 0211935W WO 02093336 A2 WO02093336 A2 WO 02093336A2
Authority
WO
WIPO (PCT)
Prior art keywords
hdt
microcode
control logic
enable
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2002/011935
Other languages
English (en)
French (fr)
Other versions
WO2002093336A3 (en
Inventor
Geoffrey S. Strongin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/852,372 external-priority patent/US7065654B1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to DE60206924T priority Critical patent/DE60206924T2/de
Priority to AU2002250591A priority patent/AU2002250591A1/en
Priority to EP02719514A priority patent/EP1410143B1/en
Priority to JP2002589946A priority patent/JP2005501313A/ja
Priority to KR10-2003-7014546A priority patent/KR20030094396A/ko
Publication of WO2002093336A2 publication Critical patent/WO2002093336A2/en
Anticipated expiration legal-status Critical
Publication of WO2002093336A3 publication Critical patent/WO2002093336A3/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram

Definitions

  • HDT control logic 410B includes HDT control logic 410B, HDT reset logic 420B, and two registers, including the HDT enable register 415 and an HDT enable lock register 435.
  • the HDT control logic 410B is coupled to receive a plurality of input signals through the plurality of HDT pins 405.
  • the HDT control logic 410B is further coupled to the HDT enable register 415 and the HDT enable lock register 435.
  • the HDT reset logic 420B is coupled to receive the RESET signal over the line 425 and a signal, such as over a line 440, through a pull-up (or pull-down) resistor 445.
  • HDT enable status bits For example, the HDT mode may be disabled, but inside SMM, a predetermined input to the HDT control logic 410 may signal the HDT control logic 410 to change the HDT mode status to enabled.
  • references to ROM are to be construed as also applying to flash memory and other substantially non-volatile memory types.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Stored Programmes (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)
PCT/US2002/011935 2001-05-10 2002-04-17 Processor with protected test and debug mode Ceased WO2002093336A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE60206924T DE60206924T2 (de) 2001-05-10 2002-04-17 Prozessor mit geschütztem prüfungs- und fehlerbeseitigungsmodus
AU2002250591A AU2002250591A1 (en) 2001-05-10 2002-04-17 Processor with protected test and debug mode
EP02719514A EP1410143B1 (en) 2001-05-10 2002-04-17 Processor with protected test and debug mode
JP2002589946A JP2005501313A (ja) 2001-05-10 2002-04-17 パーソナルコンピュータシステムにおいて裏口アクセス機構を閉鎖するための機構
KR10-2003-7014546A KR20030094396A (ko) 2001-05-10 2002-04-17 개인용 컴퓨터 시스템들에서 백도어 액세스 메커니즘들을막기 위한 메커니즘

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US85294201A 2001-05-10 2001-05-10
US09/852,372 US7065654B1 (en) 2001-05-10 2001-05-10 Secure execution box
US09/852,372 2001-05-10
US09/852,942 2001-05-10
US09/853,226 US20030028781A1 (en) 2001-05-10 2001-05-11 Mechanism for closing back door access mechanisms in personal computer systems
US09/853,226 2001-05-11

Publications (2)

Publication Number Publication Date
WO2002093336A2 true WO2002093336A2 (en) 2002-11-21
WO2002093336A3 WO2002093336A3 (en) 2004-02-12

Family

ID=27420360

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/011935 Ceased WO2002093336A2 (en) 2001-05-10 2002-04-17 Processor with protected test and debug mode

Country Status (9)

Country Link
US (1) US20030028781A1 (enExample)
EP (1) EP1410143B1 (enExample)
JP (1) JP2005501313A (enExample)
KR (1) KR20030094396A (enExample)
CN (1) CN1520537A (enExample)
AU (1) AU2002250591A1 (enExample)
DE (1) DE60206924T2 (enExample)
TW (1) TWI228889B (enExample)
WO (1) WO2002093336A2 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030097587A1 (en) * 2001-11-01 2003-05-22 Gulick Dale E. Hardware interlock mechanism using a watchdog timer
US20040034872A1 (en) * 2002-08-16 2004-02-19 Peter Huyge Method for triggering an event in an electronic device, and corresponding device
US7334123B2 (en) * 2003-05-02 2008-02-19 Advanced Micro Devices, Inc. Computer system including a bus bridge for connection to a security services processor
JP4692826B2 (ja) * 2003-07-28 2011-06-01 ソニー株式会社 情報処理装置および方法、記録媒体、並びにプログラム
US7805614B2 (en) * 2004-04-26 2010-09-28 Northrop Grumman Corporation Secure local or remote biometric(s) identity and privilege (BIOTOKEN)
US7552341B2 (en) * 2004-09-01 2009-06-23 Microsoft Corporation Licensing the use of software on a particular CPU
JP4309361B2 (ja) * 2005-03-14 2009-08-05 パナソニック株式会社 電子機器制御システム及び制御信号送信装置
JP4207050B2 (ja) * 2005-06-27 2009-01-14 コニカミノルタビジネステクノロジーズ株式会社 画像形成装置
US7925815B1 (en) * 2006-06-29 2011-04-12 David Dunn Modifications to increase computer system security
US8661265B1 (en) 2006-06-29 2014-02-25 David Dunn Processor modifications to increase computer system security
US7610426B1 (en) * 2006-12-22 2009-10-27 Dunn David A System management mode code modifications to increase computer system security
US8316414B2 (en) * 2006-12-29 2012-11-20 Intel Corporation Reconfiguring a secure system
US20090109984A1 (en) * 2007-10-31 2009-04-30 Dell Products L.P. Wireless device with flash cache and boot from dock
US9286232B2 (en) * 2009-01-26 2016-03-15 International Business Machines Corporation Administering registered virtual addresses in a hybrid computing environment including maintaining a cache of ranges of currently registered virtual addresses
US20120117227A1 (en) * 2010-11-10 2012-05-10 Sony Corporation Method and apparatus for obtaining feedback from a device
US20120185688A1 (en) * 2011-01-13 2012-07-19 Google Inc. Processor mode locking
CN105788638A (zh) * 2011-03-04 2016-07-20 瑞萨电子株式会社 半导体器件
CN103984908B (zh) * 2014-05-05 2017-03-08 上海新储集成电路有限公司 一种南桥芯片及其应用方法
US10101928B2 (en) * 2016-02-19 2018-10-16 Dell Products L.P. System and method for enhanced security and update of SMM to prevent malware injection
US10534936B2 (en) * 2017-08-30 2020-01-14 Dell Products, Lp System and method for enabling and disabling of baseboard management controller configuration lockdown
US11354406B2 (en) 2018-06-28 2022-06-07 Intel Corporation Physics-based approach for attack detection and localization in closed-loop controls for autonomous vehicles
TWI682301B (zh) * 2018-11-19 2020-01-11 歐生全科技股份有限公司 多功能認證裝置與運作方法
NO346155B1 (en) * 2020-10-26 2022-03-28 Kongsberg Defence & Aerospace As Configuration authentication prior to enabling activation of a FPGA having volatile configuration-memory
US12292975B2 (en) * 2022-03-28 2025-05-06 Intel Corporation Method, system and apparatus to prevent denial of service attacks on PCIe based computing devices
US12164348B2 (en) * 2022-10-04 2024-12-10 Nxp Usa, Inc. Capturing of on-chip resets in an integrated circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855023A (ja) * 1994-07-25 1996-02-27 Motorola Inc データ処理システムおよびその方法
JP3461234B2 (ja) * 1996-01-22 2003-10-27 株式会社東芝 データ保護回路
US6026016A (en) * 1998-05-11 2000-02-15 Intel Corporation Methods and apparatus for hardware block locking in a nonvolatile memory
US6154819A (en) * 1998-05-11 2000-11-28 Intel Corporation Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks

Also Published As

Publication number Publication date
DE60206924D1 (de) 2005-12-01
EP1410143A2 (en) 2004-04-21
KR20030094396A (ko) 2003-12-11
TWI228889B (en) 2005-03-01
DE60206924T2 (de) 2006-07-27
EP1410143B1 (en) 2005-10-26
CN1520537A (zh) 2004-08-11
US20030028781A1 (en) 2003-02-06
JP2005501313A (ja) 2005-01-13
WO2002093336A3 (en) 2004-02-12
AU2002250591A1 (en) 2002-11-25

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