WO2002082639A1

WO2002082639A1 - Low noise amplifiers

Info

Publication number: WO2002082639A1
Application number: PCT/EP2002/003889
Authority: WO
Inventors: Pietro Andreani; Henrik Sjöland
Original assignee: Telefonaktiebolaget L M Ericsson (Publ)
Priority date: 2001-04-09
Filing date: 2002-04-08
Publication date: 2002-10-17
Also published as: WO2002082639A8; CN1515070A

Abstract

A low noise amplifier comprises a CMOS transistor (M1) having gate, source and drain terminals, the gate terminal being connected via a first impedance matching network (Lg) to an input terminal of the amplifier, and the source terminal being connected via a second impedance matching network (Ls) to a signal ground connection, and a capacitive impedance (Cd) connected between the gate terminal and the source terminal of the transistor (M1).

Description

LO NOISE AMPLIFIERS

The present invention relates to low noise amplifiers .

BACKGROUND OF THE INVENTION

When a weak radio signal is received, it must first be amplified before further processing. The amplifier performing this function must add as little noise as possible to the signal. Such an amplifier is referred to as a Low-Noise Amplifier (LNA) . Apart from low noise, the amplifier must also have a well determined resistive input impedance to enable the filter that typically precedes the amplifier to operate as desired. To understand the importance of LNAs, it should be noted that the noise-figure of a radio receiver can never be less than that of the LNA in the receiver. In a high performance radio receiver the first block is always a low noise amplifier (LNA) , noise performance of which sets a limit to that of the entire receiver. Therefore, if CMOS technology is to be used in demanding applications, it is important to be able to design CMOS LNAs with very low noise. In general, the requirements on an LNA are, apart from low noise, also high linearity, sufficiently high gain, well- defined resistive input impedance (to match the passive off-chip filter that precedes the LNA in almost all radio receivers) , and low power consumption.

There are several alternatives how to obtain a resistive input impedance. For instance, one can use a common-gate topology, so that the input conductance becomes equal to the transconductance of the transistor. The best noise performance, however, is- achieved with inductive source degeneration, an example of which is illustrated in Figure 1 of the accompanying drawings .

The circuit of Figure 1 comprises two transistors -_L and M₂_ Each transistor has gate, drain and source connections G, D and S respectively, the first transistor having its source connected to ground via an impedance LS and its gate G connected to an input of the circuit via an inductance LG. In the circuit of Figure 1 RS represents the source output impedance and VS represents the input voltage. The second transistor M₂ has its source connection connected to the drain connection of the first transistor M₁ and its drain connection connected a supply voltage VCC via an output inductance L_out . The gate connection of the second transistor M₂ is connected to the supply voltage VCC. The drain connection of the second transistor provides an output V_out of the circuit.

An inductor L_g is inserted in series with the source (emitter) of the input transistor m₁ . Together with the intrinsic gate-source (base-emitter) capacitance, this results in a resistive part of the input impedance. The inductor L_s will have a small inductance, and will introduce little noise even if it is a low quality on-chip component. The input impedance will be capacitive and resistive, which can be transformed to the desired impedance by an inductive matching network. A problem of this topology is the sensitivity to gate induced current noise, since such noise is enhanced by the Q-factor in the input circuit. A high Q is beneficial for reducing channel current noise, however, and in a design where the gate induced current noise is disregarded one might end up with a large Q, and a noise totally dominated by the gate induced current noise. For example, in CMOS, gate-induced noise is a problem that limits the achievable performance.

SUMMARY OF THE PRESENT INVENTION

According to one aspect of the present invention, there is provided an input device which decreases the amount of noise current injected at the input. To achieve the same input impedance, an additional capacitor is introduced between gate and source (base and emitter) of the input device. If this capacitance is of high quality, it introduces very low noise, and the total noise of the amplifier can be significantly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a low noise amplifier with inductive source degeneration;

Figure 2 illustrates a low noise amplifier embodying the present invention;

Figure 3 illustrates a MOS transistor; Figure 4 illustrates a small signal circuit for noise calculations; and

Figure 5 illustrates a plot of noise figure against transistor Q and width.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Although the present invention is described with reference to a MOS transistor, it will be readily appreciated that the principles can be applied to any transistor which exhibits a gate (or equivalent) noise related to the gate (or equivalent) capacitance. Figure 2 illustrates an embodiment of the present invention, which includes first and second transistors M_x and M₂ connected with one another and other components as shown in the Figure 1 circuit. In the embodiment of the present invention illustrated in Figure 2, an additional capacitance C_d is provided in parallel to the intrinsic gate capacitance C_gs of transistor M . The additional capacitance C_d has the effect of decoupling Q from C_gs, which allows for an adjustable reduction of Q for any given value of C_gs . This can be very important, since the gate induced current noise grows with the square of

In the following description, it will be shown that such a technique allows for the design of very low noise CMOS LNAs, without any associated power consumption penalties. In order to render the analysis manageable, all passive components will be treated as lossless. Thus, the calculated noise figures will represent minimum values for the available technology, design specifications, and power consumption levels. Figure 2 shows a simplified schematic of an LNA embodying the invention. Transistor M₂ has a minor influence on the noise behaviour of the LNA, and its contribution to the total noise is disregarded in the analysis. Table 1 summarizes a number of symbols used in the following, where the transistor referred to is M . The treatment will be confined to the case of a long-channel (or better, low-electric-field) transistor, for which the usual quadratic I_da - V_gg relation applies in the saturation region. For example, see "Operation and modelling of the MOS Transistor" , Yannis P. Tsiridis, 2^nd Edition, McGraw-Hill .1999 for a detailed explanation of a MOS transistor. Figure 3 illustrates a MOS transistor structure, and in particular illustrates the transistor width W and gate length L.

Table 1. Process and design parameters

Symbol Parameter

W Transistor width L Transistor length

I_ds Transistor channel current

V_ds Transistor drain- source voltage

V Transistor gate- source voltage

C_gs Transistor gate-source capacitance g_m Transistor transconductance

G_J-_J, Transistor bulk transconductance

G_do Transistor output conductance for V_dg =0 μ_n Electron mobility

C_ox Gate unit capacitance Y Channel current noise factor δ Gate induced current noise factor

R_s Source resistance ω_Q Angular frequency of operation k_B Boltzmann's constant T Absolute temperature

It is well-known that the input impedance of the circuit (neglecting g„^, whose influence on both input impedance and output noise is minimal) is given by

where L_t =L_g + L_g and C_t = C_d + C_gg . ___g_m can be written, in the usual long-channel approximation, as

At the resonance (operating) angular frequency

the impedance presented by the LNA must be equal to the source impedance matching; thus, the resulting total impedance at resonance is

ιn,res R_s + g_m = 2R_s c (4)

where the equality

g_m ^ = R_s (5)

must be fulfilled. The quality factor Q of the input circuit is then

The small signal equivalent circuit for the noise analysis is shown in Figure 3. Three noise sources have been included: the thermal noise of the source resistance (i_{n R}) , the thermal noise of the channel current (i_{n d}) , and the gate induced current noise (i_{n g}) . The corresponding noise densities are:

t² „,_g (9)

The correlation between gate induced current noise and channel current noise has been disregarded. Such noise can be readily shown to introduce only a very small error. Conventional circuit analysis gives the transfer function of the three noise sources to the output noise current i_n#out (see Figure 3) at resonance:

^ln,out,R ">^Λ (10)

¹n,out,d ^~ 2 ^l"'^d

Making use of equation (6) , the following noise figure is obtained at resonance: •2 -2

I n,out,R + I n,out,g + 1^' n,out,d

F =

I n.out.R δg ^m (Q² + i)P² + _Λg_do

= 1 + 5*. do 4^J

R_sQg

where

and the long-channel regime simplification g_do=g_m has been made. The commonly used expression

will be adopted in the following. Using equations (6) , (14), and (15), P can be expressed as

P= Q-2co_QR_sC_gs = Q-^Θ₀R_SC_0XWL (16)

Equation (13) can be rewritten (using equations (2) and

a - --ⁱ ≡ ] + aQ²W² + -W² + bQ-²W ' (17) where the expressions for a and b are obvious. A typical plot of expression (17) as a function of Q and W is shown in Figure 4. It is straightforward to check that expression (17) does not have a minimum for finite values of Q and W; rather, it can be made arbitrarily close to unity for any value of I_ds . However, this condition is approached when Q tends to infinity and W tends to zero, which are not reasonable choices for these parameters. In practice, Q must be limited for reasons such as linearity and sensitivity to parameter variations, and W must be large enough to allow for a given I_ds. A Q value can therefore be fixed which will be the maximum possible that can be tolerated, and derive and expression for the optimal transistor width W_opt in presence of such a Q. Taking the derivative of expression (17) with respect to W yields

(18)

Equating expression ( 18 ) to zero gives W_opt as

The corresponding value for P_opt is obtained by inserting expression (19) in expression (16):

Finally, the minimum value of the noise factor F_min, for a given Q, can be obtained from expressions (17) and (19) :

It is possible to compare the above noise figure to what can be achieved without the extra capacitor C_d, for the same value of Q and I_ds . We therefore define the suppression factor S as

where F_p=1 is given by expression (13) with P=l Accordingly:

with W_p=1 f rom expressions ( 6 ) and ( 15 ]

W - (24)

Q- ^₀R_SC_0XL

Expressions ( 19) , (20 ) , and (24 ) yield

F_mιn can be written as

F_P_. - 1 ^ = 1+ ^7 — (26)

Thus, the higher S, the larger the improvement on F_min.

In the limit of a high Q, S is proportional to Q 3/2. The relations found above lead to a realizable amplifier, that is, all design parameters can be assigned reasonable values. In the description below, process parameters are taken from a standard 0.35μm CMOS process, where δ=2γ (a recent simulation-based analysis of the values for Y and δ is found in Proceedings CICC 1999, paper 16-2, May 1999, where the symbol β is used instead of δ) . The operating (resonance) frequency is 1.8 GHz, the source impedance is 50Ω, and the current consumption is set to 1 mA. Table 2 summarizes both process and design data.

The design procedure is started by fixing Q at the moderately high value of three. Expressions (19) and (20) then give W_opt = 35μm and P = 0.15, respectively.. Frorτt expression (15) we obtain C_gs = 44fF, and from expression (14) C_d = 250fF. Expressions (2) and .(5) yield respectively g_m ~ 5.8 mA/V and L_s ~ 2.5 nH. Finally, L_g calculated from expression (3) is 24 nH. Clearly, all components (except possibly l_g) have integratable values.

Expression (21) gives F_min = 1.26 ( = 0.99 dB) , which is a very low value. From the suppression factor S ~ 4.59 we can calculate the value of F when P=l, resulting in F_p=1 = 2.18 (= 3.38 dB) , a much higher value. Table 3 shows the component values for the cases Q=2 and Q=4 as well.

Table 2. Process and design parameter values.

Parameter Value

L_min (eff) . 0.4 μm _n 0 . 04 m²/V

Cox 4 . 710 ^{" 3}F/m² . Y 2 . . 0 δ 4 . . 0

Ids 1 A

2 π . 1 . 8 ι°V ^• 1

Table 3. Component values and noise performance of the amplifier. ,

It will be readily apparent that the embodiments of the invention presented above allow for the design of very low noise CMOS LNAs at low power consumption levels .

The principles of the invention of applicable to differential low noise amplifiers as well as to the LNA illustrated and described above. In the case of a differential LNA, the source terminal would be connected to the signal ground (or common) terminal via an impedance matching network such as an inductor. The principles of the invention are also applicable to transistors in general, for example bipolar transistors. In the case of bipolar transistors, the input and "supply" terminals are provided by the base, emitter and collector.

Claims

CLAIMS :

1. A low noise amplifier comprising: / a CMOS transistor having gate, source and drain terminals, the gate terminal being connected via a first impedance matching network to an input terminal of the amplifier, and the source terminal being connected via a second impedance matching network to a signal ground connection; and a capacitive impedance connected between the gate terminal and the source terminal of the transistor.

2. A low noise amplifier comprising a transistor having an input terminal and first and second supply terminals, and a capacitive impedance connected between the input terminal and one of the first and second supply terminals.

3. A low noise amplifier comprising: a bipolar transistor having base, emitter and collector terminals, the base terminal being connected via a first impedance matching network to an input terminal of the amplifier and the emitter terminal being connected via a second impedance matching network to a signal ground terminal; a capacitive impedance connected between the base and emitter terminals of the transistor.