WO2002071474A3 - Method for broadening active semiconductor areas - Google Patents

Method for broadening active semiconductor areas Download PDF

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Publication number
WO2002071474A3
WO2002071474A3 PCT/EP2002/001786 EP0201786W WO02071474A3 WO 2002071474 A3 WO2002071474 A3 WO 2002071474A3 EP 0201786 W EP0201786 W EP 0201786W WO 02071474 A3 WO02071474 A3 WO 02071474A3
Authority
WO
WIPO (PCT)
Prior art keywords
pad
broadening
semiconductor substrate
oxide layer
active semiconductor
Prior art date
Application number
PCT/EP2002/001786
Other languages
German (de)
French (fr)
Other versions
WO2002071474A2 (en
Inventor
Dietmar Temmler
Andreas Wich-Glasen
Original Assignee
Infineon Technologies Ag
Dietmar Temmler
Andreas Wich-Glasen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Dietmar Temmler, Andreas Wich-Glasen filed Critical Infineon Technologies Ag
Publication of WO2002071474A2 publication Critical patent/WO2002071474A2/en
Publication of WO2002071474A3 publication Critical patent/WO2002071474A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The invention relates to a method for broadening active semiconductor areas (2) on a semiconductor substrate (1) that has at least one trench isolation (3). The method is composed of the following steps: deposition of a pad-oxide layer (5) on a surface (4) of the semiconductor substrate (1); deposition of a pad-nitride layer (6) on the pad-oxide layer (5); structuring of the pad-nitride layer (6) to create at least one opening in the pad-nitride layer (6) and etching of the trench isolation(s) (3) in the pad-oxide layer (5) and the semiconductor substrate (1). The aim of the invention is to adjust the broadening of the structures of active semiconductor areas in a simple and cost-effective manner that is substantially independent of other process steps during the production of the component. To achieve this, the inventive method is characterised by the selective deposition of an epitaxy layer (7) with a predetermined thickness and by the oxidation of the surface (4) of the semiconductor substrate (1), to create a thin oxide layer (9) for passivation.
PCT/EP2002/001786 2001-03-07 2002-02-20 Method for broadening active semiconductor areas WO2002071474A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2001110974 DE10110974C2 (en) 2001-03-07 2001-03-07 Method for widening an active semiconductor region on a semiconductor substrate
DE10110974.1 2001-03-07

Publications (2)

Publication Number Publication Date
WO2002071474A2 WO2002071474A2 (en) 2002-09-12
WO2002071474A3 true WO2002071474A3 (en) 2002-11-28

Family

ID=7676613

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/001786 WO2002071474A2 (en) 2001-03-07 2002-02-20 Method for broadening active semiconductor areas

Country Status (3)

Country Link
DE (1) DE10110974C2 (en)
TW (1) TW527645B (en)
WO (1) WO2002071474A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035481A (en) * 2012-08-09 2013-04-10 上海华虹Nec电子有限公司 Formation method of groove

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980306A (en) * 1987-11-11 1990-12-25 Seiko Instruments Inc. Method of making a CMOS device with trench isolation device
JPH0621214A (en) * 1992-07-03 1994-01-28 Seiko Epson Corp Manufacture of semiconductor device
EP0736897A2 (en) * 1995-04-04 1996-10-09 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit
US6063691A (en) * 1997-12-29 2000-05-16 Lg Semicon Co., Ltd. Shallow trench isolation (STI) fabrication method for semiconductor device
US6184108B1 (en) * 1996-01-31 2001-02-06 Advanced Micro Devices, Inc. Method of making trench isolation structures with oxidized silicon regions
US6200881B1 (en) * 1999-07-23 2001-03-13 Worldwide Semiconductor Manufacturing Corp. Method of forming a shallow trench isolation
US6274455B1 (en) * 1997-12-29 2001-08-14 Hyundai Electronics Industries Co., Ltd. Method for isolating semiconductor device
JP2001284445A (en) * 2000-03-29 2001-10-12 Toshiba Corp Semiconductor device and manufacturing method therefor
US20020001918A1 (en) * 2000-06-30 2002-01-03 Park Myoung Kyu Method for forming a field oxide film on a semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4745081A (en) * 1985-10-31 1988-05-17 International Business Machines Corporation Method of trench filling
US4900692A (en) * 1989-04-24 1990-02-13 Motorola, Inc. Method of forming an oxide liner and active area mask for selective epitaxial growth in an isolation trench
JPH1174522A (en) * 1996-12-19 1999-03-16 Texas Instr Inc <Ti> Method and device for forming planar field effect transistor with source and drain on insulator
US5879998A (en) * 1997-07-09 1999-03-09 Advanced Micro Devices, Inc. Adaptively controlled, self-aligned, short channel device and method for manufacturing same
US5970363A (en) * 1997-12-18 1999-10-19 Advanced Micro Devices, Inc. Shallow trench isolation formation with improved trench edge oxide
KR100251280B1 (en) * 1998-03-25 2000-04-15 윤종용 Sti method

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980306A (en) * 1987-11-11 1990-12-25 Seiko Instruments Inc. Method of making a CMOS device with trench isolation device
JPH0621214A (en) * 1992-07-03 1994-01-28 Seiko Epson Corp Manufacture of semiconductor device
EP0736897A2 (en) * 1995-04-04 1996-10-09 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
US6184108B1 (en) * 1996-01-31 2001-02-06 Advanced Micro Devices, Inc. Method of making trench isolation structures with oxidized silicon regions
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit
US6063691A (en) * 1997-12-29 2000-05-16 Lg Semicon Co., Ltd. Shallow trench isolation (STI) fabrication method for semiconductor device
US6274455B1 (en) * 1997-12-29 2001-08-14 Hyundai Electronics Industries Co., Ltd. Method for isolating semiconductor device
US6200881B1 (en) * 1999-07-23 2001-03-13 Worldwide Semiconductor Manufacturing Corp. Method of forming a shallow trench isolation
JP2001284445A (en) * 2000-03-29 2001-10-12 Toshiba Corp Semiconductor device and manufacturing method therefor
US6399992B1 (en) * 2000-03-29 2002-06-04 Kabushiki Kaisha Toshiba Semiconductor device and method of making the same
US20020001918A1 (en) * 2000-06-30 2002-01-03 Park Myoung Kyu Method for forming a field oxide film on a semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 018, no. 225 (E - 1541) 22 April 1994 (1994-04-22) *
PATENT ABSTRACTS OF JAPAN vol. 2002, no. 02 2 April 2002 (2002-04-02) *

Also Published As

Publication number Publication date
TW527645B (en) 2003-04-11
DE10110974C2 (en) 2003-07-24
DE10110974A1 (en) 2002-09-26
WO2002071474A2 (en) 2002-09-12

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