WO2002071474A2

WO2002071474A2 - Method for broadening active semiconductor areas

Info

Publication number: WO2002071474A2
Application number: PCT/EP2002/001786
Authority: WO
Inventors: Dietmar Temmler; Andreas Wich-Glasen
Original assignee: Infineon Technologies Ag
Priority date: 2001-03-07
Filing date: 2002-02-20
Publication date: 2002-09-12
Also published as: TW527645B; DE10110974C2; DE10110974A1; WO2002071474A3

Abstract

The invention relates to a method for broadening active semiconductor areas (2) on a semiconductor substrate (1) that has at least one trench isolation (3). The method is composed of the following steps: deposition of a pad-oxide layer (5) on a surface (4) of the semiconductor substrate (1); deposition of a pad-nitride layer (6) on the pad-oxide layer (5); structuring of the pad-nitride layer (6) to create at least one opening in the pad-nitride layer (6) and etching of the trench isolation(s) (3) in the pad-oxide layer (5) and the semiconductor substrate (1). The aim of the invention is to adjust the broadening of the structures of active semiconductor areas in a simple and cost-effective manner that is substantially independent of other process steps during the production of the component. To achieve this, the inventive method is characterised by the selective deposition of an epitaxy layer (7) with a predetermined thickness and by the oxidation of the surface (4) of the semiconductor substrate (1), to create a thin oxide layer (9) for passivation.

Description

description

Process for widening active semiconductor areas

The invention relates to a method for modifying active semiconductor regions of a semiconductor component and, in particular, for widening edge zones of these regions which represent electronic elements after the semiconductor component has been completed. Such a method for widening active semiconductor regions on a semiconductor substrate which has at least one trench isolation (STI) comprises the steps of depositing a pad oxide layer on a surface of the semiconductor substrate; Depositing a pad nitride layer on the pad oxide layer; Patterning the pad nitride layer to create at least one opening in the pad nitride layer; Etching a first trench in the pad oxide layer and in the semiconductor substrate.

When semiconductor functional elements are further reduced, the structuring of active areas (active area,

AA) increasingly difficult. The necessary high packing densities require the introduction of 1: 1 pitches with regard to the final dimensions, which places high demands on the lithography (resolution). In order to achieve a sufficiently large etch reserve (etch bias) for the subsequent structuring etching of a trench isolation (shallow trench isolation, STI), the lithography must produce correspondingly wider resist structures with the same width of active area and isolation trench (1: 1 pitch) (in order to form short circuits, so-called . Bridging faults to avoid). In addition, the etch reserve in STI structuring has a stronger impact on the structure widths for scaled technologies in absolute terms. Subsequent process steps (oxidations) are also becoming more critical for scaled technologies with regard to the minimal structures (critical dimension, CD). For example, while 15 nm oxidations with 0.2 μm technologies only mean a CD loss of approx. 7.5%, with 0.1 μm technologies it would already be 15%. Another problem with STI trench isolation is the impairment of, for example, the gate oxide at the edges of the trench (trench corner degradation). In IEEE, IEDM 96, pages 747 to 750, Tai-su Park et al. titled "Correlation between Gate Oxide Reliability and the Profile of the Trench Top Corner in Shallow Trench Isolation" describes the rounding of the trench edges and the use of an Si0 ₂ spacer, which has the effect of impairing the edge of the gate oxide in an STI Have the component reduced.

The described problem of structure widths and etched surfaces for active, STI-insulated semiconductor areas, their negative effects on electrical and process properties has so far been developed with great effort by the

Single process lithography and plasma etching as well as development of subsequent process steps (cleaning, oxidation) solved.

The object of the present invention is to specify a method with which the structure widths of active semiconductor regions can be set in a simple and inexpensive manner, essentially independently of other process steps in the production of the component.

This object is achieved by the method according to claim

1. Preferred embodiments of the invention are the subject of the dependent claims.

According to the invention, the active semiconductor regions are covered with an epitaxial layer. The epitaxial layer on the one hand allows the semiconductor structure to become thicker in the vertical direction, on the other hand the trenches of the semiconductor structure grow in the horizontal direction, its clear width between adjacent structures of the semiconductor structure (projecting on the structure surface) becomes smaller. This epitaxial layer also changes the area ratio between the active and passive region of the semiconductor. In addition to the steps of depositing a pad oxide layer on a surface of the semiconductor substrate, the method according to the invention for widening active semiconductor regions on a semiconductor substrate which has at least one trench isolation comprises; Depositing a pad nitride layer on the pad oxide layer; Structuring the pad nitride layer to produce at least one opening in the pad nitride layer and etching the at least one trench isolation in the pad oxide layer and in the semiconductor substrate according to the invention, selectively depositing an epitaxial layer with a predetermined thickness and oxidizing the surface of the semiconductor substrate Creation of a thin oxide layer for passivation.

In a preferred embodiment of the invention, the thin epitaxial layer has a predetermined doping.

The thickness of the epitaxial layer is preferably less than 0.3 times a critical structural dimension and is in particular of the order of 50 nm.

The selective deposition according to the invention of a thin epitaxial semiconductor layer after the STI structuring makes it possible for all STI-applying technologies to expose narrower active structures (active area or AA structures), the exposure in the less critical, "relaxed" area of lithography -Process window to perform. In addition, the CD loss that occurs can be compensated for by epitaxy and even a CD gain can be achieved. Characterized in that the exposure in the less critical area of the lithographic process window is performed, the Ri ^¬ siko is lowered a short-circuiting.

Further advantages of the invention are the reduction of at ^¬ demands on the mask manufacturing (waiving Maskenbi- as) and the elimination or minimization of the unwanted etching away of the pad nitride (Padnitrid Pull Back). In addition, epitaxially grown surfaces have significantly fewer defects than etched surfaces due to the etching damage there. This is associated with a reduction in leakage currents in this area. The damage caused by the structuring etching (damages, striations), which are usually eliminated with the following cleaning and oxidation, are epitaxially overgrown according to the invention. The minimum thickness of the oxide on the active area (AAOX), which was previously necessary for eliminating defects, can be reduced. This means a CD gain as well as an advantageous reduction in the thermal budget.

Another advantage is the epitaxial pre-rounding of the edge of the active area, which is associated with a reduction of the so-called divot, which reduces its effect on the threshold voltage of the semiconductor element (array V _τ ) and the reliability of the gate oxide (GOX reliability) ) is improved.

Further features and advantages of the invention result from the following description of preferred exemplary embodiments.

1 shows a cross section through a semiconductor structure with an active region and STI trench according to the prior art.

2 shows a cross section through a semiconductor structure with an active region and an STI trench after a first step of the method according to the invention.

3 shows a cross section through a semiconductor structure with an active region and an STI trench after a second step of the method according to the invention. 4 shows an electron micrograph of a structure which was produced using the method according to the invention.

1 shows a cross section through a semiconductor structure according to the prior art, schematically and not to scale. After preceding process steps, an active region 2 is located on a semiconductor substrate 1 and is separated from adjacent active regions by at least one trench isolation 2. The corresponding method steps for the production of the active region 2 and the at least one trench insulation 3 comprise, as a first step, the deposition of a pad oxide layer 5 on a surface 4 of the semiconductor substrate 1. A pad nitride layer 6 is then placed on the pad oxide layer 5 deposited. The thickness of the pad oxide layer 5 is of the order of 10 to 100 nm, the thickness of the pad nitride layer 6 is between 100 and 200 nm. The pad nitride layer 6 is structured in order to create at least one opening in the pad nitride layer 6. The pad oxide layer 5 and partially the semiconductor substrate 1 are removed by etching in the opening in the pad nitride layer 6, so that at least one trench insulation 3 is produced.

In order to be able to adjust the structure width of the active semiconductor region in a simple and inexpensive manner and essentially independently of other process steps, the edge zones of the active semiconductor region are subsequently modified according to the invention. This is done by additional selective deposition of an epitaxial layer 7 on the

Semiconductor structure according to the steps described above, at the end of which the structure in FIG. 1 is present.

The structure after the epitaxial layer 7 has been deposited according to the invention is shown in FIG. 2. In contrast to the known applications of selective epitaxy in the semiconducting ^¬ terherstellung be the invention, selectively deposited epitaxial semiconductor layer 7 only modifies the edge zones of the active regions 2. The epitaxial layer 7 is preferably very thin and no complete electronic functions are implemented therein. In particular, their thickness is less than 0.3F, where F is the critical structural dimension of the technology under consideration.

The active region 2 in FIG. 2 is widened overall by the selective deposition of the epitaxial layer 7 with a predetermined thickness. The situation after the epitaxial deposition on the side of the active region 2 at an edge 8, at which the pad nitride layer 6, the pad oxide layer 5 and the epitaxial layer 7 meet, is shown in an enlarged representation as an insert in FIG. 2.

After the epitaxial layer 7 has been applied in FIG. 2, the structure is passivated.

3 shows a cross section through the structure after its oxidation. By oxidizing the structure according to FIG. 2, a thin oxide layer 9 is generated, which serves to passivate the structure. Here, too, the critical area of the edge 8 of the active area 2 is shown in an enlarged representation as an insert in FIG. 3.

The deformation at the edge 8, which was caused by the epitaxial growth of the semiconductor layer 7, is further increased by the subsequent oxidation. The deformation can, however, be eliminated using known method steps, which is explained further below. 2 and 3, the possibility of changing the horizontal extent of an active area 2 after the lithography permits a "more relaxed" structuring of active area 2 and STI trench isolation 3. The thin epitaxial layer 7 can be produced with pure Si. In particular, however, the epitaxial layer 7 can be deposited in-situ with a doping that is advantageous for the electrical function of the active components. For example, field threshold voltages can be set and the narrow channel effects of scaled MOS transistors can be counteracted.

FIG. 4 shows an electron micrograph of an active, STI-insulated semiconductor region that is broadened by means of selective Si epitaxy in a 140 nm DRAM process based on a one-transistor trench memory cell. After the STI etching, the remaining lacquer was removed, and this was followed by an etching process in the HF field and the cleaning of the structure. This was followed by a baking process in an H ₂ atmosphere in the epitaxial system. With this it is possible to remove the natural oxide layer, smooth the surface and heal etching damage. This surface treatment was followed by the selective epitaxial growth according to the invention with a thickness of approximately 25 nm. As can be seen in FIG. 4, the thickness of the epitaxial layer is approximately the same on both sides of the active region and is 28.2 nm and 26.7 nm.

reference numeral

1 semiconductor substrate

2 active semiconductor area (AA) 3 STI trenches

4 surface of the semiconductor substrate

5 pad oxide layer

6 pad nitride layer

7 epitaxial layer 8 edge of the active semiconductor region (AA)

9 oxide layer

Claims

claims

1. A method for widening active semiconductor regions (2) on a semiconductor substrate (1) which has at least one trench isolation (3), with the steps

Depositing a pad oxide layer (5) on a surface (4) of the semiconductor substrate (1);

Depositing a pad nitride layer (6) on the pad oxide layer (5); Structuring the pad nitride layer (6) to create at least one opening in the pad nitride layer (6) and etching the at least one trench insulation (3) in the pad oxide layer (5) and in the semiconductor substrate (1); selective deposition of an epitaxial layer (7) with a predetermined thickness and

Oxidizing the surface (4) of the semiconductor substrate (1) to produce a thin oxide layer (9) for passivation.

2. The method according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the thin epitaxial layer (7) has a predetermined doping.

3. The method of claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the predetermined thickness of the epitaxial layer (7) smaller than that

Is 0.3 times a critical structural dimension.

4. The method according to any one of the preceding claims, that the epitaxial layer (7) has a predetermined thickness of the order of 15 to 50 nm.