WO2002067263A2

WO2002067263A2 - Contact system comprising a dielectric antifuse for an ic-memory element and method for producing one such contact system

Info

Publication number: WO2002067263A2
Application number: PCT/EP2002/000145
Authority: WO
Inventors: Dirk Toebben
Original assignee: Infineon Technologies Ag
Priority date: 2001-02-19
Filing date: 2002-01-09
Publication date: 2002-08-29
Also published as: DE10107664A1; WO2002067263A3

Abstract

The invention relates to a contact system comprising a dielectric antifuse (4) for an IC-memory component, and a method for producing one such contact system. Said contact system comprises a metallisation region (2, 3) which is arranged on a substrate (1) and is surrounded by an isolation layer (17). An isolation layer (4) used as a dielectric antifuse is arranged on said metallisation region (2, 3). A metallisation layer is then applied to the dielectric antifuse, said metallisation layer being used as a bit line (5) of the IC-memory component and being preferably produced according to RIE technology. As the dielectric antifuse (4) is arranged directly below the bit line (5), it is protected from damage which may occur during later steps in the process, especially when applying a top contact (9) to the bit line (5).

Description

description

Contact arrangement with a dielectric fuse for an IC memory element and method for producing such a contact arrangement

The invention relates to a contact arrangement with a dielectric fuse for an IC memory element and a method for producing such a contact arrangement.

IC memory chips, such as DRAMs, usually include a larger number of redundant memory cells that can be activated in the event of a malfunction of individual standard memory cells. For this purpose, the redundant memory cells or their peripheral circuitry have dielectric fuses which, if necessary, can be destroyed by applying current in order to establish a conductive connection between the adjacent metal layers.

Due to the function of the dielectric fuse to create an electrical connection when an overcurrent is applied instead of interrupting the electrical connection, as is the case with conventional fuses, it is actually an "anti-fuse" in terms of function. In the following description however, the term "fuse" is used to describe such an element.

FIGS. 3a-d show a method for producing a contact arrangement with a dielectric fuse, as is known from the production of a DRAM, in particular using silicon technology.

In FIG. 3a, reference numeral 20 denotes an insulation layer, for example made of silicon dioxide, into which two metallization regions 21a, 21b made of tungsten are introduced. The metallization regions 21a, 21b each serve as Bit line for reading out or writing in

Memory information from a memory cell of the DRAM.

The metallization regions 21a, 21b are produced in a method in which a trench etching first takes place in the insulation layer 20 and then tungsten is deposited over the entire surface. The surface is then planarized by a CMP (chemical mechanical polishing) process, which results in the separate metallization regions 21a, 21b.

As shown in FIG. 3b, in a subsequent process step, a dielectric fuse 22 consisting of several layers is applied to the resulting structure. The fuse stack 22 preferably consists of an electrically insulating layer, for example of SiN, and an electrically conductive layer, for example of WSi _x , the upper of the two layers being necessary so that a later contact etching process does not damage the lower dielectric layer ,

By applying photoresist 23 and then etching away areas not covered by photoresist 23, a structure is finally obtained as shown in FIG. 3c. In the circuit of a redundant memory cell, the fuse stack 22, which represents a fusible link, is arranged on the right-hand metallization region 21b, while the fuse stack has been removed on the left-hand side in order to establish a standard contact.

An oxide layer 24, e.g. applied by means of CVD.

As shown in FIG. 3d, contact holes 25a, 25b are then formed above the first and second metallization regions 21a, 21b, respectively, and filled with tungsten to fill the contacts 2βa, 26b. The surface of the structure is in turn processed using CMP.

As can be clearly seen from FIG. 3d, the fuse stack 22 is attacked by the etching of the contact hole 25b, so that the contact 26b projects slightly downward into the fuse stack 22. In order to avoid excessive damage to the fuse stack 22 with the consequence of undesired contacting of the adjacent metal layers 21b and 26b, it is necessary, on the one hand, to apply a relatively thick protective layer to the dielectric layer. On the other hand, due to the small dimensions of the fuse stack 22, it is still possible for an unintentional through-connection to occur.

It is therefore the object of the present invention to create a contact arrangement with a dielectric fuse or a corresponding production method in which damage to the dielectric fuse by subsequent process steps is largely ruled out.

According to the invention, this object is achieved by the contact arrangement having the features of patent claim 1 and by the method for producing a contact arrangement having the features of patent claim 11.

The idea on which the present invention is based essentially consists in arranging the dielectric fuse below, preferably immediately below, the bit line in order to protect it from a subsequent contact etching process.

The contact arrangement according to the invention with a dielectric fuse essentially comprises a metallization region arranged on a substrate, an insulation layer serving as a dielectric fuse, which is provided on the metallization region, and a further metallization layer. which serves as the bit line of an IC memory chip, the dielectric fuse layer being provided below, preferably directly below, the bit line.

The bit line is preferably produced using RIE technology (reactive iron etchmg). With the RIE technique, a layer is applied over a large area and then structured as desired using lithography and etching processes. This has the advantage that the distance between adjacent bit lines can already be chosen larger in lithography than in a manufacture using damascene technology, as a result of which the bit line shunt capacitance is ultimately reduced.

The metallization region preferably comprises an electrode of a transistor, such as the gate contact of a MOS transistor, and a contact (bottom contact) for contacting the transistor electrode.

In one exemplary embodiment, dielectric fuse layer is arranged between a bottom contact and the bit line.

According to a preferred embodiment, the dielectric fuse consists of a nitride layer, in particular a silicon nitride layer S ₃ N ₄ .

According to a further preferred development, the bit line consists of several layers, in particular three layers. In this case, the bit line comprises a middle layer made of aluminum and an upper and a lower layer preferably made of Ti and / or TiN.

According to a further preferred development, the dielectric fuse lies above an insulation layer located in the substrate, in particular an STI (shallow trench insulation) layer. This has the advantage that the substrate is not damaged by subsequent process steps. The method according to the invention for producing such a contact arrangement with a dielectric fuse includes, among other things, the provision of a circuit substrate, the provision of a metallization region on the circuit substrate and the arrangement of one serving as a dielectric fuse

Insulation layer over the metallization area. Furthermore, the manufacturing method according to the invention includes the application of a bit line, preferably using RIE technology, to the insulation layer.

The bit line preferably consists of several layers, in particular a middle conductive layer and outer cladding layers, e.g. made of Ti and / or TiN.

The bit line is preferably sputtered onto the fuse layer.

The invention is explained in more detail below with reference to the accompanying drawings.

Show it:

Fig. La, lb equivalent circuit diagrams of a memory cell and a peripheral transistor of a DRAM;

2 shows an example of a contact arrangement with a dielectric fuse designed according to an embodiment of the invention; and

3a-d are schematic representations of various

Process steps of a known manufacturing method for a contact arrangement with dielectric fuse.

In the figures, identical reference symbols designate identical or functionally identical components. FIG. 1 a shows an equivalent circuit diagram of a memory cell in a DRAM, with a field effect transistor 11 for controlling the reading out or writing of information from or into a capacitance 12. The gate contact 13 of the transistor 11 is controlled via a so-called word line 14.

The information stored in the capacitance 12 is read out via the contacts 15, 16 of the transistor 11 via a so-called bit line 17.

A peripheral transistor 19 shown in FIG. 1b comprises a gate contact 18 which is connected to the bit line 5 via a conductor 3 leading to the gate contact 2.

The drain and source contact 30, 31 of the peripheral transistor 19 are as CD contacts (Contact to

Diffusion) and are each connected to a metallic conductor track 32.

A possible location for the arrangement of the dielectric fuse is between the conductor 3 and the bit line 5. However, the fuse layer could also be arranged in a memory cell of the memory element.

The topography of a corresponding contact arrangement according to an embodiment of the invention is shown in FIG. 2.

The contact arrangement shown in FIG. 2 comprises a metallization region which is arranged on a substrate 1 and forms the gate contact 2 of the peripheral transistor 19. The gate contact 2 usually consists of a large number of individual layers, such as, for example, polysilicon, tungsten silicide and silicon nitride.

A wedge-shaped contact 3 (bottom contact) for contacting the gate contact 2 is provided above the gate contact 2. The contacts 2 and 3 are surrounded by an insulation layer 17, such as Si0 ₂ or BPSG (boron phosphorus silicate glass), which is applied to the substrate 1.

The surface of the insulation layer contact structure is preferably planed by means of CMP, so that the bottom contact 3 is flush with the insulation layer 17.

Finally, the dielectric fuse layer 4 is applied to this planarized surface. This layer is then structured, as explained with reference to FIG. 3.

A bit line 5 consisting of a plurality of layers 6, 7, 8 is arranged directly on the dielectric fuse 4. The bit line 5 has two outer, an upper 6 and a lower layer 7, for example made of T1 / T1N ₄ , and a middle layer, preferably made of aluminum.

Since aluminum conducts much better than, for example, tungsten, this layer can be chosen to be very thin, which in particular reduces the bit line shunt capacitance. In addition, the lower edge of the bit line path is further away from the upper edge of the gate contact stack 2 than in the case of a bit line produced using m Damascene technology. With a bit line made in Damascene technology, this distance is always smaller than with the bit line 5 made with RIE technology, since the limiting factor for the layer thickness of the insulation layer 17 arranged above the gate contact stack 2 is the etching process for the contact hole of the bottom -Contact 3 and other contacts to the substrate.

In this exemplary embodiment, the bit line 5 is sputtered onto the dielectric fuse 4. Since this is a relatively cold process, there is no damage to the dielectric fuse 4. When structuring the bit line 5, the topography that is created by the fuse layer is not disruptive. The fuse layer 4 is structured in such a way that it overlaps the bottom contact 3 below it sufficiently to adequately protect the bottom contact 3 during a metal etching process.

Finally, a contact 9 (top contact) is applied to the bit line 5, which is used for global wiring of the memory chip and e.g. is formed from tungsten or copper.

The bit line 5 is in turn structured in such a way that it overlaps the top contact 9 lying above it sufficiently far to the side so that the contact hole etching process for the top contact 9 does not damage the fuse layer.

Before the top contact 9 is produced, HDP oxide (high density plasma) is preferably applied. The surface is preferably planarized using CMP.

The electrical fuse layers 4 are preferably arranged only over STI regions 10 in the substrate 1 in order to prevent the substrate 1 from being adversely affected by subsequent process steps in the production, in particular, of the dielectric fuse 4 and the bit line 5, and by the fuse blow process itself avoid.

Although the process complexity of these variants exceeds that of the current standard process, in which the bit line 5 is produced together with the bottom contact 3 using dual damascene technology, it has significant advantages, in particular with regard to the bit line auxiliary capacitance and with regard to reliability the dielectric fuse. LIST OF REFERENCE NUMBERS

1. Substrate

2. Metallization area

3. Bottom contact

4. Fuse

5th bit line

6. upper layer

7. lower layer

8. middle layer

9. Top contact

10. Isolation area

11. Transistor

12. Capacitor

13. Gate

14. Word line

15. Gate contact

16. Source contact

17. Insulation layer

20. Insulation layer

21a, b bit line

22. Fuse stack

23. Photoresist

24. Insulation layer

25a, b contact hole

26a, b contact

30. Contact

31. Contact

32. Head

Claims

claims

1. A contact arrangement with a dielectric fuse for an IC memory element, comprising:

a first metallization region (2, 3) arranged on a substrate (1);

an insulation layer (4) serving as a dielectric fuse above the metallization region (2, 3); and

a further metallization region (5), which serves as a bit line (5) of the IC memory element above the insulation layer (4).

2. Contact arrangement according to claim 1, d a d u r c h g e k e n n z e i c h n e t that arranged on the substrate (1)

Metallization region (2,3) has a transistor contact (2) and a contact (3) contacting the transistor contact.

3. Contact arrangement according to claim 1 or 2, so that the dielectric fuse (4) is arranged between the contact (3) for contacting the transistor contact (2) and the bit line (5).

4. Contact arrangement according to claim 1, 2 or 3, d a d u r c h g e k e n n z e i c h n e t that the transistor contact is a gate contact (2) of a FET transistor.

5. Contact arrangement according to one of the preceding claims, characterized in that the dielectric fuse (4) consists of a material that can be destroyed by applying current, so that a conductive connection can be established between the adjacent metal layers.

6. Contact arrangement according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the dielectric fuse (4) has a nitride layer.

7. Contact arrangement according to one of the preceding claims, such that the bit line (5) consists of several layers (6, 7, 8).

8. Contact arrangement according to one of the preceding claims, that the bit line (5) has a layer (8) made of aluminum.

9. Contact arrangement according to one of the preceding claims, so that the bit line (5) has an upper (6) and a lower (7) layer made of Ti and / or TiN.

10. Contact arrangement according to one of the preceding claims, so that the dielectric fuse (4) is arranged above an insulation layer (10) located in the substrate.

11. A method for producing a contact arrangement of an IC memory element with a dielectric fuse, comprising the following steps:

Providing a substrate (1);

Forming a first metallization region (2) on the substrate (1); Forming a contact (3) for contacting the metallization region (2);

Applying an insulation layer (4) serving as a dielectric fuse;

Structuring the insulation layer (4)

Application of a further metallization area, which serves as a bit line (5) of the IC memory element, the insulation layer (4) being arranged below the bit line (5); and

Structuring the bit line (5).

12. The method according to claim 11, so that the bit line (5) consists of several layers (6, 7, 8) and has a middle layer (8) made of aluminum.

13. Contact arrangement according to claim 11, so that the individual layers (6, 7, 8) of the bit line (5) are sputtered onto the dielectric fuse (4).

14. Contact arrangement according to claim 11 or 12, that also applies to the uppermost layer (6) of the bit line (5)

Contact (9) for contacting the bit line (5) is applied.

15. Contact arrangement according to one of the preceding

Process claims, that the bit line (5) is manufactured in RIE technology.