WO2002059945A3 - Structure de films oxydee et procede de realisation d'une structure d'oxyde metallique epitaxiale - Google Patents

Structure de films oxydee et procede de realisation d'une structure d'oxyde metallique epitaxiale Download PDF

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Publication number
WO2002059945A3
WO2002059945A3 PCT/US2002/002981 US0202981W WO02059945A3 WO 2002059945 A3 WO2002059945 A3 WO 2002059945A3 US 0202981 W US0202981 W US 0202981W WO 02059945 A3 WO02059945 A3 WO 02059945A3
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metal oxide
oxidized film
oxidized
film structure
making
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PCT/US2002/002981
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English (en)
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WO2002059945A2 (fr
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Shupan Gan
Yong Liang
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Battelle Memorial Institute
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Publication of WO2002059945A3 publication Critical patent/WO2002059945A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/16—Oxides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/16—Oxides
    • C30B29/22—Complex oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02301—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment in-situ cleaning
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Abstract

La présente invention concerne une structure oxydée stable et un procédé amélioré permettant la réalisation d'une structure de ce type, comprenant un procédé amélioré permettant le réalisation d'un modèle interfacial à partir duquel peut s'effectuer la croissance d'une structure d'oxyde métallique cristallin. Le procédé de l'invention comprend les étapes suivantes: utilisation d'un substrat ayant une surface propre; et dépôt d'un métal sur la surface à une température élevée sous une certaine dépression, afin de former une couche composée métal-substrat sur la surface, ladite couche ayant une épaisseur de moins d'une monocouche. La couche composée est alors oxydée par exposition de la couche composée essentiellement à de l'oxygène à une pression partielle faible et à basse température. Le procédé peut également comprendre le recuit de la surface sous une certaine dépression afin de permettre une meilleure stabilisation de la structure de films oxydée. La structure d'oxyde métallique cristallin peut ultérieurement effectuer une croissance épitaxiale grâce à l'utilisation de la structure de films oxydée en tant que modèle interfacial et au dépôt sur le modèle interfacial d'au moins une couche d'oxyde métallique cristallin.
PCT/US2002/002981 2001-01-26 2002-01-22 Structure de films oxydee et procede de realisation d'une structure d'oxyde metallique epitaxiale WO2002059945A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002242059A AU2002242059A1 (en) 2001-01-26 2002-01-22 Oxidized film structure and method of making epitaxial metal oxide structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/770,784 2001-01-26
US09/770,784 US6524651B2 (en) 2001-01-26 2001-01-26 Oxidized film structure and method of making epitaxial metal oxide structure

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WO2002059945A2 WO2002059945A2 (fr) 2002-08-01
WO2002059945A3 true WO2002059945A3 (fr) 2003-03-27

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US (1) US6524651B2 (fr)
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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6392257B1 (en) * 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
WO2002009187A2 (fr) * 2000-07-24 2002-01-31 Motorola, Inc. Diodes a heterojonction tunnel et processus de fabrication de celles-ci
US20020096683A1 (en) * 2001-01-19 2002-07-25 Motorola, Inc. Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate
US7371633B2 (en) * 2001-02-02 2008-05-13 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
US20020158245A1 (en) * 2001-04-26 2002-10-31 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices utilizing binary metal oxide layers
US20030012965A1 (en) * 2001-07-10 2003-01-16 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate comprising an oxygen-doped compound semiconductor layer
US20030010992A1 (en) * 2001-07-16 2003-01-16 Motorola, Inc. Semiconductor structure and method for implementing cross-point switch functionality
US7019332B2 (en) * 2001-07-20 2006-03-28 Freescale Semiconductor, Inc. Fabrication of a wavelength locker within a semiconductor structure
US6855992B2 (en) * 2001-07-24 2005-02-15 Motorola Inc. Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same
US6730575B2 (en) * 2001-08-30 2004-05-04 Micron Technology, Inc. Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure
US6916717B2 (en) * 2002-05-03 2005-07-12 Motorola, Inc. Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate
US20040012037A1 (en) * 2002-07-18 2004-01-22 Motorola, Inc. Hetero-integration of semiconductor materials on silicon
AU2002331705A1 (en) * 2002-08-16 2004-03-03 Midwest Research Institute Multi-junction, monolithic solar cell with active silicon substrate
US20060162767A1 (en) * 2002-08-16 2006-07-27 Angelo Mascarenhas Multi-junction, monolithic solar cell with active silicon substrate
US20040069991A1 (en) * 2002-10-10 2004-04-15 Motorola, Inc. Perovskite cuprate electronic device structure and process
US20040079285A1 (en) * 2002-10-24 2004-04-29 Motorola, Inc. Automation of oxide material growth in molecular beam epitaxy systems
US7169619B2 (en) * 2002-11-19 2007-01-30 Freescale Semiconductor, Inc. Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process
US6885065B2 (en) * 2002-11-20 2005-04-26 Freescale Semiconductor, Inc. Ferromagnetic semiconductor structure and method for forming the same
US6762114B1 (en) * 2002-12-31 2004-07-13 Texas Instruments Incorporated Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness
US6963090B2 (en) * 2003-01-09 2005-11-08 Freescale Semiconductor, Inc. Enhancement mode metal-oxide-semiconductor field effect transistor
DE10303875B4 (de) * 2003-01-31 2006-03-16 Technische Universität Clausthal Struktur, insbesondere Halbleiterstruktur, sowie Verfahren zur Herstellung einer Struktur
US7020374B2 (en) * 2003-02-03 2006-03-28 Freescale Semiconductor, Inc. Optical waveguide structure and method for fabricating the same
US6890816B2 (en) * 2003-02-07 2005-05-10 Freescale Semiconductor, Inc. Compound semiconductor structure including an epitaxial perovskite layer and method for fabricating semiconductor structures and devices
US20040164315A1 (en) * 2003-02-25 2004-08-26 Motorola, Inc. Structure and device including a tunneling piezoelectric switch and method of forming same
US6864141B1 (en) * 2003-06-03 2005-03-08 Lsi Logic Corporation Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion beams
US8766341B2 (en) * 2009-10-20 2014-07-01 The Regents Of The University Of California Epitaxial growth of single crystalline MgO on germanium
US11226507B2 (en) * 2019-10-29 2022-01-18 Psiquantum, Corp. Method and system for formation of stabilized tetragonal barium titanate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5482003A (en) * 1991-04-10 1996-01-09 Martin Marietta Energy Systems, Inc. Process for depositing epitaxial alkaline earth oxide onto a substrate and structures prepared with the process
US6110840A (en) * 1998-02-17 2000-08-29 Motorola, Inc. Method of passivating the surface of a Si substrate
EP1043427A1 (fr) * 1999-03-22 2000-10-11 Motorola, Inc. Structure semiconductrice comportant une interface en oxyde cristallin de métal alcalino-terreux entre du silicium et une couche d'oxyde monocristallin
WO2000060146A1 (fr) * 1999-04-06 2000-10-12 Ut-Battelle, Llc Structure d'oxyde cristallin semi-conductrice et procede generique pour former cette structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225031A (en) * 1991-04-10 1993-07-06 Martin Marietta Energy Systems, Inc. Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process
US6113690A (en) 1998-06-08 2000-09-05 Motorola, Inc. Method of preparing crystalline alkaline earth metal oxides on a Si substrate
US6022410A (en) 1998-09-01 2000-02-08 Motorola, Inc. Alkaline-earth metal silicides on silicon

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5482003A (en) * 1991-04-10 1996-01-09 Martin Marietta Energy Systems, Inc. Process for depositing epitaxial alkaline earth oxide onto a substrate and structures prepared with the process
US6110840A (en) * 1998-02-17 2000-08-29 Motorola, Inc. Method of passivating the surface of a Si substrate
EP1043427A1 (fr) * 1999-03-22 2000-10-11 Motorola, Inc. Structure semiconductrice comportant une interface en oxyde cristallin de métal alcalino-terreux entre du silicium et une couche d'oxyde monocristallin
WO2000060146A1 (fr) * 1999-04-06 2000-10-12 Ut-Battelle, Llc Structure d'oxyde cristallin semi-conductrice et procede generique pour former cette structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MCKEE R A ET AL: "MOLECULAR BEAM EPITAXY GROWTH OF EPITAXIAL BARIUM SILICIDE, BARIUM OXIDE, AND BARIUM TITANATE ON SILICON", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 59, no. 7, 12 August 1991 (1991-08-12), pages 782 - 784, XP000233755, ISSN: 0003-6951 *

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US20020102418A1 (en) 2002-08-01
AU2002242059A1 (en) 2002-08-06
WO2002059945A2 (fr) 2002-08-01
US6524651B2 (en) 2003-02-25

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