WO2002059704A2 - Procede et appareil de generation automatique de programmes pour traitement de plaquettes dans un dispositif de traitement multichambre de plaquettes a semi-conducteurs - Google Patents

Procede et appareil de generation automatique de programmes pour traitement de plaquettes dans un dispositif de traitement multichambre de plaquettes a semi-conducteurs Download PDF

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WO2002059704A2
WO2002059704A2 PCT/US2002/002378 US0202378W WO02059704A2 WO 2002059704 A2 WO2002059704 A2 WO 2002059704A2 US 0202378 W US0202378 W US 0202378W WO 02059704 A2 WO02059704 A2 WO 02059704A2
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wafer
vertex
successor
schedule
vertices
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PCT/US2002/002378
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WO2002059704A3 (fr
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Dusan B. Jevtic
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Applied Materials, Inc.
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Priority claimed from US09/771,254 external-priority patent/US6725114B1/en
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Publication of WO2002059704A2 publication Critical patent/WO2002059704A2/fr
Publication of WO2002059704A3 publication Critical patent/WO2002059704A3/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41865—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by job scheduling, process planning, material flow
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the present invention relates to a multiple chamber wafer processing tool and, more particularly, to a method and apparatus for automatically generating a schedule (s) for a semiconductor wafer within a multiple chamber semiconductor wafer processing tool .
  • FIG. 1 depicts, in part, a schematic diagram of the Endura ® System.
  • the cluster tool 100 contains, for example, four process chambers 104, 106, 108, 110, a transfer chamber 112, a preclean chamber 114, a buffer chamber 116, a wafer orienter/degas chamber 118, a cooldown chamber 102, and a pair of loadlock chambers 120 and 122.
  • Each chamber represents a different stage or phase of semiconductor wafer processing.
  • the buffer chamber 116 is centrally located with respect to the loadlock chambers 120 and 122, the wafer orienter/degas chamber 118, the preclean chamber 114 and the cooldown chamber 102. To effectuate wafer transfer amongst these chambers, the buffer chamber 116 contains a first robotic transfer mechanism 124.
  • the wafers 128 are typically carried from storage to the system in a plastic transport cassette 126 that is placed within one of the loadlock chambers 120 or 122.
  • the robotic transport mechanism 124 transports the wafers 128, one at a time, from the cassette 126 to any of the three chambers 118, 102, or 11 .
  • a given wafer is first placed in the wafer orienter/degas chamber 118, then moved to the preclean chamber 114.
  • the cooldown chamber 102 is generally not used until after the wafer is processed within the process chambers 104, 106, 108, 110.
  • Individual wafers are carried upon a wafer transport blade 130 that is located at the distal end of the first robotic mechanism 124.
  • the transport operation is controlled by a sequencer 136.
  • the transfer chamber 112 is surrounded by and has access to the four process chambers 104, 106, 108 and 110 as well as the preclean chamber 114 and the cooldown chamber 102.
  • the transfer chamber 112 contains a second robotic transport mechanism 132.
  • the mechanism 132 has a wafer transport blade 134 attached to its distal end for carrying the individual wafers.
  • the wafer transport blade 134 of the second transport mechanism 132 retrieves a wafer from the preclean chamber 114 and carries that wafer to the first stage of processing, for example, a physical vapor deposition (PVD) stage within chamber 104. Once the wafer is processed and the PVD stage deposits material upon the wafer, the wafer can then be moved to a second stage of e processing and so on.
  • PVD physical vapor deposition
  • the transport mechanism 132 moves the wafer from the process chamber and transports the wafer to the cooldown chamber 102.
  • the wafer is then removed from the cooldown chamber using the first transport mechanism 124 within the buffer chamber 116.
  • the wafer is placed in the transport cassette 126 within the loadlock chamber 122.
  • a cluster tool may be coupled to a factory interface comprising at least one factory interface robot, one or more metrology chambers/defect control chambers and one or more load ports, and one or more wafer orienting chambers.
  • the factory interface is coupled to the load locks of the cluster tool.
  • a cluster tool contains n chambers, denoted by C x , C 2 , ..., C n , one or more transfer chambers (robots) 112 and 116, and one or more loadlocks 120 and 122.
  • the exact arrangement of chambers, robots and loadlocks is referred to as the "configuration" of the tool.
  • a wafer W a to be processed is taken from a loadlock, ' placed successively into various chambers as each chamber performs a particular process upon the wafer.
  • a wafer's trace is the trajectory of a particular wafer through the cluster tool; that is, a trace is the order in which chambers are visited by a wafer (not necessarily C i+1 after C ⁇ ) .
  • processing sequence is the order of applying processes (recipes) to a wafer. If more than one chamber • performs the same process (parallel chambers) , a given processing sequence may be satisfied by several different traces .
  • a wafer which completes its processing sequence and is returned to the loadlock is said to be processed by the tool.
  • scheduling routine which schedules the movement of wafers through the cluster tool (based on a given processing sequence) is referred to as a "scheduling routine .
  • the steady-state throughput of a tool under scheduling routine A is denoted by S (A) . If n>l then, depending on a given processing sequence, one may consider a number of scheduling routines that fulfill the processing sequence.
  • the routine which maximizes the value of throughput is ⁇ deemed the "optimum" routine and the maximum attainable value of throughput is known as the tool's "capacity.” That is, if A is the set of all possible scheduling routines for a given processing sequence, then A* is optimum if
  • the tool's capacity S(A*) depends on a given processing sequence as well as on chamber and robot parameters within the processing sequence.
  • the problem of finding efficient scheduling routines for a given processing sequence is of considerable practical importance.
  • a trial and error method is used until a schedule is determined that provides a sufficient throughput.
  • the sufficient throughput may not be the best throughput that is possible for a given trace.
  • a first embodiment of the invention uses a set of deterministic rules to compute the various schedules.
  • a schedule is defined as a series of "letters" that form a "word”.
  • Each letter in the word defines a possible positioning of wafers within a cluster tool.
  • the positioning of the wafers within the tool must fulfill the trace, i.e., each letter must follow from a predecessor letter in accordance with a particular set of rules that define the trace .
  • the invention Given a letter (input letter) representing present wafer positions, the invention computes all possible successor wafer positions, i.e., all possible valid successor letters, as well as the total number of successors for the input letter.
  • the invention provides individual "modules" for successor computation for serial traces, parallel traces, and mixed traces.
  • a schedule tree is derived. The schedule tree contains all possible schedules that will fulfill a given trace. Each and every schedule can then be modeled to determine the expected throughput of each schedule. By comparing the throughput associated with each schedule, an optimal schedule or schedules is identified.
  • a method and apparatus performs successive application of three digraph- based processes.
  • a digraph E) is formed to determine a directed edge from vertex u e ⁇ Q,l ⁇ N to vertex ve ⁇ 0,l ⁇ only if wand v differ in at most two coordinates and v is chosen by modifying u according to the rules derived from a cluster tool's operation.
  • N is the number of chambers in the tool
  • E is an edge set
  • u and v are coordinates representing wafer positions in the tool.
  • the invention determines simple cycles in G N TMJ0•' ⁇ J ⁇ ' F ) that correspond to various schedules for moving wafers through the system.
  • Third, by using a throughput simulation program all possible cycles (schedules) are executed and the schedule that yields the highest throughput is chosen as an optimal schedule .
  • Fig. 1 depicts a schematic diagram of a multiple chamber semiconductor wafer processing tool being controlled by a sequencer that operates using scheduling routines generated by a schedule generator in accordance with the present invention
  • Fig. 2 depicts block diagram of schedule generator that performs operative steps in accordance with the present invention
  • Fig. 3 depicts a flow diagram of a 4-chamber serial trace
  • Fig. 4 depicts a flow diagram, of a 4-chamber mixed trace
  • Fig. 5 depicts a flow diagram of a schedule optimization routine of the present invention
  • FIG. 6 depicts a tree diagram representing all possible schedules for a 2-chamber serial trace
  • FIG. 6A depicts a schematic diagram of a 2-chamber serial trace of FIG. 6 showing a wafer in position (1,0);
  • Fig. 7 depicts a tree diagram representing all possible schedules for a 3-chamber serial trace
  • FIG. 7A depicts a schematic diagram of a 3-chamber serial trace of FIG. 7 showing a wafer in position (0,1,0);
  • Fig. 8 depicts a tree diagram representing all possible schedules for a trace: LL-C-- (C 2 , C 3 ) -LL;
  • FIG. 8A depicts a schematic diagram of a 3-chamber mixed trace of FIG. 8 showing a wafer in position (1,1,0);
  • Fig. 9 depicts a tree diagram containing partial schedules as constructed using the present invention;
  • Fig. 10 depicts a flow diagram of a routine for producing all possible schedules for a given trace using a backtracking technique
  • Fig. 11 depicts a chamber occupancy digraph associated with a two chamber serial wafer flow
  • Fig. 11A illustrates wafer positions in a 2 -chamber cluster tool associated with the digraph of Fig. 11
  • Fig. 12 depicts a chamber occupancy digraph associated with a three chamber serial wafer flow
  • Fig. 12A illustrates wafer positioning in a 3-chamber cluster tool associated with the digraph of Fig. 12;
  • Fig. 13 depicts a chamber occupancy digraph associated with a four chamber serial wafer flow
  • Fig. 13A illustrates wafer positioning in a 4-chamber cluster tool associated with the digraph of Fig. 13;
  • Fig. 14 depicts a chamber occupancy digraph associated with a LL-C- L - (C 2 ,C 3 ) -LL wafer flow;
  • Fig. 14A illustrates wafer positioning in a 3-chamber cluster tool associated with the digraph of Fig. 14;
  • Fig. 15 depicts a chamber occupancy digraph associated with a LL- (C 1# C 2 ) -C 3 -LL wafer flow
  • Fig. 15A illustrates wafer positioning in a 3-chamber cluster tool associated with the digraph of Fig. 15;
  • Fig. 16 depicts a digraph having an exponential number of simple cycles
  • Fig. 17 depicts a flow diagram of a recursive enumeration process of the present invention
  • Fig. 18 depicts an adjacency matrix for the digraph of
  • Fig. 19 depicts a flow diagram of a backtrack process for identifying successor vertices to produce a digraph
  • Fig. 20 depicts a chamber occupancy digraph and adjacency matrix for a chamber with a cleaning process
  • Fig. 21 depicts a chamber occupancy digraph and adjacency matrix for a two chamber wafer flow with a cleaning process .
  • FIG. 1 depicts, in part, a schematic diagram of a conventional multiple chamber semiconductor wafer processing tool .
  • the depicted cluster tool 100 is controlled by a sequencer that executes the scheduling routines determined by the present invention.
  • the present invention is embodied in a schedule generator 50 that produces scheduling routines which are executed by the sequencer 136.
  • FIG. 2 depicts a block diagram of the scheduling generator 50 that produces the scheduling routines executed by the sequencer to control the cluster tool 100 of FIG. 1. Additionally, the schedule generator 50 operates to determine an optimal sequencing routine for a given processing sequence and tool configuration. Although, the schedule generator is shown to remotely produce schedules and download one or more schedules to the sequencer, those skilled in the art will understand that the invention could be practiced on a processor within the sequencer.
  • the schedule generator 50 contains a microprocessor 200 as well as memory 202 for storing a schedule generation routine 210, a schedule optimization routine 212 and the scheduling routine (s) generated by routines 210 and 212:
  • the microprocessor 200 cooperates with conventional support circuitry 206 such as power supplies, clock circuits, cache, and the like as well as circuits that assist in executing the software routines.
  • conventional support circuitry 206 such as power supplies, clock circuits, cache, and the like as well as circuits that assist in executing the software routines.
  • it is contemplated that some of the process steps discussed herein as software processes may be implemented within hardware, e.g., as circuitry that cooperates with the microprocessor to perform various process steps.
  • the schedule generator 50 also contains input/output circuitry 208 that forms an interface between conventional input/output (I/O) devices 214 such as a keyboard, mouse, and display as well as an interface to the sequencer.
  • I/O input/output
  • the schedule generator 50 is depicted as a general purpose computer that is programmed to determine scheduling routines in accordance with the present invention, the invention can be implemented in hardware as an application specific integrated circuit (ASIC) . As such, the process steps described herein are intended to be broadly interpreted as being equivalently performed by software, hardware, or a combination thereof.
  • the automatic schedule generator 50 of the present invention executes a schedule generation routine 210 that generates all possible schedules for a given trace.
  • a schedule optimization routine 212 facilitates an automated process of producing an optimum schedule for a given cluster tool using an exhaustive search of all possible schedules.
  • Tool configuration describes physical placement of chambers within a cluster tool.
  • the tool may have chambers C x , C 2 , C 3 and C 4 , a LoadLock (LL) as well as one or more robots .
  • LL LoadLock
  • Process sequence is the order in which processes are applied to a given wafer.
  • P n is the name of the n-th process (e.g., etch) and, V , P 2 , P 3 , (which also may be written as P.— ⁇ -P 2 —P 3 ) is a process sequence.
  • Processing capability of a cluster tool is the result of mapping a required process sequence onto the set of chambers within the tool.
  • the image of this mapping is called a "trace".
  • a process sequence P x —>P 2 —>P 3 may be mapped onto four chambers C ⁇ r C 2 , C 3 and C 4 to yield a trace
  • (C x vC y vC z ) means that wafers can move to either chambers C x or C y or C z , but only into one of the chambers. That is, (C x vC y vC z ) is a stage comprised of three "parallel" chambers.
  • the term "schedule” means a finite and repeatable sequence of wafer and robot movements through the cluster tool. More formally, let S be the set of all possible wafer and robot states . A string of symbols (letters) from a finite set of states S is referred to as a word. Symbols are represented as letters from the alphabet
  • (1,1) are all possible letters in alphabet S and (0,1) (1,1) (0,1) is a word having a length of 3 letters over S.
  • Each letter identifies the instantaneous state of the tool. For example, as is discussed in detail below, a letter may define the particular positioning of a wafer or wafers within a tool at a particular point in the trace. Broadly speaking, whatever the specific alphabet, a schedule S is represented as a word,
  • Traces are available in three different configurations, A trace is parallel if it is comprised of exactly one stage; a trace is serial if each stage has exactly one chamber and a trace is mixed if it is neither serial nor parallel.
  • Figs. 3 and 4 schematically depict 4-stage serial and mixed traces, respectively .
  • Fig. 5 depicts a high level flow diagram of the schedule optimization routine 212.
  • the optimization routine contains a schedule generation routine 210 that produces all possible schedules in an alphabet induced by a given trace.
  • Routine 212 is an automated process that performs the following steps : a) Input a trace L (step 500) , b) Produce all possible schedules over L (routine 210) using a two step process, where the first step (step 508) generates all possible successor positions (letters) to which a wafer can be moved from a present position (letter) and the second step (step 510) uses a backtracking technique to change wafer positions such that other successor positions (letters) can be computed by step 508, c) Evaluate each of the schedules in (b) with respect to throughput (for a given set of robot and process parameters) (step 504) , d) Record a schedule or a set of schedules which have the highest throughput for the given trace L (step
  • step (c) requires a throughput simulation program, for computational efficiency, steps (a) , (b) and (d) are generally incorporated into the simulation program.
  • steps (a) , (b) and (d) are generally incorporated into the simulation program.
  • a plurality of embodiments of the present invention are discussed below in Sections B, C, D and E of this disclosure. Specifically, the definitions of a schedule in a ⁇ 0,l ⁇ n alphabet, rules for generating successors of a given letter, and modules needed for computation of successors are given in Section B for a serial trace and Section C for mixed and parallel traces. In Section D, these processes are extended to include robot utilization in the computations. Lastly, a generalized backtracking routine for generating all possible schedules from a given trace, applicable to any trace with or without a robot, is presented in Section E. B. Schedule Generation for Serial Traces Using n-tuples
  • a schedule S is a finite string of binary n-tuples
  • FIG. 6 illustrates all possible schedules available (i.e., two schedules) in a 2-chamber serial trace.
  • FIG. 6A depicts a schematic diagram of the 2-chamber serial trace of FIG. 6 having a wafer in position represented by the 2-tuple (1,0) . These n-tuples are referred to herein as the coordinates of wafer positioning. From position (1,0), the schedule of FIG. 6 dictates that the wafer is next moved to a position represented by the 2-tuple (0,1), i.e., a wafer is now in chamber C 2 and no wafer is in chamber C x .
  • each 2-tuple represents a set of possible positions for a wafer or wafers that validly fulfill a step in the trace.
  • FIG. 7 illustrates the seven possible schedules available in a 3-chamber serial trace
  • FIG. 7A depicts a schematic diagram of the trace of FIG. 7 having a wafer positioning represented by the 3-tuple (0,1,0) . From Fig. 7, the strings
  • S p (1,1,1) (1,1,0) (1,0,1) (0,1,1,) (1,1,1)
  • S w (1,0,0) (0,1,0) (0,0,1) (0,0,0) (1,0,0)
  • S x (1,0,1) (0,1,1) (0,1,0) (1,1,0) (1,0,1) .
  • the 2 n binary n-tuples are regarded as letters from the alphabet
  • a finite string of letters is referred to as a word.
  • strings S p , S w , and S x are all 5-letter words.
  • a partial schedule S of 'length k is a k-letter word S (1)
  • S (2) ... S (k) in which next letter S(i+1) depends only on the previous letter S(i), i l, 2 , ... ,k-l, and is built according to rules (s x ) , (s 2 ) , and (s 3 ) stated above.
  • all letters in a partial schedule are different.
  • W(i) M ⁇
  • u x u 2 . .. w k is a partial schedule, then u 1 u 2 . . .
  • M k w k+1 is also a schedule (partial or full) provided « k+1 is obtained from w k according to rules ( s x ) , (s 2 ) , and (s 3 ) .
  • a given letter u k may have anywhere from 1 to [n/2 ] + 1 successors ⁇ k+1 .
  • the number of successors (variable nmb below) is easily determined by the following function:
  • SerCount ( -- k ) represents the number of successors of w k in a serial n-chamber trace. Since, in an exhaustive search, all the successors are examined, the foregoing pseudo-code determines the total number of successor letters that must be computed to complete an exhaustive search.
  • Generating all SerCount ( u ) successors of a given letter u is not particularly difficult.
  • each successor of u is generated, it is stored in a binary matrix Z that has SerCount ( u ) rows and (n+1) columns.
  • the last column of Z is reserved for a Boolean variable that is set to true if the successor was used in a partial schedule and is set to false if the successor was not used. This entry is used later in the backtracking routine (discussed below with reference to FIG. 10) that generates all possible schedules for a given trace.
  • the successors of a given letter are determined by the following function.
  • Function copy ( u , v ) returns letter u that is a replica of letter v .
  • This manner of implementing rules (s x ) , (s 2 ) , and (s 3 ) , in which the routine first copies u into v and then modifies v, is not inefficient because u and v differ in at most two coordinates.
  • Function store ( v , Z) copies letter v into a proper row of matrix Z. Note that in the above module, the routine copies a binary n-tuple twice; clearly, in implementation, the routine copies the successor of u (slightly altered n-tuple u ) into the proper row of matrix Z directly.
  • the pseudo-code uses the foregoing pseudo-code and given a letter u in a serial trace, the pseudo-code generates all possible successor letters of u and stores them in matrix Z .
  • the pseudo-code produces a string of valid successor letters, e.g., letters (1,0,1), (0,1,0), (1,1,0), and (0,0,0).
  • a different valid set of successors is produced, e.g., letter (0,1,0) may produce letters (1,1,0), (1,0,1), (1,0,0) and (0,1,0).
  • FIG. 4 depicts an illustrative mixed trace containing four stages with six chambers , where chambers C ⁇ and C 4 are serial and chamber pairs C 2 (a) , C 2 (b) and C 3 (a), C 3 (b) are parallel.
  • an n- chamber mixed trace is comprised of k successive stages, F 1 , F 2' ⁇ • •
  • l,2,...,n are positions in a binary n- tuple x that corresponds to chambers C- [ _,C2, ⁇ • • ,C n , respectively, then positions 1,2,..., .Ej corresponds to chambers in stage 1, positions
  • chamber C j _ belongs to stage j -, then position i in the corresponding associated binary n-tuple x belongs to F ⁇ - and ⁇ GF ⁇ . (while, in fact, i is one of the consecutive
  • a schedule is a finite string of binary n-tuples which starts and ends with the same binary n-tuple. This is the only repeated letter in the word.
  • v is a successor of u
  • u and v differ in at most two coordinates and the following rules define the relationship of u and v :
  • M,
  • nmb: nmb+l; return (nmb) end;
  • a function that generates and stores all successors of a given letter in a mixed trace is:
  • FIG. 8 depicts an illustrative schedule tree for a 3-chamber mixed trace, (e.g., LL—>C 1 — > (C 2 vC 3 ) —>LL) , where the successors of a particular letter are determined using the MixGenerator ( u ) pseudo-code.
  • FIG. 8A depicts a schematic diagram of the trace of FIG. 8 having wafers positioned in position (1,1,0) .
  • 3[z] l, if C_ contains a wafer.
  • the first n coordinates of x are from ⁇ 0,1 ⁇ .
  • the robot position is described by the last coordinate of x , i.e., x 3 in the 3-tuple (x 1 ,x 2 ;x 3 ), where x ⁇ and x 2 are wafer coordinates and x 3 is a robot coordinate.
  • S 2 is comprised of twelve 3-tuples, namely,
  • S 2 ⁇ (0,0;0), (0,0;1), (0,0; 2); (0,1;0), (0,1;1), (0,1; 2); (1,0;0), (1,0;1), (1,0;2); (1,1;0), (1,1;1), (1,1;2) ⁇ .
  • n+1 -tuples are referred to as letters from the alphabet S n .
  • a word is a finite string of letters from S n .
  • abcdaxy is a word, but not a schedule .
  • a schedule S is a word (a string of the above described (n+1) -tuples) ,
  • any two consecutive letters u and v (where v is a successor of u ) differ in at most three coordinates and are related in accordance with the following rules:
  • rules (a) , (b) , and (c) above are, in fact rules (s-t_),(s 2 ), and (S3), respectively, when the robot is already prepositioned to move a wafer, while (d) , (e) , and (f) correspond to prepositioning the robot for moves defined by rules (a) , (b) , and (c) , respectively.
  • a routine that calculates the number of successors of a given letter as well as finds and stores these successors is designed in a similar manner as in the previous cases for mixed and serial traces (this time by following the steps (a) through (f) ) .
  • the new functions used are modifications of SerCount ( u ) and
  • SerGenerator ( u ) (or MixCount ( u ) and MixGenerator ( u ) ) .
  • SerCount ( u ) (or MixCount ( u ) and MixGenerator ( u ) ) .
  • SerCount ( u ) (or MixCount ( u ) and MixGenerator ( u ) ) .
  • SerGenerator ( u ) (or MixCount ( u ) and MixGenerator ( u ) ) .
  • Backtracking algorithms use special problem-tailored techniques to systematically explore implicitly directed graphs (usually trees) . Such algorithms are well known in the art.
  • a backtracking algorithm is used in conjunction with one or more of the previously discussed successor generation routines (e.g., SerGenerator ( z7 ) or MixGenerator ( u ) ) to produce every possible schedule given a particular trace.
  • the routine either prints or stores the full schedule u ⁇ 7 J+ ... j -. + -
  • the routine removes z and looks at another unused successor of « ⁇ ... If there are no unused successors of u - ⁇ . the routine goes back (backtrack) and looks at unused successors of - ⁇ - and so on, until the routine returns to the starting letter u - ⁇ .
  • the routine contains the following sequence of steps :
  • Step 3 Find a successor letter (of the last letter -7 ⁇ ., in the schedule) which was not used, append it to the partial schedule and go to Step 2. If there are no unused successors, go to step 5.
  • Step 5. Print or store the schedule and go to Step 5. 5. If there are no more schedules, then STOP. Else, go to Step 6.
  • the routine builds a tree whose nodes are letters . If x is such a node, the children of x axe successors of a letter x and, for serial traces, there are exactly
  • a basic schedule generator routine can be summarized by the following five steps:
  • step 1 the routine initializes the schedule, S, and the level of the search tree, L.
  • L must be initialized to 1.
  • the routine uses a letter that has only one successor.
  • a letter 0 corresponds to a situation in which all chambers are empty (i.e., the tool has just begun processing wafers) .
  • Function cnt ( x ) returns the number of successors of a given letter x .
  • the routine finds, stores and marks unused successors of x .
  • a successor may be a record with two fields: the first field is the actual letter, while the second field is a Boolean variable with value true if the successor was not used in a particular partial schedule S and value false otherwise. (Or the routine may use a matrix representation for the list of successors as described in Sections C and D above . ) '
  • step 3 one of the unused successors of the last letter x is appended to the partial schedule S, the length of schedule L is increased by 1 and the number of unused successors of x is decreased by 1. (There will always be at least one successor to any given letter.)
  • step 4 the routine checks if S is a full schedule by comparing the newly added (the last) letter S (L) with all previous letters S (1) , S (2) , ... , S (L-l) . (That should be accomplished every time a new letter is appended to a partial schedule.) If S(L) is a repeated letter, the routine prints (stores) the schedule; else, the routine continues with building the schedule.
  • the routine When a partial schedule becomes a full schedule, S(1)S (2) ...S (L) , after storing the schedule, the routine removes the last letter S(L) and look for some other unused successor of S(L-l) . If there are some unused successors, the routine appends a successor to the partial schedule, finds its successors, appends one of these successors and so on. If there are no successors, the routine removes S(L-l) from S and looks for unused successors of S(L-2) and so on.
  • the routine above is valid for any representation of the scheduling problem. That is, either serial or mixed traces with letters from ⁇ 0,l ⁇ n or either of these traces with robot position being part of the model (and thus alphabet from ⁇ 0,l ⁇ n x ⁇ 0,l...,n ⁇ ).
  • functions that count and generate successors of a given letter are different each time.
  • Fig. 10 depicts a flow diagram of a schedule generation routine 1000 that operates as generally discussed above.
  • the routine 1000 begins at step 1002 by initializing the schedule, e.g., setting an initial letter to an n-tuple (n-string) of zeros.
  • the routine finds, stores and marks all unused successors of the last letter in a partial schedule.
  • the successor letters are determined using the pseudo-code routines SerGenerator, ParGenerator and MixGenerator and the number of successor letters for each letter is determined using SerCount, ParCount and MixCount.
  • these pseudo-code routines must be appropriately modified to accommodate the expanded letters and the modify rules of successor generation.
  • step 1006 the routine appends an unused successor of the last letter to a partial schedule as well as increases the length of the schedule by one and decreases the number of unused successors by one.
  • the routine queries, at step 1008, whether the last letter of the partial trace has been reached. If the query is negatively answered, the routine proceeds along the NO path to step 1004. If the query is affirmatively answered, the routine proceeds to step 1010 where the schedule is either printed or stored.
  • Steps 1012, 1014, 1016 and 1018 represent a backtracking process.
  • the routine removes the last letter of the schedule to produce a partial schedule and reduce the schedule length by one.
  • the routine queries whether the length of schedule is one. If the query is affirmatively answered, the routine stops at step 1016. However, if the query is negatively answered, the routine proceeds to step 1018.
  • the routine queries whether there is an unused successor to the last letter. If the query is negatively answered, the routine proceeds along the NO path to step 1012. Otherwise, the routine proceeds to step 1020 where an unused successor is appended to the partial schedule. The routine then returns to step 1004.
  • each schedule is used by the model to predict a throughput for that schedule .
  • the throughputs for all the schedules are compared to find the schedule having the highest (best) throughput.
  • the schedule with the highest throughput is deemed optimal and is used to control the sequencer.
  • the throughput model may be executed upon the sequencer computer or, more likely, it is executed on a remote computer, and the optimal schedule is downloaded to the sequencer .
  • the schedule generation process is performed using digraphs that represent a plurality of schedules that are available for a particular cluster tool configuration.
  • C v C 2 n chambers in the system
  • C n n chambers in the system
  • This schedule is defined as a finite string of binary n-tuples,
  • the length of a schedule is the number of different binary vectors comprising it.
  • vector (0101) has three successors, namely (1101) and (0100) and (0011) . They are obtained by applying 5j and s 2 and s 3 , respectively.
  • FIG. 11A, 12A, and 13A Diagrams of G 2 ,G 3 and G 4 are shown in Figs. 11, 12 and 13, respectively.
  • Figs. 11A, 12A, and 13A illustrate wafer positioning within the cluster tool, where an empty circle represents an empty chamber and a circle containing a dot represents a chamber containing a wafer.
  • f(n) ⁇ 1(C)
  • Z(C)denotes the length of a cycle .
  • a schedule is then a finite string x- - -uv -- -x corresponding to a cycle in G ⁇ (V,E)that starts and ends at x .
  • f(n) is the total number of schedules. If v is the immediate successor of zzin the schedule, then zzand v differ in at most two coordinates, and v must be chosen according to the above rules (s v s 2 ,sf) . These rules give rise to the requirements for (zz,v) E(G Thread) .
  • an n-chamber mixed wafer flow is comprised of k successive stages (or families) , F 1 ,F 2 ,...,F k , where k ⁇ n. .
  • 1,2,...,/z are positions in a binary n-tuple x that correspond to chambers C v C 2 ,...,C n , respectively, then make positions 1,2,.. correspond to chambers in stage (family) 1, positions
  • chamber C t belongs to stage (family) F t
  • Any such cycle is a union of simple cycles and thus its corresponding throughput is the sum of throughputs of the simple cycles. It then follows from the fact that the sum of any M non-negative numbers (throughputs) is larger than M times the smallest number (throughput) .
  • the problem of finding an optimum schedule calls for finding all simple cycles in G( ⁇ 0,1 ⁇ ",E) whose vertices are occupancy-vectors from ⁇ 0,l ⁇ "and whose edges are defined by either rules. That is, for any pair of vertices e ⁇ 0,l ⁇ " there is an edge from x to y if and only if y e s(x) .
  • the schedules then correspond to simple cycles in G( ⁇ 0,l ⁇ ",EJ .
  • the number of cycles in a digraph can be exponential in the number of vertices. For example, it is known that the complete digraph of n vertices and (n- 1) edges contains
  • Fig. 17 depicts a flow diagram of a recursive enumeration process 1700. The process begins at step 102 and proceeds to step 1704. At step 1704, a search begins at vertex s by building a directed path (s,v v v 2 ,...,v k ) at step 1706, such that v t > s for l ⁇ i ⁇ k . A cycle is identified
  • step 1710 the process 1700 proceeds through query 1710 to the previous vertex v k _ x at step 1716 and attempts to list cycles from that vertex and so on. This process is continued through step 1710 until the process
  • the process 1700 To prevent traversing cycles that originate at a vertex v ' during the search for cycles rooted at s , the process 1700 must exclude all vertices on the current path (except s ) as extensions of that path. A vertex v will be marked as unavailable by setting avail(v) to. false as soon as v is appended to the current path. The vertex v will remain unavailable at least until the process 1700 has backed up past v to the previous vertex on the current path. If the current path up to vertex v did not lead to a cycle rooted at, s , v will remain unavailable for awhile even after the process backs up past it. This prevents searching for cycles in parts of the digraph on
  • a vertex v is added to the top of the stack before the search continues (by a recursive call) and is removed from the top of the stack in backing up (on return from the recursive call) .
  • the vertex is marked unavailable as the vertex is put on the stack and, if the vertex leads to a cycle rooted at s , made available again after the vertex is removed from the stack. If the process did not lead to a cycle rooted at s , then the cycle remains temporarily unavailable.
  • a record is kept of the predecessors of all unavailable vertices that are not on the current path by maintaining sets B(w) for each w ⁇ V :
  • v k+l s
  • a new cycle (s,v 1 ,v 2 ,...,v k ,s) has been generated.
  • the process outputs (e.g., print) the cycle and then set flag ⁇ — trzze to indicate that a cycle (rooted at s ) going through v k has been found.
  • a back edge of a digraph generated in a depth-first search corresponds to a simple cycle.
  • a forward edge may correspond to a "short-cut" of a cycle.
  • a cross edge in the same tree) may correspond to one or more other simple cycles .
  • edges are specified by the successor relationship as
  • the set E in G( ⁇ 0,l ⁇ ,E] has five edges, namely ((00),
  • D (x,y) l if and only if y e s(x) .
  • a string u 1 u 2 ---u k u M is a cycle if it is built according to rules for successor occupancy-vector, all vertices u , ' ⁇ i 2 ,...,u k+1 are different, and the successor of u k+1 is the starting vertex zz, . If happens to be a simple- cycle, the process stores the cycle (or print it) , removes the vertex u k from the cycle and looks at some other unused successor of u k . If there is such a successor, say z , the process checks if u l u 2 ---u k z is a cycle.
  • Fig. 19 depicts a flow diagram of the backtrack process 1900. The process performs the following sequence of steps:
  • Step 1902. (Initialize.) Choose the first vertex zz ⁇ of a cycle and go to Step 1904. Step 1904. If ⁇ , 2 -- -u k is not a cycle, go to Step 1906. Else, go to Step 1908.
  • Step 1906 Find a successor vertex (of the last vertex u k in the cycle) which was not used, go to step 1908. If there are no unused successors, go to Step 1912. Step 1908. Append the vertex to the path and go to Step
  • Step 1908. Output (print or store) the cycle and go to
  • Step 1912. Step 1912. If there are no more vertices, then STOP at step 1914. Else, go to Step 1916. Step 1916. (Backtrack.) Remove the last visited vertex from the cycle and go to Step 1906.
  • the process 1900 must ensure that the process doesn't produce duplicate cycles in Step 1908 as well as that the process have produced all possible cycles.
  • the former is performed in Step 19010 where the process appends only an unused successor of the last vertex to the path.
  • the latter is ensured by the proper termination condition (i.e., the process is at u and there are no unused successors of u ) .
  • the process needs to the backtrack search for each vertex from ⁇ 0,1 ⁇ " . If a(x) is the number of cycles that start with the vertex x , the total number of cycles is T_ (x) .
  • a chamber When chamber cleaning process is taken into account in the schedule generation process, a chamber has three states: 0 (empty chamber) , 1 (wafer in chamber) , and C (chamber undergoing a cleaning process) . Only an empty chamber can initiate a cleaning process . When a cleaning process is over, a chamber either remains empty or a wafer is put in.
  • Fig. 20 depicts digraph G,( ⁇ 0,1,C ⁇ ,E) that takes account of cleaning processes.
  • Fig. 20 also depicts the digraph's corresponding adjacency matrix and an illustrative wafer positioning.
  • Fig. 21 depicting a digraph, an adjacency matrix and illustrative wafer positioning in a cluster tool for a 2-chamber serial wafer flow with chamber clean.
  • Fig. 21 depicting a digraph, an adjacency matrix and illustrative wafer positioning in a cluster tool for a 2-chamber serial wafer flow with chamber clean.
  • the associated 9-vertex digraph there are now seven cycles of length two, 4 cycles of length three, two cycles of length five, three cycles of length six, one cycle of length seven and one of length eight .

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Abstract

L'invention porte sur un procédé et un appareil de génération de programmes s'appliquant à une plaquette dans un dispositif de traitement multichambre de plaquettes à semi-conducteurs. Ce procédé consiste à reproduire un tracé formant une série de chambres dans lesquelles passe une plaquette lors de son traitement par le dispositif ; initialiser un générateur de séquences avec un noeud définissant le positionnement initial de la plaquette dans le dispositif ; générer tous les noeuds descendants pour produire une série de vecteurs interconnectant les noeuds qui, réunis, produisent un cycle représentant un programme. Tous les éventuels programmes sont analysés pour déterminer celui qui aura le rendement le plus élevé.
PCT/US2002/002378 2001-01-26 2002-01-28 Procede et appareil de generation automatique de programmes pour traitement de plaquettes dans un dispositif de traitement multichambre de plaquettes a semi-conducteurs WO2002059704A2 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1826645A1 (fr) * 2006-02-25 2007-08-29 MTU Aero Engines GmbH Méthode pour la génération de chaînes de procédé

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TWI426459B (zh) * 2007-10-26 2014-02-11 Hon Hai Prec Ind Co Ltd 自動識別模具出庫和入庫動作的系統及方法

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US6074443A (en) * 1996-10-21 2000-06-13 Applied Materials, Inc. Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot
EP1058172A2 (fr) * 1999-06-01 2000-12-06 Applied Materials, Inc. Techniques de traitement de semi-conducteurs
WO2000079355A1 (fr) * 1999-06-22 2000-12-28 Brooks Automation, Inc. Unite de commande sequentielle utilisee dans la fabrication d'elements de micro-electroniques

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US5444632A (en) * 1994-04-28 1995-08-22 Texas Instruments Incorporated Apparatus and method for controlling and scheduling processing machines
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EP1058172A2 (fr) * 1999-06-01 2000-12-06 Applied Materials, Inc. Techniques de traitement de semi-conducteurs
WO2000079355A1 (fr) * 1999-06-22 2000-12-28 Brooks Automation, Inc. Unite de commande sequentielle utilisee dans la fabrication d'elements de micro-electroniques

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1826645A1 (fr) * 2006-02-25 2007-08-29 MTU Aero Engines GmbH Méthode pour la génération de chaînes de procédé

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